--initial commit

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc_ex.c

@@ -0,0 +1,384 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_adc_ex.c
+  * @author  MCD Application Team
+  * @brief   This file provides firmware functions to manage the following
+  *          functionalities of the Analog to Digital Converter (ADC)
+  *          peripheral:
+  *           + Peripheral Control functions
+  *          Other functions (generic functions) are available in file
+  *          "stm32g0xx_hal_adc.c".
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  [..]
+  (@) Sections "ADC peripheral features" and "How to use this driver" are
+      available in file of generic functions "stm32g0xx_hal_adc.c".
+  [..]
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal.h"
+
+/** @addtogroup STM32G0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup ADCEx ADCEx
+  * @brief ADC Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup ADCEx_Private_Constants ADC Extended Private Constants
+  * @{
+  */
+
+/* Fixed timeout value for ADC calibration.                                   */
+/* Values defined to be higher than worst cases: maximum ratio between ADC    */
+/* and CPU clock frequencies.                                                 */
+/* Example of profile low frequency : ADC frequency at 31.25kHz (ADC clock    */
+/* source PLL 8MHz, ADC clock prescaler 256), CPU frequency 52MHz.            */
+/* Calibration time max = 116 / fADC (refer to datasheet)                     */
+/*                      = 193 024 CPU cycles                                  */
+#define ADC_CALIBRATION_TIMEOUT         (193024UL)   /*!< ADC calibration time-out value (unit: CPU cycles) */
+#define ADC_DISABLE_TIMEOUT             (2UL)
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
+  * @brief    Extended IO operation functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+
+      (+) Perform the ADC self-calibration.
+      (+) Get calibration factors.
+      (+) Set calibration factors.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Perform an ADC automatic self-calibration
+  *         Calibration prerequisite: ADC must be disabled (execute this
+  *         function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
+  * @note   Calibration factor can be read after calibration, using function
+  *         HAL_ADC_GetValue() (value on 7 bits: from DR[6;0]).
+  * @param  hadc       ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+  __IO uint32_t wait_loop_index = 0UL;
+  uint32_t backup_setting_cfgr1;
+  uint32_t calibration_index;
+  uint32_t calibration_factor_accumulated = 0;
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  __HAL_LOCK(hadc);
+
+  /* Calibration prerequisite: ADC must be disabled. */
+
+  /* Disable the ADC (if not already disabled) */
+  tmp_hal_status = ADC_Disable(hadc);
+
+  /* Check if ADC is effectively disabled */
+  if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+  {
+    /* Set ADC state */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_REG_BUSY,
+                      HAL_ADC_STATE_BUSY_INTERNAL);
+
+    /* Manage settings impacting calibration                                  */
+    /* - Disable ADC mode auto power-off                                      */
+    /* - Disable ADC DMA transfer request during calibration                  */
+    /* Note: Specificity of this STM32 series: Calibration factor is          */
+    /*       available in data register and also transferred by DMA.          */
+    /*       To not insert ADC calibration factor among ADC conversion data   */
+    /*       in array variable, DMA transfer must be disabled during          */
+    /*       calibration.                                                     */
+    backup_setting_cfgr1 = READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG | ADC_CFGR1_AUTOFF);
+    CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG | ADC_CFGR1_AUTOFF);
+
+    /* ADC calibration procedure */
+    /* Note: Perform an averaging of 8 calibrations for optimized accuracy */
+    for (calibration_index = 0UL; calibration_index < 8UL; calibration_index++)
+    {
+      /* Start ADC calibration */
+      LL_ADC_StartCalibration(hadc->Instance);
+
+      /* Wait for calibration completion */
+      while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
+      {
+        wait_loop_index++;
+        if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
+        {
+          /* Update ADC state machine to error */
+          ADC_STATE_CLR_SET(hadc->State,
+                            HAL_ADC_STATE_BUSY_INTERNAL,
+                            HAL_ADC_STATE_ERROR_INTERNAL);
+
+          __HAL_UNLOCK(hadc);
+
+          return HAL_ERROR;
+        }
+      }
+
+      calibration_factor_accumulated += LL_ADC_GetCalibrationFactor(hadc->Instance);
+    }
+    /* Compute average */
+    calibration_factor_accumulated /= calibration_index;
+    /* Apply calibration factor */
+    LL_ADC_Enable(hadc->Instance);
+    LL_ADC_SetCalibrationFactor(hadc->Instance, calibration_factor_accumulated);
+    LL_ADC_Disable(hadc->Instance);
+
+    /* Wait for ADC effectively disabled before changing configuration */
+    /* Get tick count */
+    tickstart = HAL_GetTick();
+
+    while (LL_ADC_IsEnabled(hadc->Instance) != 0UL)
+    {
+      if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if (LL_ADC_IsEnabled(hadc->Instance) != 0UL)
+        {
+          /* Update ADC state machine to error */
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+          /* Set ADC error code to ADC peripheral internal error */
+          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+          return HAL_ERROR;
+        }
+      }
+    }
+
+    /* Restore configuration after calibration */
+    SET_BIT(hadc->Instance->CFGR1, backup_setting_cfgr1);
+
+    /* Set ADC state */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_BUSY_INTERNAL,
+                      HAL_ADC_STATE_READY);
+  }
+  else
+  {
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+    /* Note: No need to update variable "tmp_hal_status" here: already set    */
+    /*       to state "HAL_ERROR" by function disabling the ADC.              */
+  }
+
+  __HAL_UNLOCK(hadc);
+
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Get the calibration factor.
+  * @param hadc ADC handle.
+  * @retval Calibration value.
+  */
+uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Return the selected ADC calibration value */
+  return ((hadc->Instance->CALFACT) & 0x0000007FU);
+}
+
+/**
+  * @brief  Set the calibration factor to overwrite automatic conversion result.
+  *         ADC must be enabled and no conversion is ongoing.
+  * @param hadc ADC handle
+  * @param CalibrationFactor Calibration factor (coded on 7 bits maximum)
+  * @retval HAL state
+  */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t CalibrationFactor)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  uint32_t tmp_adc_is_conversion_on_going_regular;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_CALFACT(CalibrationFactor));
+
+  __HAL_LOCK(hadc);
+
+  /* Verification of hardware constraints before modifying the calibration    */
+  /* factors register: ADC must be enabled, no conversion on going.           */
+  tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+
+  if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
+      && (tmp_adc_is_conversion_on_going_regular == 0UL)
+     )
+  {
+    hadc->Instance->CALFACT &= ~ADC_CALFACT_CALFACT;
+    hadc->Instance->CALFACT |= CalibrationFactor;
+  }
+  else
+  {
+    /* Update ADC state machine */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+    /* Update ADC error code */
+    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+    /* Update ADC state machine to error */
+    tmp_hal_status = HAL_ERROR;
+  }
+
+  __HAL_UNLOCK(hadc);
+
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Analog watchdog 2 callback in non-blocking mode.
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file.
+  */
+}
+
+/**
+  * @brief  Analog watchdog 3 callback in non-blocking mode.
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file.
+  */
+}
+
+
+/**
+  * @brief  End Of Sampling callback in non-blocking mode.
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file.
+  */
+}
+
+/**
+  * @brief  ADC channel configuration ready callback in non-blocking mode.
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADCEx_ChannelConfigReadyCallback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADCEx_ChannelConfigReadyCallback must be implemented in the user file.
+  */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Disable ADC voltage regulator.
+  * @note   Disabling voltage regulator allows to save power. This operation can
+  *         be carried out only when ADC is disabled.
+  * @note   To enable again the voltage regulator, the user is expected to
+  *         resort to HAL_ADC_Init() API.
+  * @param hadc ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
+  if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+  {
+    LL_ADC_DisableInternalRegulator(hadc->Instance);
+    tmp_hal_status = HAL_OK;
+  }
+  else
+  {
+    tmp_hal_status = HAL_ERROR;
+  }
+
+  return tmp_hal_status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cec.c

@@ -0,0 +1,997 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_cec.c
+  * @author  MCD Application Team
+  * @brief   CEC HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the High Definition Multimedia Interface
+  *          Consumer Electronics Control Peripheral (CEC).
+  *           + Initialization and de-initialization function
+  *           + IO operation function
+  *           + Peripheral Control function
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+ ===============================================================================
+                        ##### How to use this driver #####
+ ===============================================================================
+    [..]
+    The CEC HAL driver can be used as follow:
+
+    (#) Declare a CEC_HandleTypeDef handle structure.
+    (#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:
+        (##) Enable the CEC interface clock.
+        (##) CEC pins configuration:
+            (+++) Enable the clock for the CEC GPIOs.
+            (+++) Configure these CEC pins as alternate function pull-up.
+        (##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()
+             and HAL_CEC_Receive_IT() APIs):
+            (+++) Configure the CEC interrupt priority.
+            (+++) Enable the NVIC CEC IRQ handle.
+            (+++) The specific CEC interrupts (Transmission complete interrupt,
+                  RXNE interrupt and Error Interrupts) will be managed using the macros
+                  __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
+                  and receive process.
+
+    (#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in
+        in case of Bit Rising Error, Error-Bit generation conditions, device logical
+        address and Listen mode in the hcec Init structure.
+
+    (#) Initialize the CEC registers by calling the HAL_CEC_Init() API.
+
+  [..]
+    (@) This API (HAL_CEC_Init()) configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
+        by calling the customed HAL_CEC_MspInit() API.
+  *** Callback registration ***
+  =============================================
+
+  The compilation define  USE_HAL_CEC_REGISTER_CALLBACKS when set to 1
+  allows the user to configure dynamically the driver callbacks.
+  Use Functions HAL_CEC_RegisterCallback() or HAL_CEC_RegisterXXXCallback()
+  to register an interrupt callback.
+
+  Function HAL_CEC_RegisterCallback() allows to register following callbacks:
+    (+) TxCpltCallback     : Tx Transfer completed callback.
+    (+) ErrorCallback      : callback for error detection.
+    (+) MspInitCallback    : CEC MspInit.
+    (+) MspDeInitCallback  : CEC MspDeInit.
+  This function takes as parameters the HAL peripheral handle, the Callback ID
+  and a pointer to the user callback function.
+
+  For specific callback HAL_CEC_RxCpltCallback use dedicated register callbacks
+  HAL_CEC_RegisterRxCpltCallback().
+
+  Use function HAL_CEC_UnRegisterCallback() to reset a callback to the default
+  weak function.
+  HAL_CEC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+  and the Callback ID.
+  This function allows to reset following callbacks:
+    (+) TxCpltCallback     : Tx Transfer completed callback.
+    (+) ErrorCallback      : callback for error detection.
+    (+) MspInitCallback    : CEC MspInit.
+    (+) MspDeInitCallback  : CEC MspDeInit.
+
+  For callback HAL_CEC_RxCpltCallback use dedicated unregister callback :
+  HAL_CEC_UnRegisterRxCpltCallback().
+
+  By default, after the HAL_CEC_Init() and when the state is HAL_CEC_STATE_RESET
+  all callbacks are set to the corresponding weak functions :
+  examples HAL_CEC_TxCpltCallback() , HAL_CEC_RxCpltCallback().
+  Exception done for MspInit and MspDeInit functions that are
+  reset to the legacy weak function in the HAL_CEC_Init()/ HAL_CEC_DeInit() only when
+  these callbacks are null (not registered beforehand).
+  if not, MspInit or MspDeInit are not null, the HAL_CEC_Init() / HAL_CEC_DeInit()
+  keep and use the user MspInit/MspDeInit functions (registered beforehand)
+
+  Callbacks can be registered/unregistered in HAL_CEC_STATE_READY state only.
+  Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
+  in HAL_CEC_STATE_READY or HAL_CEC_STATE_RESET state,
+  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+  In that case first register the MspInit/MspDeInit user callbacks
+  using HAL_CEC_RegisterCallback() before calling HAL_CEC_DeInit()
+  or HAL_CEC_Init() function.
+
+  When the compilation define USE_HAL_CEC_REGISTER_CALLBACKS is set to 0 or
+  not defined, the callback registration feature is not available and all callbacks
+  are set to the corresponding weak functions.
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal.h"
+
+/** @addtogroup STM32G0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup CEC CEC
+  * @brief HAL CEC module driver
+  * @{
+  */
+#ifdef HAL_CEC_MODULE_ENABLED
+#if defined (CEC)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup CEC_Private_Constants CEC Private Constants
+  * @{
+  */
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup CEC_Private_Functions CEC Private Functions
+  * @{
+  */
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup CEC_Exported_Functions CEC Exported Functions
+  * @{
+  */
+
+/** @defgroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to initialize the CEC
+      (+) The following parameters need to be configured:
+        (++) SignalFreeTime
+        (++) Tolerance
+        (++) BRERxStop                 (RX stopped or not upon Bit Rising Error)
+        (++) BREErrorBitGen            (Error-Bit generation in case of Bit Rising Error)
+        (++) LBPEErrorBitGen           (Error-Bit generation in case of Long Bit Period Error)
+        (++) BroadcastMsgNoErrorBitGen (Error-bit generation in case of broadcast message error)
+        (++) SignalFreeTimeOption      (SFT Timer start definition)
+        (++) OwnAddress                (CEC device address)
+        (++) ListenMode
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Initializes the CEC mode according to the specified
+  *         parameters in the CEC_InitTypeDef and creates the associated handle .
+  * @param hcec CEC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
+{
+  /* Check the CEC handle allocation */
+  if ((hcec == NULL) || (hcec->Init.RxBuffer == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
+  assert_param(IS_CEC_SIGNALFREETIME(hcec->Init.SignalFreeTime));
+  assert_param(IS_CEC_TOLERANCE(hcec->Init.Tolerance));
+  assert_param(IS_CEC_BRERXSTOP(hcec->Init.BRERxStop));
+  assert_param(IS_CEC_BREERRORBITGEN(hcec->Init.BREErrorBitGen));
+  assert_param(IS_CEC_LBPEERRORBITGEN(hcec->Init.LBPEErrorBitGen));
+  assert_param(IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(hcec->Init.BroadcastMsgNoErrorBitGen));
+  assert_param(IS_CEC_SFTOP(hcec->Init.SignalFreeTimeOption));
+  assert_param(IS_CEC_LISTENING_MODE(hcec->Init.ListenMode));
+  assert_param(IS_CEC_OWN_ADDRESS(hcec->Init.OwnAddress));
+
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
+  if (hcec->gState == HAL_CEC_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hcec->Lock = HAL_UNLOCKED;
+
+    hcec->TxCpltCallback  = HAL_CEC_TxCpltCallback;  /* Legacy weak TxCpltCallback  */
+    hcec->RxCpltCallback = HAL_CEC_RxCpltCallback;   /* Legacy weak RxCpltCallback */
+    hcec->ErrorCallback = HAL_CEC_ErrorCallback;     /* Legacy weak ErrorCallback */
+
+    if (hcec->MspInitCallback == NULL)
+    {
+      hcec->MspInitCallback = HAL_CEC_MspInit; /* Legacy weak MspInit  */
+    }
+
+    /* Init the low level hardware */
+    hcec->MspInitCallback(hcec);
+  }
+#else
+  if (hcec->gState == HAL_CEC_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hcec->Lock = HAL_UNLOCKED;
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_CEC_MspInit(hcec);
+  }
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
+
+  hcec->gState = HAL_CEC_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_CEC_DISABLE(hcec);
+
+  /* Write to CEC Control Register */
+  hcec->Instance->CFGR = hcec->Init.SignalFreeTime | hcec->Init.Tolerance | hcec->Init.BRERxStop | \
+                         hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | \
+                         hcec->Init.BroadcastMsgNoErrorBitGen | \
+                         hcec->Init.SignalFreeTimeOption | ((uint32_t)(hcec->Init.OwnAddress) << 16U) | \
+                         hcec->Init.ListenMode;
+
+  /* Enable the following CEC Transmission/Reception interrupts as
+    * well as the following CEC Transmission/Reception Errors interrupts
+    * Rx Byte Received IT
+    * End of Reception IT
+    * Rx overrun
+    * Rx bit rising error
+    * Rx short bit period error
+    * Rx long bit period error
+    * Rx missing acknowledge
+    * Tx Byte Request IT
+    * End of Transmission IT
+    * Tx Missing Acknowledge IT
+    * Tx-Error IT
+    * Tx-Buffer Underrun IT
+    * Tx arbitration lost   */
+  __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR | CEC_IT_RXEND | CEC_IER_RX_ALL_ERR | CEC_IT_TXBR | CEC_IT_TXEND |
+                      CEC_IER_TX_ALL_ERR);
+
+  /* Enable the CEC Peripheral */
+  __HAL_CEC_ENABLE(hcec);
+
+  hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+  hcec->gState = HAL_CEC_STATE_READY;
+  hcec->RxState = HAL_CEC_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief DeInitializes the CEC peripheral
+  * @param hcec CEC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
+{
+  /* Check the CEC handle allocation */
+  if (hcec == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
+
+  hcec->gState = HAL_CEC_STATE_BUSY;
+
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
+  if (hcec->MspDeInitCallback == NULL)
+  {
+    hcec->MspDeInitCallback = HAL_CEC_MspDeInit; /* Legacy weak MspDeInit  */
+  }
+
+  /* DeInit the low level hardware */
+  hcec->MspDeInitCallback(hcec);
+
+#else
+  /* DeInit the low level hardware */
+  HAL_CEC_MspDeInit(hcec);
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
+
+  /* Disable the Peripheral */
+  __HAL_CEC_DISABLE(hcec);
+
+  /* Clear Flags */
+  __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND | CEC_FLAG_TXBR | CEC_FLAG_RXBR | CEC_FLAG_RXEND | CEC_ISR_ALL_ERROR);
+
+  /* Disable the following CEC Transmission/Reception interrupts as
+    * well as the following CEC Transmission/Reception Errors interrupts
+    * Rx Byte Received IT
+    * End of Reception IT
+    * Rx overrun
+    * Rx bit rising error
+    * Rx short bit period error
+    * Rx long bit period error
+    * Rx missing acknowledge
+    * Tx Byte Request IT
+    * End of Transmission IT
+    * Tx Missing Acknowledge IT
+    * Tx-Error IT
+    * Tx-Buffer Underrun IT
+    * Tx arbitration lost   */
+  __HAL_CEC_DISABLE_IT(hcec, CEC_IT_RXBR | CEC_IT_RXEND | CEC_IER_RX_ALL_ERR | CEC_IT_TXBR | CEC_IT_TXEND |
+                       CEC_IER_TX_ALL_ERR);
+
+  hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+  hcec->gState = HAL_CEC_STATE_RESET;
+  hcec->RxState = HAL_CEC_STATE_RESET;
+
+  /* Process Unlock */
+  __HAL_UNLOCK(hcec);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Initializes the Own Address of the CEC device
+  * @param hcec CEC handle
+  * @param  CEC_OwnAddress The CEC own address.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
+{
+  /* Check the parameters */
+  assert_param(IS_CEC_OWN_ADDRESS(CEC_OwnAddress));
+
+  if ((hcec->gState == HAL_CEC_STATE_READY) && (hcec->RxState == HAL_CEC_STATE_READY))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hcec);
+
+    hcec->gState = HAL_CEC_STATE_BUSY;
+
+    /* Disable the Peripheral */
+    __HAL_CEC_DISABLE(hcec);
+
+    if (CEC_OwnAddress != CEC_OWN_ADDRESS_NONE)
+    {
+      hcec->Instance->CFGR |= ((uint32_t)CEC_OwnAddress << 16);
+    }
+    else
+    {
+      hcec->Instance->CFGR &= ~(CEC_CFGR_OAR);
+    }
+
+    hcec->gState = HAL_CEC_STATE_READY;
+    hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcec);
+
+    /* Enable the Peripheral */
+    __HAL_CEC_ENABLE(hcec);
+
+    return  HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief CEC MSP Init
+  * @param hcec CEC handle
+  * @retval None
+  */
+__weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcec);
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_CEC_MspInit can be implemented in the user file
+   */
+}
+
+/**
+  * @brief CEC MSP DeInit
+  * @param hcec CEC handle
+  * @retval None
+  */
+__weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcec);
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_CEC_MspDeInit can be implemented in the user file
+   */
+}
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User CEC Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hcec CEC handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
+  *          @arg HAL_CEC_ERROR_CB_ID Error callback ID
+  *          @arg HAL_CEC_MSPINIT_CB_ID MspInit callback ID
+  *          @arg HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID,
+                                           pCEC_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hcec);
+
+  if (hcec->gState == HAL_CEC_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_CEC_TX_CPLT_CB_ID :
+        hcec->TxCpltCallback = pCallback;
+        break;
+
+      case HAL_CEC_ERROR_CB_ID :
+        hcec->ErrorCallback = pCallback;
+        break;
+
+      case HAL_CEC_MSPINIT_CB_ID :
+        hcec->MspInitCallback = pCallback;
+        break;
+
+      case HAL_CEC_MSPDEINIT_CB_ID :
+        hcec->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hcec->gState == HAL_CEC_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_CEC_MSPINIT_CB_ID :
+        hcec->MspInitCallback = pCallback;
+        break;
+
+      case HAL_CEC_MSPDEINIT_CB_ID :
+        hcec->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hcec);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister an CEC Callback
+  *         CEC callback is redirected to the weak predefined callback
+  * @param hcec uart handle
+  * @param CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *          @arg HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
+  *          @arg HAL_CEC_ERROR_CB_ID Error callback ID
+  *          @arg HAL_CEC_MSPINIT_CB_ID MspInit callback ID
+  *          @arg HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hcec);
+
+  if (hcec->gState == HAL_CEC_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_CEC_TX_CPLT_CB_ID :
+        hcec->TxCpltCallback = HAL_CEC_TxCpltCallback;  /* Legacy weak  TxCpltCallback */
+        break;
+
+      case HAL_CEC_ERROR_CB_ID :
+        hcec->ErrorCallback = HAL_CEC_ErrorCallback;  /* Legacy weak ErrorCallback   */
+        break;
+
+      case HAL_CEC_MSPINIT_CB_ID :
+        hcec->MspInitCallback = HAL_CEC_MspInit;
+        break;
+
+      case HAL_CEC_MSPDEINIT_CB_ID :
+        hcec->MspDeInitCallback = HAL_CEC_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hcec->gState == HAL_CEC_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_CEC_MSPINIT_CB_ID :
+        hcec->MspInitCallback = HAL_CEC_MspInit;
+        break;
+
+      case HAL_CEC_MSPDEINIT_CB_ID :
+        hcec->MspDeInitCallback = HAL_CEC_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hcec);
+
+  return status;
+}
+
+/**
+  * @brief  Register CEC RX complete Callback
+  *         To be used instead of the weak HAL_CEC_RxCpltCallback() predefined callback
+  * @param  hcec CEC handle
+  * @param  pCallback pointer to the Rx transfer compelete Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CEC_RegisterRxCpltCallback(CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hcec);
+
+  if (HAL_CEC_STATE_READY == hcec->RxState)
+  {
+    hcec->RxCpltCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hcec);
+  return status;
+}
+
+/**
+  * @brief  UnRegister CEC RX complete Callback
+  *         CEC RX complete Callback is redirected to the weak HAL_CEC_RxCpltCallback() predefined callback
+  * @param  hcec CEC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hcec);
+
+  if (HAL_CEC_STATE_READY == hcec->RxState)
+  {
+    hcec->RxCpltCallback = HAL_CEC_RxCpltCallback; /* Legacy weak  CEC RxCpltCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hcec);
+  return status;
+}
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup CEC_Exported_Functions_Group2 Input and Output operation functions
+  *  @brief CEC Transmit/Receive functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    This subsection provides a set of functions allowing to manage the CEC data transfers.
+
+    (#) The CEC handle must contain the initiator (TX side) and the destination (RX side)
+        logical addresses (4-bit long addresses, 0xF for broadcast messages destination)
+
+    (#) The communication is performed using Interrupts.
+           These API's return the HAL status.
+           The end of the data processing will be indicated through the
+           dedicated CEC IRQ when using Interrupt mode.
+           The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks
+           will be executed respectively at the end of the transmit or Receive process
+           The HAL_CEC_ErrorCallback() user callback will be executed when a communication
+           error is detected
+
+    (#) API's with Interrupt are :
+         (+) HAL_CEC_Transmit_IT()
+         (+) HAL_CEC_IRQHandler()
+
+    (#) A set of User Callbacks are provided:
+         (+) HAL_CEC_TxCpltCallback()
+         (+) HAL_CEC_RxCpltCallback()
+         (+) HAL_CEC_ErrorCallback()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Send data in interrupt mode
+  * @param hcec CEC handle
+  * @param InitiatorAddress Initiator address
+  * @param DestinationAddress destination logical address
+  * @param pData pointer to input byte data buffer
+  * @param Size amount of data to be sent in bytes (without counting the header).
+  *              0 means only the header is sent (ping operation).
+  *              Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress,
+                                      const uint8_t *pData, uint32_t Size)
+{
+  /* if the peripheral isn't already busy and if there is no previous transmission
+     already pending due to arbitration lost */
+  if (hcec->gState == HAL_CEC_STATE_READY)
+  {
+    if ((pData == NULL) && (Size > 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    assert_param(IS_CEC_ADDRESS(DestinationAddress));
+    assert_param(IS_CEC_ADDRESS(InitiatorAddress));
+    assert_param(IS_CEC_MSGSIZE(Size));
+
+    /* Process Locked */
+    __HAL_LOCK(hcec);
+    hcec->pTxBuffPtr = pData;
+    hcec->gState = HAL_CEC_STATE_BUSY_TX;
+    hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+
+    /* initialize the number of bytes to send,
+      * 0 means only one header is sent (ping operation) */
+    hcec->TxXferCount = (uint16_t)Size;
+
+    /* in case of no payload (Size = 0), sender is only pinging the system;
+       Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
+    if (Size == 0U)
+    {
+      __HAL_CEC_LAST_BYTE_TX_SET(hcec);
+    }
+
+    /* send header block */
+    hcec->Instance->TXDR = (uint32_t)(((uint32_t)InitiatorAddress << CEC_INITIATOR_LSB_POS) | DestinationAddress);
+
+    /* Set TX Start of Message  (TXSOM) bit */
+    __HAL_CEC_FIRST_BYTE_TX_SET(hcec);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hcec);
+
+    return HAL_OK;
+
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Get size of the received frame.
+  * @param hcec CEC handle
+  * @retval Frame size
+  */
+uint32_t HAL_CEC_GetLastReceivedFrameSize(const CEC_HandleTypeDef *hcec)
+{
+  return hcec->RxXferSize;
+}
+
+/**
+  * @brief Change Rx Buffer.
+  * @param hcec CEC handle
+  * @param Rxbuffer Rx Buffer
+  * @note  This function can be called only inside the HAL_CEC_RxCpltCallback()
+  * @retval Frame size
+  */
+void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer)
+{
+  hcec->Init.RxBuffer = Rxbuffer;
+}
+
+/**
+  * @brief This function handles CEC interrupt requests.
+  * @param hcec CEC handle
+  * @retval None
+  */
+void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
+{
+
+  /* save interrupts register for further error or interrupts handling purposes */
+  uint32_t itflag;
+  itflag = hcec->Instance->ISR;
+
+
+  /* ----------------------------Arbitration Lost Management----------------------------------*/
+  /* CEC TX arbitration error interrupt occurred --------------------------------------*/
+  if (HAL_IS_BIT_SET(itflag, CEC_FLAG_ARBLST))
+  {
+    hcec->ErrorCode = HAL_CEC_ERROR_ARBLST;
+    __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST);
+  }
+
+  /* ----------------------------Rx Management----------------------------------*/
+  /* CEC RX byte received interrupt  ---------------------------------------------------*/
+  if (HAL_IS_BIT_SET(itflag, CEC_FLAG_RXBR))
+  {
+    /* reception is starting */
+    hcec->RxState = HAL_CEC_STATE_BUSY_RX;
+    hcec->RxXferSize++;
+    /* read received byte */
+    *hcec->Init.RxBuffer = (uint8_t) hcec->Instance->RXDR;
+    hcec->Init.RxBuffer++;
+    __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR);
+  }
+
+  /* CEC RX end received interrupt  ---------------------------------------------------*/
+  if (HAL_IS_BIT_SET(itflag, CEC_FLAG_RXEND))
+  {
+    /* clear IT */
+    __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND);
+
+    /* Rx process is completed, restore hcec->RxState to Ready */
+    hcec->RxState = HAL_CEC_STATE_READY;
+    hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+    hcec->Init.RxBuffer -= hcec->RxXferSize;
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1U)
+    hcec->RxCpltCallback(hcec, hcec->RxXferSize);
+#else
+    HAL_CEC_RxCpltCallback(hcec, hcec->RxXferSize);
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
+    hcec->RxXferSize = 0U;
+  }
+
+  /* ----------------------------Tx Management----------------------------------*/
+  /* CEC TX byte request interrupt ------------------------------------------------*/
+  if (HAL_IS_BIT_SET(itflag, CEC_FLAG_TXBR))
+  {
+    --hcec->TxXferCount;
+    if (hcec->TxXferCount == 0U)
+    {
+      /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
+      __HAL_CEC_LAST_BYTE_TX_SET(hcec);
+    }
+    /* In all cases transmit the byte */
+    hcec->Instance->TXDR = (uint8_t)*hcec->pTxBuffPtr;
+    hcec->pTxBuffPtr++;
+    /* clear Tx-Byte request flag */
+    __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR);
+  }
+
+  /* CEC TX end interrupt ------------------------------------------------*/
+  if (HAL_IS_BIT_SET(itflag, CEC_FLAG_TXEND))
+  {
+    __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND);
+
+    /* Tx process is ended, restore hcec->gState to Ready */
+    hcec->gState = HAL_CEC_STATE_READY;
+    /* Call the Process Unlocked before calling the Tx call back API to give the possibility to
+    start again the Transmission under the Tx call back API */
+    __HAL_UNLOCK(hcec);
+    hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1U)
+    hcec->TxCpltCallback(hcec);
+#else
+    HAL_CEC_TxCpltCallback(hcec);
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
+  }
+
+  /* ----------------------------Rx/Tx Error Management----------------------------------*/
+  if ((itflag & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE | CEC_ISR_TXUDR |
+              CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U)
+  {
+    hcec->ErrorCode = itflag;
+    __HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR | HAL_CEC_ERROR_BRE | CEC_FLAG_LBPE | CEC_FLAG_SBPE |
+                         HAL_CEC_ERROR_RXACKE | HAL_CEC_ERROR_TXUDR | HAL_CEC_ERROR_TXERR | HAL_CEC_ERROR_TXACKE);
+
+
+    if ((itflag & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE)) != 0U)
+    {
+      hcec->Init.RxBuffer -= hcec->RxXferSize;
+      hcec->RxXferSize = 0U;
+      hcec->RxState = HAL_CEC_STATE_READY;
+    }
+    else if (((itflag & CEC_ISR_ARBLST) == 0U) && ((itflag & (CEC_ISR_TXUDR | CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U))
+    {
+      /* Set the CEC state ready to be able to start again the process */
+      hcec->gState = HAL_CEC_STATE_READY;
+    }
+    else
+    {
+      /* Nothing todo*/
+    }
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1U)
+    hcec->ErrorCallback(hcec);
+#else
+    /* Error  Call Back */
+    HAL_CEC_ErrorCallback(hcec);
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* Nothing todo*/
+  }
+}
+
+/**
+  * @brief Tx Transfer completed callback
+  * @param hcec CEC handle
+  * @retval None
+  */
+__weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcec);
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_CEC_TxCpltCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief Rx Transfer completed callback
+  * @param hcec CEC handle
+  * @param RxFrameSize Size of frame
+  * @retval None
+  */
+__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcec);
+  UNUSED(RxFrameSize);
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_CEC_RxCpltCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @brief CEC error callbacks
+  * @param hcec CEC handle
+  * @retval None
+  */
+__weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcec);
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_CEC_ErrorCallback can be implemented in the user file
+   */
+}
+/**
+  * @}
+  */
+
+/** @defgroup CEC_Exported_Functions_Group3 Peripheral Control function
+  *  @brief   CEC control functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control function #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the CEC.
+     (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral.
+     (+) HAL_CEC_GetError() API can be helpful to check in run-time the error of the CEC peripheral.
+@endverbatim
+  * @{
+  */
+/**
+  * @brief return the CEC state
+  * @param hcec pointer to a CEC_HandleTypeDef structure that contains
+  *              the configuration information for the specified CEC module.
+  * @retval HAL state
+  */
+HAL_CEC_StateTypeDef HAL_CEC_GetState(const CEC_HandleTypeDef *hcec)
+{
+  uint32_t temp1;
+  uint32_t temp2;
+  temp1 = hcec->gState;
+  temp2 = hcec->RxState;
+
+  return (HAL_CEC_StateTypeDef)(temp1 | temp2);
+}
+
+/**
+  * @brief  Return the CEC error code
+  * @param  hcec  pointer to a CEC_HandleTypeDef structure that contains
+  *              the configuration information for the specified CEC.
+  * @retval CEC Error Code
+  */
+uint32_t HAL_CEC_GetError(const CEC_HandleTypeDef *hcec)
+{
+  return hcec->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* CEC */
+#endif /* HAL_CEC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_crc.c

@@ -0,0 +1,516 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_crc.c
+  * @author  MCD Application Team
+  * @brief   CRC HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Cyclic Redundancy Check (CRC) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+ ===============================================================================
+                     ##### How to use this driver #####
+ ===============================================================================
+    [..]
+         (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
+         (+) Initialize CRC calculator
+             (++) specify generating polynomial (peripheral default or non-default one)
+             (++) specify initialization value (peripheral default or non-default one)
+             (++) specify input data format
+             (++) specify input or output data inversion mode if any
+         (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
+             input data buffer starting with the previously computed CRC as
+             initialization value
+         (+) Use HAL_CRC_Calculate() function to compute the CRC value of the
+             input data buffer starting with the defined initialization value
+             (default or non-default) to initiate CRC calculation
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal.h"
+
+/** @addtogroup STM32G0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup CRC CRC
+  * @brief CRC HAL module driver.
+  * @{
+  */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup CRC_Private_Functions CRC Private Functions
+  * @{
+  */
+static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
+static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup CRC_Exported_Functions CRC Exported Functions
+  * @{
+  */
+
+/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions.
+  *
+@verbatim
+ ===============================================================================
+            ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize the CRC according to the specified parameters
+          in the CRC_InitTypeDef and create the associated handle
+      (+) DeInitialize the CRC peripheral
+      (+) Initialize the CRC MSP (MCU Specific Package)
+      (+) DeInitialize the CRC MSP
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the CRC according to the specified
+  *         parameters in the CRC_InitTypeDef and create the associated handle.
+  * @param  hcrc CRC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
+{
+  /* Check the CRC handle allocation */
+  if (hcrc == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
+
+  if (hcrc->State == HAL_CRC_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hcrc->Lock = HAL_UNLOCKED;
+    /* Init the low level hardware */
+    HAL_CRC_MspInit(hcrc);
+  }
+
+  hcrc->State = HAL_CRC_STATE_BUSY;
+
+  /* check whether or not non-default generating polynomial has been
+   * picked up by user */
+  assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
+  if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
+  {
+    /* initialize peripheral with default generating polynomial */
+    WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
+    MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
+  }
+  else
+  {
+    /* initialize CRC peripheral with generating polynomial defined by user */
+    if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  /* check whether or not non-default CRC initial value has been
+   * picked up by user */
+  assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
+  if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
+  {
+    WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
+  }
+  else
+  {
+    WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
+  }
+
+
+  /* set input data inversion mode */
+  assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
+  MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
+
+  /* set output data inversion mode */
+  assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
+  MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
+
+  /* makes sure the input data format (bytes, halfwords or words stream)
+   * is properly specified by user */
+  assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));
+
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the CRC peripheral.
+  * @param  hcrc CRC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
+{
+  /* Check the CRC handle allocation */
+  if (hcrc == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
+
+  /* Check the CRC peripheral state */
+  if (hcrc->State == HAL_CRC_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_BUSY;
+
+  /* Reset CRC calculation unit */
+  __HAL_CRC_DR_RESET(hcrc);
+
+  /* Reset IDR register content */
+  CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR);
+
+  /* DeInit the low level hardware */
+  HAL_CRC_MspDeInit(hcrc);
+
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_RESET;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hcrc);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CRC MSP.
+  * @param  hcrc CRC handle
+  * @retval None
+  */
+__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcrc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_CRC_MspInit can be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitialize the CRC MSP.
+  * @param  hcrc CRC handle
+  * @retval None
+  */
+__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcrc);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_CRC_MspDeInit can be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
+  *  @brief    management functions.
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+          using combination of the previous CRC value and the new one.
+
+       [..]  or
+
+      (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+          independently of the previous CRC value.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+  *         starting with the previously computed CRC as initialization value.
+  * @param  hcrc CRC handle
+  * @param  pBuffer pointer to the input data buffer, exact input data format is
+  *         provided by hcrc->InputDataFormat.
+  * @param  BufferLength input data buffer length (number of bytes if pBuffer
+  *         type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
+  *         number of words if pBuffer type is * uint32_t).
+  * @note  By default, the API expects a uint32_t pointer as input buffer parameter.
+  *        Input buffer pointers with other types simply need to be cast in uint32_t
+  *        and the API will internally adjust its input data processing based on the
+  *        handle field hcrc->InputDataFormat.
+  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+  */
+uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
+{
+  uint32_t index;      /* CRC input data buffer index */
+  uint32_t temp = 0U;  /* CRC output (read from hcrc->Instance->DR register) */
+
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_BUSY;
+
+  switch (hcrc->InputDataFormat)
+  {
+    case CRC_INPUTDATA_FORMAT_WORDS:
+      /* Enter Data to the CRC calculator */
+      for (index = 0U; index < BufferLength; index++)
+      {
+        hcrc->Instance->DR = pBuffer[index];
+      }
+      temp = hcrc->Instance->DR;
+      break;
+
+    case CRC_INPUTDATA_FORMAT_BYTES:
+      temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
+      break;
+
+    case CRC_INPUTDATA_FORMAT_HALFWORDS:
+      temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength);    /* Derogation MisraC2012 R.11.5 */
+      break;
+    default:
+      break;
+  }
+
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_READY;
+
+  /* Return the CRC computed value */
+  return temp;
+}
+
+/**
+  * @brief  Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+  *         starting with hcrc->Instance->INIT as initialization value.
+  * @param  hcrc CRC handle
+  * @param  pBuffer pointer to the input data buffer, exact input data format is
+  *         provided by hcrc->InputDataFormat.
+  * @param  BufferLength input data buffer length (number of bytes if pBuffer
+  *         type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
+  *         number of words if pBuffer type is * uint32_t).
+  * @note  By default, the API expects a uint32_t pointer as input buffer parameter.
+  *        Input buffer pointers with other types simply need to be cast in uint32_t
+  *        and the API will internally adjust its input data processing based on the
+  *        handle field hcrc->InputDataFormat.
+  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+  */
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
+{
+  uint32_t index;      /* CRC input data buffer index */
+  uint32_t temp = 0U;  /* CRC output (read from hcrc->Instance->DR register) */
+
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_BUSY;
+
+  /* Reset CRC Calculation Unit (hcrc->Instance->INIT is
+  *  written in hcrc->Instance->DR) */
+  __HAL_CRC_DR_RESET(hcrc);
+
+  switch (hcrc->InputDataFormat)
+  {
+    case CRC_INPUTDATA_FORMAT_WORDS:
+      /* Enter 32-bit input data to the CRC calculator */
+      for (index = 0U; index < BufferLength; index++)
+      {
+        hcrc->Instance->DR = pBuffer[index];
+      }
+      temp = hcrc->Instance->DR;
+      break;
+
+    case CRC_INPUTDATA_FORMAT_BYTES:
+      /* Specific 8-bit input data handling  */
+      temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
+      break;
+
+    case CRC_INPUTDATA_FORMAT_HALFWORDS:
+      /* Specific 16-bit input data handling  */
+      temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength);    /* Derogation MisraC2012 R.11.5 */
+      break;
+
+    default:
+      break;
+  }
+
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_READY;
+
+  /* Return the CRC computed value */
+  return temp;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
+  *  @brief    Peripheral State functions.
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral State functions #####
+ ===============================================================================
+    [..]
+    This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the CRC handle state.
+  * @param  hcrc CRC handle
+  * @retval HAL state
+  */
+HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
+{
+  /* Return CRC handle state */
+  return hcrc->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup CRC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Enter 8-bit input data to the CRC calculator.
+  *         Specific data handling to optimize processing time.
+  * @param  hcrc CRC handle
+  * @param  pBuffer pointer to the input data buffer
+  * @param  BufferLength input data buffer length
+  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+  */
+static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
+{
+  uint32_t i; /* input data buffer index */
+  uint16_t data;
+  __IO uint16_t *pReg;
+
+  /* Processing time optimization: 4 bytes are entered in a row with a single word write,
+   * last bytes must be carefully fed to the CRC calculator to ensure a correct type
+   * handling by the peripheral */
+  for (i = 0U; i < (BufferLength / 4U); i++)
+  {
+    hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \
+                         ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \
+                         ((uint32_t)pBuffer[(4U * i) + 2U] << 8U)  | \
+                         (uint32_t)pBuffer[(4U * i) + 3U];
+  }
+  /* last bytes specific handling */
+  if ((BufferLength % 4U) != 0U)
+  {
+    if ((BufferLength % 4U) == 1U)
+    {
+      *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i];         /* Derogation MisraC2012 R.11.5 */
+    }
+    if ((BufferLength % 4U) == 2U)
+    {
+      data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
+      pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR);                    /* Derogation MisraC2012 R.11.5 */
+      *pReg = data;
+    }
+    if ((BufferLength % 4U) == 3U)
+    {
+      data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
+      pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR);                    /* Derogation MisraC2012 R.11.5 */
+      *pReg = data;
+
+      *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U];  /* Derogation MisraC2012 R.11.5 */
+    }
+  }
+
+  /* Return the CRC computed value */
+  return hcrc->Instance->DR;
+}
+
+/**
+  * @brief  Enter 16-bit input data to the CRC calculator.
+  *         Specific data handling to optimize processing time.
+  * @param  hcrc CRC handle
+  * @param  pBuffer pointer to the input data buffer
+  * @param  BufferLength input data buffer length
+  * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
+  */
+static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
+{
+  uint32_t i;  /* input data buffer index */
+  __IO uint16_t *pReg;
+
+  /* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
+   * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
+   * a correct type handling by the peripheral */
+  for (i = 0U; i < (BufferLength / 2U); i++)
+  {
+    hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U];
+  }
+  if ((BufferLength % 2U) != 0U)
+  {
+    pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR);                 /* Derogation MisraC2012 R.11.5 */
+    *pReg = pBuffer[2U * i];
+  }
+
+  /* Return the CRC computed value */
+  return hcrc->Instance->DR;
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_CRC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_crc_ex.c

@@ -0,0 +1,223 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_crc_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended CRC HAL module driver.
+  *          This file provides firmware functions to manage the extended
+  *          functionalities of the CRC peripheral.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+================================================================================
+            ##### How to use this driver #####
+================================================================================
+    [..]
+         (+) Set user-defined generating polynomial through HAL_CRCEx_Polynomial_Set()
+         (+) Configure Input or Output data inversion
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal.h"
+
+/** @addtogroup STM32G0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup CRCEx CRCEx
+  * @brief CRC Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions
+  * @brief    Extended Initialization and Configuration functions.
+  *
+@verbatim
+ ===============================================================================
+            ##### Extended configuration functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure the generating polynomial
+      (+) Configure the input data inversion
+      (+) Configure the output data inversion
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Initialize the CRC polynomial if different from default one.
+  * @param  hcrc CRC handle
+  * @param  Pol CRC generating polynomial (7, 8, 16 or 32-bit long).
+  *         This parameter is written in normal representation, e.g.
+  *         @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
+  *         @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
+  * @param  PolyLength CRC polynomial length.
+  *         This parameter can be one of the following values:
+  *          @arg @ref CRC_POLYLENGTH_7B  7-bit long CRC (generating polynomial of degree 7)
+  *          @arg @ref CRC_POLYLENGTH_8B  8-bit long CRC (generating polynomial of degree 8)
+  *          @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16)
+  *          @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */
+
+  /* Check the parameters */
+  assert_param(IS_CRC_POL_LENGTH(PolyLength));
+
+  /* check polynomial definition vs polynomial size:
+   * polynomial length must be aligned with polynomial
+   * definition. HAL_ERROR is reported if Pol degree is
+   * larger than that indicated by PolyLength.
+   * Look for MSB position: msb will contain the degree of
+   *  the second to the largest polynomial member. E.g., for
+   *  X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
+  while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
+  {
+  }
+
+  switch (PolyLength)
+  {
+    case CRC_POLYLENGTH_7B:
+      if (msb >= HAL_CRC_LENGTH_7B)
+      {
+        status =   HAL_ERROR;
+      }
+      break;
+    case CRC_POLYLENGTH_8B:
+      if (msb >= HAL_CRC_LENGTH_8B)
+      {
+        status =   HAL_ERROR;
+      }
+      break;
+    case CRC_POLYLENGTH_16B:
+      if (msb >= HAL_CRC_LENGTH_16B)
+      {
+        status =   HAL_ERROR;
+      }
+      break;
+
+    case CRC_POLYLENGTH_32B:
+      /* no polynomial definition vs. polynomial length issue possible */
+      break;
+    default:
+      status =  HAL_ERROR;
+      break;
+  }
+  if (status == HAL_OK)
+  {
+    /* set generating polynomial */
+    WRITE_REG(hcrc->Instance->POL, Pol);
+
+    /* set generating polynomial size */
+    MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
+  }
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Set the Reverse Input data mode.
+  * @param  hcrc CRC handle
+  * @param  InputReverseMode Input Data inversion mode.
+  *         This parameter can be one of the following values:
+  *          @arg @ref CRC_INPUTDATA_INVERSION_NONE     no change in bit order (default value)
+  *          @arg @ref CRC_INPUTDATA_INVERSION_BYTE     Byte-wise bit reversal
+  *          @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD HalfWord-wise bit reversal
+  *          @arg @ref CRC_INPUTDATA_INVERSION_WORD     Word-wise bit reversal
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
+{
+  /* Check the parameters */
+  assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode));
+
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_BUSY;
+
+  /* set input data inversion mode */
+  MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode);
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the Reverse Output data mode.
+  * @param  hcrc CRC handle
+  * @param  OutputReverseMode Output Data inversion mode.
+  *         This parameter can be one of the following values:
+  *          @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion (default value)
+  *          @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE  bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
+{
+  /* Check the parameters */
+  assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode));
+
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_BUSY;
+
+  /* set output data inversion mode */
+  MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode);
+
+  /* Change CRC peripheral state */
+  hcrc->State = HAL_CRC_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+
+
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+#endif /* HAL_CRC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cryp_ex.c

@@ -0,0 +1,386 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_cryp_ex.c
+  * @author  MCD Application Team
+  * @brief   CRYPEx HAL module driver.
+  *          This file provides firmware functions to manage the extended
+  *          functionalities of the Cryptography (CRYP) peripheral.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal.h"
+
+/** @addtogroup STM32G0xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CRYPEx
+  * @{
+  */
+
+#if defined(AES)
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup CRYPEx_Private_Defines
+  * @{
+  */
+
+#define CRYP_PHASE_INIT                              0x00000000U             /*!< GCM/GMAC (or CCM) init phase */
+#define CRYP_PHASE_HEADER                            AES_CR_GCMPH_0          /*!< GCM/GMAC or CCM header phase */
+#define CRYP_PHASE_PAYLOAD                           AES_CR_GCMPH_1          /*!< GCM(/CCM) payload phase   */
+#define CRYP_PHASE_FINAL                             AES_CR_GCMPH            /*!< GCM/GMAC or CCM  final phase  */
+
+#define CRYP_OPERATINGMODE_ENCRYPT                   0x00000000U             /*!< Encryption mode   */
+#define CRYP_OPERATINGMODE_KEYDERIVATION             AES_CR_MODE_0           /*!< Key derivation mode  only used when performing ECB and CBC decryptions  */
+#define CRYP_OPERATINGMODE_DECRYPT                   AES_CR_MODE_1           /*!< Decryption       */
+#define CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT     AES_CR_MODE             /*!< Key derivation and decryption only used when performing ECB and CBC decryptions  */
+
+#define  CRYPEx_PHASE_PROCESS       0x02U     /*!< CRYP peripheral is in processing phase */
+#define  CRYPEx_PHASE_FINAL         0x03U     /*!< CRYP peripheral is in final phase this is relevant only with CCM and GCM modes */
+
+/*  CTR0 information to use in CCM algorithm */
+#define CRYP_CCM_CTR0_0            0x07FFFFFFU
+#define CRYP_CCM_CTR0_3            0xFFFFFF00U
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions---------------------------------------------------------*/
+/** @addtogroup CRYPEx_Exported_Functions
+  * @{
+  */
+
+/** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions
+ *  @brief   Extended processing functions.
+ *
+@verbatim
+  ==============================================================================
+              ##### Extended AES processing functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to generate the authentication
+          TAG in Polling mode
+      (#)HAL_CRYPEx_AESGCM_GenerateAuthTAG
+      (#)HAL_CRYPEx_AESCCM_GenerateAuthTAG
+         they should be used after Encrypt/Decrypt operation.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  generate the GCM authentication TAG.
+  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  AuthTag Pointer to the authentication buffer
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
+{
+  uint32_t tickstart;
+  /* Assume first Init.HeaderSize is in words */
+  uint64_t headerlength = (uint64_t)hcryp->Init.HeaderSize * 32U; /* Header length in bits */
+  uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* Input length in bits */
+  uint32_t tagaddr = (uint32_t)AuthTag;
+
+  /* Correct headerlength if Init.HeaderSize is actually in bytes */
+  if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_BYTE)
+  {
+    headerlength /= 4U;
+  }
+
+  if (hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* Process locked */
+    __HAL_LOCK(hcryp);
+
+    /* Change the CRYP peripheral state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+
+    /* Check if initialization phase has already been performed */
+    if (hcryp->Phase == CRYPEx_PHASE_PROCESS)
+    {
+      /* Change the CRYP phase */
+      hcryp->Phase = CRYPEx_PHASE_FINAL;
+    }
+    else /* Initialization phase has not been performed*/
+    {
+      /* Disable the Peripheral */
+      __HAL_CRYP_DISABLE(hcryp);
+
+      /* Sequence error code field */
+      hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE;
+
+      /* Change the CRYP peripheral state */
+      hcryp->State = HAL_CRYP_STATE_READY;
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hcryp);
+      return HAL_ERROR;
+    }
+
+    /* Select final phase */
+    MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL);
+
+    /* Set the encrypt operating mode*/
+    MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
+
+    /*TinyAES peripheral from V3.1.1 : data has to be inserted normally (no swapping)*/
+    /* Write into the AES_DINR register the number of bits in header (64 bits)
+    followed by the number of bits in the payload */
+
+    hcryp->Instance->DINR = 0U;
+    hcryp->Instance->DINR = (uint32_t)(headerlength);
+    hcryp->Instance->DINR = 0U;
+    hcryp->Instance->DINR = (uint32_t)(inputlength);
+
+    /* Wait for CCF flag to be raised */
+    tickstart = HAL_GetTick();
+    while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
+    {
+      /* Check for the Timeout */
+      if (Timeout != HAL_MAX_DELAY)
+      {
+        if (((HAL_GetTick() - tickstart) > Timeout)||(Timeout == 0U))
+        {
+          /* Disable the CRYP peripheral clock */
+          __HAL_CRYP_DISABLE(hcryp);
+
+          /* Change state */
+          hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+          hcryp->State = HAL_CRYP_STATE_READY;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hcryp);
+          return HAL_ERROR;
+        }
+      }
+    }
+
+    /* Read the authentication TAG in the output FIFO */
+    *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
+    tagaddr += 4U;
+    *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
+    tagaddr += 4U;
+    *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
+    tagaddr += 4U;
+    *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
+
+    /* Clear CCF flag */
+    __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+    /* Disable the peripheral */
+    __HAL_CRYP_DISABLE(hcryp);
+
+    /* Change the CRYP peripheral state */
+    hcryp->State = HAL_CRYP_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hcryp);
+  }
+  else
+  {
+    /* Busy error code field */
+    hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
+    return HAL_ERROR;
+  }
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  AES CCM Authentication TAG generation.
+  * @param  hcryp pointer to a CRYP_HandleTypeDef structure that contains
+  *         the configuration information for CRYP module
+  * @param  AuthTag Pointer to the authentication buffer
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
+{
+  uint32_t tagaddr = (uint32_t)AuthTag;
+  uint32_t tickstart;
+
+  if (hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    /* Process locked */
+    __HAL_LOCK(hcryp);
+
+    /* Disable interrupts in case they were kept enabled to proceed
+       a single message in several iterations */
+    __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
+
+    /* Change the CRYP peripheral state */
+    hcryp->State = HAL_CRYP_STATE_BUSY;
+
+    /* Check if initialization phase has already been performed */
+    if (hcryp->Phase == CRYPEx_PHASE_PROCESS)
+    {
+      /* Change the CRYP phase */
+      hcryp->Phase = CRYPEx_PHASE_FINAL;
+    }
+    else /* Initialization phase has not been performed*/
+    {
+      /* Disable the peripheral */
+      __HAL_CRYP_DISABLE(hcryp);
+
+      /* Sequence error code field */
+      hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE;
+
+      /* Change the CRYP peripheral state */
+      hcryp->State = HAL_CRYP_STATE_READY;
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hcryp);
+      return HAL_ERROR;
+    }
+    /* Select final phase */
+    MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL);
+
+    /* Set encrypt  operating mode*/
+    MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
+
+    /* Wait for CCF flag to be raised */
+    tickstart = HAL_GetTick();
+    while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
+    {
+      /* Check for the Timeout */
+      if (Timeout != HAL_MAX_DELAY)
+      {
+        if (((HAL_GetTick() - tickstart) > Timeout) ||(Timeout == 0U))
+        {
+          /* Disable the CRYP peripheral Clock */
+          __HAL_CRYP_DISABLE(hcryp);
+
+          /* Change state */
+          hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+          hcryp->State = HAL_CRYP_STATE_READY;
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hcryp);
+          return HAL_ERROR;
+        }
+      }
+    }
+
+    /* Read the authentication TAG in the output FIFO */
+    *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
+    tagaddr += 4U;
+    *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
+    tagaddr += 4U;
+    *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
+    tagaddr += 4U;
+    *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
+
+    /* Clear CCF Flag */
+    __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
+
+
+    /* Change the CRYP peripheral state */
+    hcryp->State = HAL_CRYP_STATE_READY;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hcryp);
+
+    /* Disable CRYP  */
+    __HAL_CRYP_DISABLE(hcryp);
+  }
+  else
+  {
+    /* Busy error code field */
+    hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY;
+    return HAL_ERROR;
+  }
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CRYPEx_Exported_Functions_Group2 Extended AES Key Derivations functions
+  * @brief   Extended Key Derivations functions.
+  *
+@verbatim
+  ==============================================================================
+              ##### Key Derivation functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to Enable or Disable the
+          the AutoKeyDerivation parameter in CRYP_HandleTypeDef structure
+          These function are allowed only in TinyAES peripheral.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  AES enable key derivation functions
+  * @param  hcryp pointer to a CRYP_HandleTypeDef structure.
+  */
+void  HAL_CRYPEx_EnableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp)
+{
+  if (hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    hcryp->AutoKeyDerivation = ENABLE;
+  }
+  else
+  {
+    /* Busy error code field */
+    hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY;
+  }
+}
+/**
+  * @brief  AES disable key derivation functions
+  * @param  hcryp pointer to a CRYP_HandleTypeDef structure.
+  */
+void  HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp)
+{
+  if (hcryp->State == HAL_CRYP_STATE_READY)
+  {
+    hcryp->AutoKeyDerivation = DISABLE;
+  }
+  else
+  {
+    /* Busy error code field */
+    hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#endif /* AES */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac_ex.c

@@ -0,0 +1,692 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_dac_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended DAC HAL module driver.
+  *          This file provides firmware functions to manage the extended
+  *          functionalities of the DAC peripheral.
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                      ##### How to use this driver #####
+  ==============================================================================
+    [..]
+
+     *** Dual mode IO operation ***
+     ==============================
+     [..]
+      (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
+          Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
+          HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in
+          Channel 1 and Channel 2.
+
+     *** Signal generation operation ***
+     ===================================
+     [..]
+      (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
+      (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
+
+      (+) HAL_DACEx_SelfCalibrate to calibrate one DAC channel.
+      (+) HAL_DACEx_SetUserTrimming to set user trimming value.
+      (+) HAL_DACEx_GetTrimOffset to retrieve trimming value (factory setting
+          after reset, user setting if HAL_DACEx_SetUserTrimming have been used
+          at least one time after reset).
+
+ @endverbatim
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal.h"
+
+/** @addtogroup STM32G0xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+
+#if defined(DAC1)
+
+/** @defgroup DACEx DACEx
+  * @brief DAC Extended HAL module driver
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup DACEx_Exported_Functions DACEx Exported Functions
+  * @{
+  */
+
+/** @defgroup DACEx_Exported_Functions_Group2 IO operation functions
+  *  @brief    Extended IO operation functions
+  *
+@verbatim
+  ==============================================================================
+                 ##### Extended features functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Start conversion.
+      (+) Stop conversion.
+      (+) Start conversion and enable DMA transfer.
+      (+) Stop conversion and disable DMA transfer.
+      (+) Get result of conversion.
+      (+) Get result of dual mode conversion.
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Enables DAC and starts conversion of both channels.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac)
+{
+  uint32_t tmp_swtrig = 0UL;
+
+
+  /* Process locked */
+  __HAL_LOCK(hdac);
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_BUSY;
+
+  /* Enable the Peripheral */
+  __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1);
+  __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2);
+
+  /* Check if software trigger enabled */
+  if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE)
+  {
+    tmp_swtrig |= DAC_SWTRIGR_SWTRIG1;
+  }
+  if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (DAC_CHANNEL_2 & 0x10UL)))
+  {
+    tmp_swtrig |= DAC_SWTRIGR_SWTRIG2;
+  }
+  /* Enable the selected DAC software conversion*/
+  SET_BIT(hdac->Instance->SWTRIGR, tmp_swtrig);
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdac);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disables DAC and stop conversion of both channels.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac)
+{
+
+  /* Disable the Peripheral */
+  __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1);
+  __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2);
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Enable or disable the selected DAC channel wave generation.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel The selected DAC channel.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
+  * @param  Amplitude Select max triangle amplitude.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
+  *            @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
+  *            @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
+  *            @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
+  *            @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
+  *            @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
+  *            @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
+  *            @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
+  *            @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
+  *            @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
+  *            @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
+  *            @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
+
+  /* Process locked */
+  __HAL_LOCK(hdac);
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_BUSY;
+
+  /* Enable the triangle wave generation for the selected DAC channel */
+  MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL),
+             (DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL));
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdac);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable or disable the selected DAC channel wave generation.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel The selected DAC channel.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
+  * @param  Amplitude Unmask DAC channel LFSR for noise wave generation.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
+
+  /* Process locked */
+  __HAL_LOCK(hdac);
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_BUSY;
+
+  /* Enable the noise wave generation for the selected DAC channel */
+  MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL),
+             (DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL));
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdac);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Set the specified data holding register value for dual DAC channel.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *               the configuration information for the specified DAC.
+  * @param  Alignment Specifies the data alignment for dual channel DAC.
+  *          This parameter can be one of the following values:
+  *            DAC_ALIGN_8B_R: 8bit right data alignment selected
+  *            DAC_ALIGN_12B_L: 12bit left data alignment selected
+  *            DAC_ALIGN_12B_R: 12bit right data alignment selected
+  * @param  Data1 Data for DAC Channel1 to be loaded in the selected data holding register.
+  * @param  Data2 Data for DAC Channel2 to be loaded in the selected data  holding register.
+  * @note   In dual mode, a unique register access is required to write in both
+  *          DAC channels at the same time.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
+{
+  uint32_t data;
+  uint32_t tmp;
+
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(Alignment));
+  assert_param(IS_DAC_DATA(Data1));
+  assert_param(IS_DAC_DATA(Data2));
+
+  /* Calculate and set dual DAC data holding register value */
+  if (Alignment == DAC_ALIGN_8B_R)
+  {
+    data = ((uint32_t)Data2 << 8U) | Data1;
+  }
+  else
+  {
+    data = ((uint32_t)Data2 << 16U) | Data1;
+  }
+
+  tmp = (uint32_t)hdac->Instance;
+  tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
+
+  /* Set the dual DAC selected data holding register */
+  *(__IO uint32_t *)tmp = data;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Conversion complete callback in non-blocking mode for Channel2.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Conversion half DMA transfer callback in non-blocking mode for Channel2.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Error DAC callback for Channel2.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DMA underrun DAC callback for Channel2.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
+   */
+}
+
+
+/**
+  * @brief  Run the self calibration of one DAC channel.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  sConfig DAC channel configuration structure.
+  * @param  Channel The selected DAC channel.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
+  * @retval Updates DAC_TrimmingValue. , DAC_UserTrimming set to DAC_UserTrimming
+  * @retval HAL status
+  * @note   Calibration runs about 7 ms.
+  */
+HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  __IO uint32_t tmp;
+  uint32_t trimmingvalue;
+  uint32_t delta;
+
+  /* store/restore channel configuration structure purpose */
+  uint32_t oldmodeconfiguration;
+
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+
+  /* Check the DAC handle allocation */
+  /* Check if DAC running */
+  if (hdac == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else if (hdac->State == HAL_DAC_STATE_BUSY)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Process locked */
+    __HAL_LOCK(hdac);
+
+    /* Store configuration */
+    oldmodeconfiguration = (hdac->Instance->MCR & (DAC_MCR_MODE1 << (Channel & 0x10UL)));
+
+    /* Disable the selected DAC channel */
+    CLEAR_BIT((hdac->Instance->CR), (DAC_CR_EN1 << (Channel & 0x10UL)));
+
+    /* Set mode in MCR  for calibration */
+    MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), 0U);
+
+    /* Set DAC Channel1 DHR register to the middle value */
+    tmp = (uint32_t)hdac->Instance;
+
+    if (Channel == DAC_CHANNEL_1)
+    {
+      tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R);
+    }
+    else
+    {
+      tmp += DAC_DHR12R2_ALIGNMENT(DAC_ALIGN_12B_R);
+    }
+
+    *(__IO uint32_t *) tmp = 0x0800UL;
+
+    /* Enable the selected DAC channel calibration */
+    /* i.e. set DAC_CR_CENx bit */
+    SET_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL)));
+
+    /* Init trimming counter */
+    /* Medium value */
+    trimmingvalue = 16UL;
+    delta = 8UL;
+    while (delta != 0UL)
+    {
+      /* Set candidate trimming */
+      MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
+
+      /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */
+      /* i.e. minimum time needed between two calibration steps */
+      HAL_Delay(1);
+
+      if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL)))
+      {
+        /* DAC_SR_CAL_FLAGx is HIGH try higher trimming */
+        trimmingvalue -= delta;
+      }
+      else
+      {
+        /* DAC_SR_CAL_FLAGx is LOW try lower trimming */
+        trimmingvalue += delta;
+      }
+      delta >>= 1UL;
+    }
+
+    /* Still need to check if right calibration is current value or one step below */
+    /* Indeed the first value that causes the DAC_SR_CAL_FLAGx bit to change from 0 to 1  */
+    /* Set candidate trimming */
+    MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
+
+    /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */
+    /* i.e. minimum time needed between two calibration steps */
+    HAL_Delay(1U);
+
+    if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL)
+    {
+      /* Trimming is actually one value more */
+      trimmingvalue++;
+      /* Set right trimming */
+      MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
+    }
+
+    /* Disable the selected DAC channel calibration */
+    /* i.e. clear DAC_CR_CENx bit */
+    CLEAR_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL)));
+
+    sConfig->DAC_TrimmingValue = trimmingvalue;
+    sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
+
+    /* Restore configuration */
+    MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), oldmodeconfiguration);
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hdac);
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Set the trimming mode and trimming value (user trimming mode applied).
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  sConfig DAC configuration structure updated with new DAC trimming value.
+  * @param  Channel The selected DAC channel.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
+  * @param  NewTrimmingValue DAC new trimming value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,
+                                            uint32_t NewTrimmingValue)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+  assert_param(IS_DAC_NEWTRIMMINGVALUE(NewTrimmingValue));
+
+  /* Check the DAC handle allocation */
+  if (hdac == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Process locked */
+    __HAL_LOCK(hdac);
+
+    /* Set new trimming */
+    MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (NewTrimmingValue << (Channel & 0x10UL)));
+
+    /* Update trimming mode */
+    sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
+    sConfig->DAC_TrimmingValue = NewTrimmingValue;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hdac);
+  }
+  return status;
+}
+
+/**
+  * @brief  Return the DAC trimming value.
+  * @param  hdac DAC handle
+  * @param  Channel The selected DAC channel.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
+  * @retval Trimming value : range: 0->31
+  *
+ */
+uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel)
+{
+  /* Check the parameter */
+  assert_param(IS_DAC_CHANNEL(Channel));
+
+  /* Retrieve trimming */
+  return ((hdac->Instance->CCR & (DAC_CCR_OTRIM1 << (Channel & 0x10UL))) >> (Channel & 0x10UL));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions
+  *  @brief    Extended Peripheral Control functions
+  *
+@verbatim
+  ==============================================================================
+             ##### Peripheral Control functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Set the specified data holding register value for DAC channel.
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Return the last data output value of the selected DAC channel.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval The selected DAC channel data output value.
+  */
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac)
+{
+  uint32_t tmp = 0UL;
+
+  tmp |= hdac->Instance->DOR1;
+
+  tmp |= hdac->Instance->DOR2 << 16UL;
+
+  /* Returns the DAC channel data output register value */
+  return tmp;
+}
+
+
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DACEx_Private_Functions DACEx private functions
+  *  @brief    Extended private functions
+  * @{
+  */
+
+
+/**
+  * @brief  DMA conversion complete callback.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
+{
+  DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+  hdac->ConvCpltCallbackCh2(hdac);
+#else
+  HAL_DACEx_ConvCpltCallbackCh2(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+  hdac->State = HAL_DAC_STATE_READY;
+}
+
+/**
+  * @brief  DMA half transfer complete callback.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
+{
+  DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+  /* Conversion complete callback */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+  hdac->ConvHalfCpltCallbackCh2(hdac);
+#else
+  HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA error callback.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
+{
+  DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Set DAC error code to DMA error */
+  hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
+
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+  hdac->ErrorCallbackCh2(hdac);
+#else
+  HAL_DACEx_ErrorCallbackCh2(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+  hdac->State = HAL_DAC_STATE_READY;
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* DAC1 */
+
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_iwdg.c

@@ -0,0 +1,282 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_iwdg.c
+  * @author  MCD Application Team
+  * @brief   IWDG HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Independent Watchdog (IWDG) peripheral:
+  *           + Initialization and Start functions
+  *           + IO operation functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                    ##### IWDG Generic features #####
+  ==============================================================================
+  [..]
+    (+) The IWDG can be started by either software or hardware (configurable
+        through option byte).
+
+    (+) The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays
+        active even if the main clock fails.
+
+    (+) Once the IWDG is started, the LSI is forced ON and both cannot be
+        disabled. The counter starts counting down from the reset value (0xFFF).
+        When it reaches the end of count value (0x000) a reset signal is
+        generated (IWDG reset).
+
+    (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
+        the IWDG_RLR value is reloaded into the counter and the watchdog reset
+        is prevented.
+
+    (+) The IWDG is implemented in the VDD voltage domain that is still functional
+        in STOP and STANDBY mode (IWDG reset can wake up the CPU from STANDBY).
+        IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
+        reset occurs.
+
+    (+) Debug mode: When the microcontroller enters debug mode (core halted),
+        the IWDG counter either continues to work normally or stops, depending
+        on DBG_IWDG_STOP configuration bit in DBG module, accessible through
+        __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros.
+
+    [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
+         The IWDG timeout may vary due to LSI clock frequency dispersion.
+         STM32G0xx devices provide the capability to measure the LSI clock
+         frequency (LSI clock is internally connected to TIM16 CH1 input capture).
+         The measured value can be used to have an IWDG timeout with an
+         acceptable accuracy.
+
+    [..] Default timeout value (necessary for IWDG_SR status register update):
+         Constant LSI_VALUE is defined based on the nominal LSI clock frequency.
+         This frequency being subject to variations as mentioned above, the
+         default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT
+         below) may become too short or too long.
+         In such cases, this default timeout value can be tuned by redefining
+         the constant LSI_VALUE at user-application level (based, for instance,
+         on the measured LSI clock frequency as explained above).
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    (#) Use IWDG using HAL_IWDG_Init() function to :
+      (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
+           clock is forced ON and IWDG counter starts counting down.
+      (++) Enable write access to configuration registers:
+          IWDG_PR, IWDG_RLR and IWDG_WINR.
+      (++) Configure the IWDG prescaler and counter reload value. This reload
+           value will be loaded in the IWDG counter each time the watchdog is
+           reloaded, then the IWDG will start counting down from this value.
+      (++) Depending on window parameter:
+        (+++) If Window Init parameter is same as Window register value,
+             nothing more is done but reload counter value in order to exit
+             function with exact time base.
+        (+++) Else modify Window register. This will automatically reload
+             watchdog counter.
+      (++) Wait for status flags to be reset.
+
+    (#) Then the application program must refresh the IWDG counter at regular
+        intervals during normal operation to prevent an MCU reset, using
+        HAL_IWDG_Refresh() function.
+
+     *** IWDG HAL driver macros list ***
+     ====================================
+     [..]
+       Below the list of most used macros in IWDG HAL driver:
+      (+) __HAL_IWDG_START: Enable the IWDG peripheral
+      (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
+          the reload register
+
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal.h"
+
+/** @addtogroup STM32G0xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+/** @addtogroup IWDG
+  * @brief IWDG HAL module driver.
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup IWDG_Private_Defines IWDG Private Defines
+  * @{
+  */
+/* Status register needs up to 5 LSI clock periods divided by the clock
+   prescaler to be updated. The number of LSI clock periods is upper-rounded to
+   6 for the timeout value calculation.
+   The timeout value is calculated using the highest prescaler (256) and
+   the LSI_VALUE constant. The value of this constant can be changed by the user
+   to take into account possible LSI clock period variations.
+   The timeout value is multiplied by 1000 to be converted in milliseconds.
+   LSI startup time is also considered here by adding LSI_STARTUP_TIME
+   converted in milliseconds. */
+#define HAL_IWDG_DEFAULT_TIMEOUT        (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL))
+#define IWDG_KERNEL_UPDATE_FLAGS        (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU)
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup IWDG_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup IWDG_Exported_Functions_Group1
+  *  @brief    Initialization and Start functions.
+  *
+@verbatim
+ ===============================================================================
+          ##### Initialization and Start functions #####
+ ===============================================================================
+ [..]  This section provides functions allowing to:
+      (+) Initialize the IWDG according to the specified parameters in the
+          IWDG_InitTypeDef of associated handle.
+      (+) Manage Window option.
+      (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
+          is reloaded in order to exit function with correct time base.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the IWDG according to the specified parameters in the
+  *         IWDG_InitTypeDef and start watchdog. Before exiting function,
+  *         watchdog is refreshed in order to have correct time base.
+  * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified IWDG module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
+{
+  uint32_t tickstart;
+
+  /* Check the IWDG handle allocation */
+  if (hiwdg == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
+  assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
+  assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
+  assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
+
+  /* Enable IWDG. LSI is turned on automatically */
+  __HAL_IWDG_START(hiwdg);
+
+  /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing
+  0x5555 in KR */
+  IWDG_ENABLE_WRITE_ACCESS(hiwdg);
+
+  /* Write to IWDG registers the Prescaler & Reload values to work with */
+  hiwdg->Instance->PR = hiwdg->Init.Prescaler;
+  hiwdg->Instance->RLR = hiwdg->Init.Reload;
+
+  /* Check pending flag, if previous update not done, return timeout */
+  tickstart = HAL_GetTick();
+
+  /* Wait for register to be updated */
+  while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
+  {
+    if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
+    {
+      if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /* If window parameter is different than current value, modify window
+  register */
+  if (hiwdg->Instance->WINR != hiwdg->Init.Window)
+  {
+    /* Write to IWDG WINR the IWDG_Window value to compare with. In any case,
+    even if window feature is disabled, Watchdog will be reloaded by writing
+    windows register */
+    hiwdg->Instance->WINR = hiwdg->Init.Window;
+  }
+  else
+  {
+    /* Reload IWDG counter with value defined in the reload register */
+    __HAL_IWDG_RELOAD_COUNTER(hiwdg);
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup IWDG_Exported_Functions_Group2
+  *  @brief   IO operation functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+ [..]  This section provides functions allowing to:
+      (+) Refresh the IWDG.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Refresh the IWDG.
+  * @param  hiwdg  pointer to a IWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified IWDG module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
+{
+  /* Reload IWDG counter with value defined in the reload register */
+  __HAL_IWDG_RELOAD_COUNTER(hiwdg);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_IWDG_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pcd_ex.c

@@ -0,0 +1,333 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_pcd_ex.c
+  * @author  MCD Application Team
+  * @brief   PCD Extended HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the USB Peripheral Controller:
+  *           + Extended features functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal.h"
+
+/** @addtogroup STM32G0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PCDEx PCDEx
+  * @brief PCD Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+
+#if defined (USB_DRD_FS)
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
+  * @{
+  */
+
+/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
+  * @brief    PCDEx control functions
+  *
+@verbatim
+ ===============================================================================
+                 ##### Extended features functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Update FIFO configuration
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure PMA for EP
+  * @param  hpcd  Device instance
+  * @param  ep_addr endpoint address
+  * @param  ep_kind endpoint Kind
+  *                  USB_SNG_BUF: Single Buffer used
+  *                  USB_DBL_BUF: Double Buffer used
+  * @param  pmaadress: EP address in The PMA: In case of single buffer endpoint
+  *                   this parameter is 16-bit value providing the address
+  *                   in PMA allocated to endpoint.
+  *                   In case of double buffer endpoint this parameter
+  *                   is a 32-bit value providing the endpoint buffer 0 address
+  *                   in the LSB part of 32-bit value and endpoint buffer 1 address
+  *                   in the MSB part of 32-bit value.
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef  HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
+                                       uint16_t ep_kind, uint32_t pmaadress)
+{
+  PCD_EPTypeDef *ep;
+
+  /* initialize ep structure*/
+  if ((0x80U & ep_addr) == 0x80U)
+  {
+    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+  }
+  else
+  {
+    ep = &hpcd->OUT_ep[ep_addr];
+  }
+
+  /* Here we check if the endpoint is single or double Buffer*/
+  if (ep_kind == PCD_SNG_BUF)
+  {
+    /* Single Buffer */
+    ep->doublebuffer = 0U;
+    /* Configure the PMA */
+    ep->pmaadress = (uint16_t)pmaadress;
+  }
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+  else /* USB_DBL_BUF */
+  {
+    /* Double Buffer Endpoint */
+    ep->doublebuffer = 1U;
+    /* Configure the PMA */
+    ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU);
+    ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16);
+  }
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Activate BatteryCharging feature.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
+{
+  USB_DRD_TypeDef *USBx = hpcd->Instance;
+  hpcd->battery_charging_active = 1U;
+
+  /* Enable BCD feature */
+  USBx->BCDR |= USB_BCDR_BCDEN;
+
+  /* Enable DCD : Data Contact Detect */
+  USBx->BCDR &= ~(USB_BCDR_PDEN);
+  USBx->BCDR &= ~(USB_BCDR_SDEN);
+  USBx->BCDR |= USB_BCDR_DCDEN;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deactivate BatteryCharging feature.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
+{
+  USB_DRD_TypeDef *USBx = hpcd->Instance;
+  hpcd->battery_charging_active = 0U;
+
+  /* Disable BCD feature */
+  USBx->BCDR &= ~(USB_BCDR_BCDEN);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle BatteryCharging Process.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
+{
+  USB_DRD_TypeDef *USBx = hpcd->Instance;
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Wait for Min DCD Timeout */
+  HAL_Delay(300U);
+
+  /* Data Pin Contact ? Check Detect flag */
+  if ((USBx->BCDR & USB_BCDR_DCDET) == USB_BCDR_DCDET)
+  {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+    hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION);
+#else
+    HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+  }
+  /* Primary detection: checks if connected to Standard Downstream Port
+  (without charging capability) */
+  USBx->BCDR &= ~(USB_BCDR_DCDEN);
+  HAL_Delay(50U);
+  USBx->BCDR |= (USB_BCDR_PDEN);
+  HAL_Delay(50U);
+
+  /* If Charger detect ? */
+  if ((USBx->BCDR & USB_BCDR_PDET) == USB_BCDR_PDET)
+  {
+    /* Start secondary detection to check connection to Charging Downstream
+    Port or Dedicated Charging Port */
+    USBx->BCDR &= ~(USB_BCDR_PDEN);
+    HAL_Delay(50U);
+    USBx->BCDR |= (USB_BCDR_SDEN);
+    HAL_Delay(50U);
+
+    /* If CDP ? */
+    if ((USBx->BCDR & USB_BCDR_SDET) == USB_BCDR_SDET)
+    {
+      /* Dedicated Downstream Port DCP */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
+#else
+      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      /* Charging Downstream Port CDP */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+      hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
+#else
+      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+    }
+  }
+  else /* NO */
+  {
+    /* Standard Downstream Port */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+    hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
+#else
+    HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+  }
+
+  /* Battery Charging capability discovery finished Start Enumeration */
+  (void)HAL_PCDEx_DeActivateBCD(hpcd);
+
+  /* Check for the Timeout, else start USB Device */
+  if ((HAL_GetTick() - tickstart) > 1000U)
+  {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+    hpcd->BCDCallback(hpcd, PCD_BCD_ERROR);
+#else
+    HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+  }
+  else
+  {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+    hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
+#else
+    HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+  }
+}
+
+
+/**
+  * @brief  Activate LPM feature.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
+{
+
+  USB_DRD_TypeDef *USBx = hpcd->Instance;
+  hpcd->lpm_active = 1U;
+  hpcd->LPM_State = LPM_L0;
+
+  USBx->LPMCSR |= USB_LPMCSR_LMPEN;
+  USBx->LPMCSR |= USB_LPMCSR_LPMACK;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deactivate LPM feature.
+  * @param  hpcd PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
+{
+  USB_DRD_TypeDef *USBx = hpcd->Instance;
+
+  hpcd->lpm_active = 0U;
+
+  USBx->LPMCSR &= ~(USB_LPMCSR_LMPEN);
+  USBx->LPMCSR &= ~(USB_LPMCSR_LPMACK);
+
+  return HAL_OK;
+}
+
+
+
+/**
+  * @brief  Send LPM message to user layer callback.
+  * @param  hpcd PCD handle
+  * @param  msg LPM message
+  * @retval HAL status
+  */
+__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(msg);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCDEx_LPM_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Send BatteryCharging message to user layer callback.
+  * @param  hpcd PCD handle
+  * @param  msg LPM message
+  * @retval HAL status
+  */
+__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(msg);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCDEx_BCD_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* defined (USB_DRD_FS) */
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rng.c

@@ -0,0 +1,839 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_rng.c
+  * @author  MCD Application Team
+  * @brief   RNG HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Random Number Generator (RNG) peripheral:
+  *           + Initialization and configuration functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+      The RNG HAL driver can be used as follows:
+
+      (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro
+          in HAL_RNG_MspInit().
+      (#) Activate the RNG peripheral using HAL_RNG_Init() function.
+      (#) Wait until the 32 bit Random Number Generator contains a valid
+          random data using (polling/interrupt) mode.
+      (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.
+
+    ##### Callback registration #####
+    ==================================
+
+    [..]
+    The compilation define USE_HAL_RNG_REGISTER_CALLBACKS when set to 1
+    allows the user to configure dynamically the driver callbacks.
+
+    [..]
+    Use Function HAL_RNG_RegisterCallback() to register a user callback.
+    Function HAL_RNG_RegisterCallback() allows to register following callbacks:
+    (+) ErrorCallback             : RNG Error Callback.
+    (+) MspInitCallback           : RNG MspInit.
+    (+) MspDeInitCallback         : RNG MspDeInit.
+    This function takes as parameters the HAL peripheral handle, the Callback ID
+    and a pointer to the user callback function.
+
+    [..]
+    Use function HAL_RNG_UnRegisterCallback() to reset a callback to the default
+    weak (surcharged) function.
+    HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+    and the Callback ID.
+    This function allows to reset following callbacks:
+    (+) ErrorCallback             : RNG Error Callback.
+    (+) MspInitCallback           : RNG MspInit.
+    (+) MspDeInitCallback         : RNG MspDeInit.
+
+    [..]
+    For specific callback ReadyDataCallback, use dedicated register callbacks:
+    respectively HAL_RNG_RegisterReadyDataCallback() , HAL_RNG_UnRegisterReadyDataCallback().
+
+    [..]
+    By default, after the HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET
+    all callbacks are set to the corresponding weak (surcharged) functions:
+    example HAL_RNG_ErrorCallback().
+    Exception done for MspInit and MspDeInit functions that are respectively
+    reset to the legacy weak (surcharged) functions in the HAL_RNG_Init()
+    and HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the HAL_RNG_Init() and HAL_RNG_DeInit()
+    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+    [..]
+    Callbacks can be registered/unregistered in HAL_RNG_STATE_READY state only.
+    Exception done MspInit/MspDeInit that can be registered/unregistered
+    in HAL_RNG_STATE_READY or HAL_RNG_STATE_RESET state, thus registered (user)
+    MspInit/DeInit callbacks can be used during the Init/DeInit.
+    In that case first register the MspInit/MspDeInit user callbacks
+    using HAL_RNG_RegisterCallback() before calling HAL_RNG_DeInit()
+    or HAL_RNG_Init() function.
+
+    [..]
+    When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or
+    not defined, the callback registration feature is not available
+    and weak (surcharged) callbacks are used.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal.h"
+
+/** @addtogroup STM32G0xx_HAL_Driver
+  * @{
+  */
+
+#if defined (RNG)
+
+/** @addtogroup RNG
+  * @brief RNG HAL module driver.
+  * @{
+  */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RNG_Private_Constants RNG Private Constants
+  * @{
+  */
+#define RNG_TIMEOUT_VALUE     2U
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+/* Private functions prototypes ----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup RNG_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup RNG_Exported_Functions_Group1
+  *  @brief   Initialization and configuration functions
+  *
+@verbatim
+ ===============================================================================
+          ##### Initialization and configuration functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize the RNG according to the specified parameters
+          in the RNG_InitTypeDef and create the associated handle
+      (+) DeInitialize the RNG peripheral
+      (+) Initialize the RNG MSP
+      (+) DeInitialize RNG MSP
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the RNG peripheral and creates the associated handle.
+  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
+  *                the configuration information for RNG.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
+{
+  /* Check the RNG handle allocation */
+  if (hrng == NULL)
+  {
+    return HAL_ERROR;
+  }
+  /* Check the parameters */
+  assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance));
+  assert_param(IS_RNG_CED(hrng->Init.ClockErrorDetection));
+
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+  if (hrng->State == HAL_RNG_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hrng->Lock = HAL_UNLOCKED;
+
+    hrng->ReadyDataCallback  = HAL_RNG_ReadyDataCallback;  /* Legacy weak ReadyDataCallback  */
+    hrng->ErrorCallback      = HAL_RNG_ErrorCallback;      /* Legacy weak ErrorCallback      */
+
+    if (hrng->MspInitCallback == NULL)
+    {
+      hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit  */
+    }
+
+    /* Init the low level hardware */
+    hrng->MspInitCallback(hrng);
+  }
+#else
+  if (hrng->State == HAL_RNG_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hrng->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware */
+    HAL_RNG_MspInit(hrng);
+  }
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+
+  /* Change RNG peripheral state */
+  hrng->State = HAL_RNG_STATE_BUSY;
+
+  /* Clock Error Detection Configuration */
+  MODIFY_REG(hrng->Instance->CR, RNG_CR_CED, hrng->Init.ClockErrorDetection);
+
+  /* Enable the RNG Peripheral */
+  __HAL_RNG_ENABLE(hrng);
+
+  /* Initialize the RNG state */
+  hrng->State = HAL_RNG_STATE_READY;
+
+  /* Initialise the error code */
+  hrng->ErrorCode = HAL_RNG_ERROR_NONE;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the RNG peripheral.
+  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
+  *                the configuration information for RNG.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
+{
+  /* Check the RNG handle allocation */
+  if (hrng == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Clear Clock Error Detection bit */
+  CLEAR_BIT(hrng->Instance->CR, RNG_CR_CED);
+  /* Disable the RNG Peripheral */
+  CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN);
+
+  /* Clear RNG interrupt status flags */
+  CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS);
+
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+  if (hrng->MspDeInitCallback == NULL)
+  {
+    hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit  */
+  }
+
+  /* DeInit the low level hardware */
+  hrng->MspDeInitCallback(hrng);
+#else
+  /* DeInit the low level hardware */
+  HAL_RNG_MspDeInit(hrng);
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+
+  /* Update the RNG state */
+  hrng->State = HAL_RNG_STATE_RESET;
+
+  /* Initialise the error code */
+  hrng->ErrorCode = HAL_RNG_ERROR_NONE;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hrng);
+
+  /* Return the function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the RNG MSP.
+  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
+  *                the configuration information for RNG.
+  * @retval None
+  */
+__weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrng);
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_RNG_MspInit must be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  DeInitializes the RNG MSP.
+  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
+  *                the configuration information for RNG.
+  * @retval None
+  */
+__weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrng);
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_RNG_MspDeInit must be implemented in the user file.
+   */
+}
+
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User RNG Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hrng RNG handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_RNG_ERROR_CB_ID Error callback ID
+  *          @arg @ref HAL_RNG_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID,
+                                           pRNG_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hrng);
+
+  if (HAL_RNG_STATE_READY == hrng->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_RNG_ERROR_CB_ID :
+        hrng->ErrorCallback = pCallback;
+        break;
+
+      case HAL_RNG_MSPINIT_CB_ID :
+        hrng->MspInitCallback = pCallback;
+        break;
+
+      case HAL_RNG_MSPDEINIT_CB_ID :
+        hrng->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_RNG_STATE_RESET == hrng->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_RNG_MSPINIT_CB_ID :
+        hrng->MspInitCallback = pCallback;
+        break;
+
+      case HAL_RNG_MSPDEINIT_CB_ID :
+        hrng->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hrng);
+  return status;
+}
+
+/**
+  * @brief  Unregister an RNG Callback
+  *         RNG callback is redirected to the weak predefined callback
+  * @param  hrng RNG handle
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_RNG_ERROR_CB_ID Error callback ID
+  *          @arg @ref HAL_RNG_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hrng);
+
+  if (HAL_RNG_STATE_READY == hrng->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_RNG_ERROR_CB_ID :
+        hrng->ErrorCallback = HAL_RNG_ErrorCallback;          /* Legacy weak ErrorCallback  */
+        break;
+
+      case HAL_RNG_MSPINIT_CB_ID :
+        hrng->MspInitCallback = HAL_RNG_MspInit;              /* Legacy weak MspInit  */
+        break;
+
+      case HAL_RNG_MSPDEINIT_CB_ID :
+        hrng->MspDeInitCallback = HAL_RNG_MspDeInit;          /* Legacy weak MspDeInit  */
+        break;
+
+      default :
+        /* Update the error code */
+        hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_RNG_STATE_RESET == hrng->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_RNG_MSPINIT_CB_ID :
+        hrng->MspInitCallback = HAL_RNG_MspInit;              /* Legacy weak MspInit  */
+        break;
+
+      case HAL_RNG_MSPDEINIT_CB_ID :
+        hrng->MspDeInitCallback = HAL_RNG_MspDeInit;          /* Legacy weak MspInit  */
+        break;
+
+      default :
+        /* Update the error code */
+        hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hrng);
+  return status;
+}
+
+/**
+  * @brief  Register Data Ready RNG Callback
+  *         To be used instead of the weak HAL_RNG_ReadyDataCallback() predefined callback
+  * @param  hrng RNG handle
+  * @param  pCallback pointer to the Data Ready Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(hrng);
+
+  if (HAL_RNG_STATE_READY == hrng->State)
+  {
+    hrng->ReadyDataCallback = pCallback;
+  }
+  else
+  {
+    /* Update the error code */
+    hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hrng);
+  return status;
+}
+
+/**
+  * @brief  UnRegister the Data Ready RNG Callback
+  *         Data Ready RNG Callback is redirected to the weak HAL_RNG_ReadyDataCallback() predefined callback
+  * @param  hrng RNG handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hrng);
+
+  if (HAL_RNG_STATE_READY == hrng->State)
+  {
+    hrng->ReadyDataCallback = HAL_RNG_ReadyDataCallback; /* Legacy weak ReadyDataCallback  */
+  }
+  else
+  {
+    /* Update the error code */
+    hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hrng);
+  return status;
+}
+
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @addtogroup RNG_Exported_Functions_Group2
+  *  @brief   Peripheral Control functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Get the 32 bit Random number
+      (+) Get the 32 bit Random number with interrupt enabled
+      (+) Handle RNG interrupt request
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Generates a 32-bit random number.
+  * @note   This function checks value of RNG_FLAG_DRDY flag to know if valid
+  *         random number is available in the DR register (RNG_FLAG_DRDY flag set
+  *         whenever a random number is available through the RNG_DR register).
+  *         After transitioning from 0 to 1 (random number available),
+  *         RNG_FLAG_DRDY flag remains high until output buffer becomes empty after reading
+  *         four words from the RNG_DR register, i.e. further function calls
+  *         will immediately return a new u32 random number (additional words are
+  *         available and can be read by the application, till RNG_FLAG_DRDY flag remains high).
+  * @note   When no more random number data is available in DR register, RNG_FLAG_DRDY
+  *         flag is automatically cleared.
+  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
+  *                the configuration information for RNG.
+  * @param  random32bit pointer to generated random number variable if successful.
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit)
+{
+  uint32_t tickstart;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process Locked */
+  __HAL_LOCK(hrng);
+
+  /* Check RNG peripheral state */
+  if (hrng->State == HAL_RNG_STATE_READY)
+  {
+    /* Change RNG peripheral state */
+    hrng->State = HAL_RNG_STATE_BUSY;
+
+    /* Get tick */
+    tickstart = HAL_GetTick();
+
+    /* Check if data register contains valid random data */
+    while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
+    {
+      if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
+        {
+          hrng->State = HAL_RNG_STATE_READY;
+          hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
+          /* Process Unlocked */
+          __HAL_UNLOCK(hrng);
+          return HAL_ERROR;
+        }
+      }
+    }
+
+    /* Get a 32bit Random number */
+    hrng->RandomNumber = hrng->Instance->DR;
+    *random32bit = hrng->RandomNumber;
+
+    hrng->State = HAL_RNG_STATE_READY;
+  }
+  else
+  {
+    hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
+    status = HAL_ERROR;
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrng);
+
+  return status;
+}
+
+/**
+  * @brief  Generates a 32-bit random number in interrupt mode.
+  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
+  *                the configuration information for RNG.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process Locked */
+  __HAL_LOCK(hrng);
+
+  /* Check RNG peripheral state */
+  if (hrng->State == HAL_RNG_STATE_READY)
+  {
+    /* Change RNG peripheral state */
+    hrng->State = HAL_RNG_STATE_BUSY;
+
+    /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
+    __HAL_RNG_ENABLE_IT(hrng);
+  }
+  else
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hrng);
+
+    hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
+    status = HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Handles RNG interrupt request.
+  * @note   In the case of a clock error, the RNG is no more able to generate
+  *         random numbers because the PLL48CLK clock is not correct. User has
+  *         to check that the clock controller is correctly configured to provide
+  *         the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT().
+  *         The clock error has no impact on the previously generated
+  *         random numbers, and the RNG_DR register contents can be used.
+  * @note   In the case of a seed error, the generation of random numbers is
+  *         interrupted as long as the SECS bit is '1'. If a number is
+  *         available in the RNG_DR register, it must not be used because it may
+  *         not have enough entropy. In this case, it is recommended to clear the
+  *         SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable
+  *         the RNG peripheral to reinitialize and restart the RNG.
+  * @note   User-written HAL_RNG_ErrorCallback() API is called once whether SEIS
+  *         or CEIS are set.
+  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
+  *                the configuration information for RNG.
+  * @retval None
+
+  */
+void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
+{
+  uint32_t rngclockerror = 0U;
+
+  /* RNG clock error interrupt occurred */
+  if (__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET)
+  {
+    /* Update the error code */
+    hrng->ErrorCode = HAL_RNG_ERROR_CLOCK;
+    rngclockerror = 1U;
+  }
+  else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
+  {
+    /* Update the error code */
+    hrng->ErrorCode = HAL_RNG_ERROR_SEED;
+    rngclockerror = 1U;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  if (rngclockerror == 1U)
+  {
+    /* Change RNG peripheral state */
+    hrng->State = HAL_RNG_STATE_ERROR;
+
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+    /* Call registered Error callback */
+    hrng->ErrorCallback(hrng);
+#else
+    /* Call legacy weak Error callback */
+    HAL_RNG_ErrorCallback(hrng);
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+
+    /* Clear the clock error flag */
+    __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI | RNG_IT_SEI);
+
+    return;
+  }
+
+  /* Check RNG data ready interrupt occurred */
+  if (__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)
+  {
+    /* Generate random number once, so disable the IT */
+    __HAL_RNG_DISABLE_IT(hrng);
+
+    /* Get the 32bit Random number (DRDY flag automatically cleared) */
+    hrng->RandomNumber = hrng->Instance->DR;
+
+    if (hrng->State != HAL_RNG_STATE_ERROR)
+    {
+      /* Change RNG peripheral state */
+      hrng->State = HAL_RNG_STATE_READY;
+      /* Process Unlocked */
+      __HAL_UNLOCK(hrng);
+
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+      /* Call registered Data Ready callback */
+      hrng->ReadyDataCallback(hrng, hrng->RandomNumber);
+#else
+      /* Call legacy weak Data Ready callback */
+      HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber);
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+    }
+  }
+}
+
+/**
+  * @brief  Read latest generated random number.
+  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
+  *                the configuration information for RNG.
+  * @retval random value
+  */
+uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)
+{
+  return (hrng->RandomNumber);
+}
+
+/**
+  * @brief  Data Ready callback in non-blocking mode.
+  * @note   When RNG_FLAG_DRDY flag value is set, first random number has been read
+  *         from DR register in IRQ Handler and is provided as callback parameter.
+  *         Depending on valid data available in the conditioning output buffer,
+  *         additional words can be read by the application from DR register till
+  *         DRDY bit remains high.
+  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
+  *                the configuration information for RNG.
+  * @param  random32bit generated random number.
+  * @retval None
+  */
+__weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrng);
+  UNUSED(random32bit);
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_RNG_ReadyDataCallback must be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  RNG error callbacks.
+  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
+  *                the configuration information for RNG.
+  * @retval None
+  */
+__weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrng);
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_RNG_ErrorCallback must be implemented in the user file.
+   */
+}
+/**
+  * @}
+  */
+
+
+/** @addtogroup RNG_Exported_Functions_Group3
+  *  @brief   Peripheral State functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral State functions #####
+ ===============================================================================
+    [..]
+    This subsection permits to get in run-time the status of the peripheral
+    and the data flow.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the RNG state.
+  * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
+  *                the configuration information for RNG.
+  * @retval HAL state
+  */
+HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
+{
+  return hrng->State;
+}
+
+/**
+  * @brief  Return the RNG handle error code.
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
+  * @retval RNG Error Code
+  */
+uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng)
+{
+  /* Return RNG Error Code */
+  return hrng->ErrorCode;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+#endif /* HAL_RNG_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+#endif /* RNG */
+
+/**
+  * @}
+  */
+

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_smartcard_ex.c

@@ -0,0 +1,495 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_smartcard_ex.c
+  * @author  MCD Application Team
+  * @brief   SMARTCARD HAL module driver.
+  *          This file provides extended firmware functions to manage the following
+  *          functionalities of the SmartCard.
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  =============================================================================
+               ##### SMARTCARD peripheral extended features  #####
+  =============================================================================
+  [..]
+  The Extended SMARTCARD HAL driver can be used as follows:
+
+    (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
+        then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut,
+        auto-retry counter,...) in the hsmartcard AdvancedInit structure.
+
+    (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
+
+        -@- When SMARTCARD operates in FIFO mode, FIFO mode must be enabled prior
+            starting RX/TX transfers. Also RX/TX FIFO thresholds must be
+            configured prior starting RX/TX transfers.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal.h"
+
+/** @addtogroup STM32G0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SMARTCARDEx SMARTCARDEx
+  * @brief SMARTCARD Extended HAL module driver
+  * @{
+  */
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup SMARTCARDEx_Private_Constants SMARTCARD Extended Private Constants
+  * @{
+  */
+/* UART RX FIFO depth */
+#define RX_FIFO_DEPTH 8U
+
+/* UART TX FIFO depth */
+#define TX_FIFO_DEPTH 8U
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard);
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SMARTCARDEx_Exported_Functions  SMARTCARD Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup SMARTCARDEx_Exported_Functions_Group1 Extended Peripheral Control functions
+  * @brief    Extended control functions
+  *
+@verbatim
+  ===============================================================================
+                      ##### Peripheral Control functions #####
+  ===============================================================================
+  [..]
+  This subsection provides a set of functions allowing to initialize the SMARTCARD.
+     (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly
+     (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly
+     (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature
+     (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature
+
+@endverbatim
+  * @{
+  */
+
+/** @brief Update on the fly the SMARTCARD block length in RTOR register.
+  * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @param BlockLength SMARTCARD block length (8-bit long at most)
+  * @retval None
+  */
+void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
+{
+  MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << USART_RTOR_BLEN_Pos));
+}
+
+/** @brief Update on the fly the receiver timeout value in RTOR register.
+  * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @param TimeOutValue receiver timeout value in number of baud blocks. The timeout
+  *                     value must be less or equal to 0x0FFFFFFFF.
+  * @retval None
+  */
+void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
+{
+  assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
+  MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_RTO, TimeOutValue);
+}
+
+/** @brief Enable the SMARTCARD receiver timeout feature.
+  * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsmartcard);
+
+    hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+    /* Set the USART RTOEN bit */
+    SET_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
+
+    hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmartcard);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/** @brief Disable the SMARTCARD receiver timeout feature.
+  * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsmartcard);
+
+    hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+    /* Clear the USART RTOEN bit */
+    CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
+
+    hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmartcard);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARDEx_Exported_Functions_Group2 Extended Peripheral IO operation functions
+  * @brief   SMARTCARD Transmit and Receive functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of FIFO mode related callback functions.
+
+    (#) TX/RX Fifos Callbacks:
+        (++) HAL_SMARTCARDEx_RxFifoFullCallback()
+        (++) HAL_SMARTCARDEx_TxFifoEmptyCallback()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  SMARTCARD RX Fifo full callback.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                   the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARDEx_RxFifoFullCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmartcard);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARDEx_RxFifoFullCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  SMARTCARD TX Fifo empty callback.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                   the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARDEx_TxFifoEmptyCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmartcard);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARDEx_TxFifoEmptyCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARDEx_Exported_Functions_Group3 Extended Peripheral FIFO Control functions
+  *  @brief   SMARTCARD control functions
+  *
+@verbatim
+ ===============================================================================
+                  ##### Peripheral FIFO Control functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the SMARTCARD
+    FIFO feature.
+     (+) HAL_SMARTCARDEx_EnableFifoMode() API enables the FIFO mode
+     (+) HAL_SMARTCARDEx_DisableFifoMode() API disables the FIFO mode
+     (+) HAL_SMARTCARDEx_SetTxFifoThreshold() API sets the TX FIFO threshold
+     (+) HAL_SMARTCARDEx_SetRxFifoThreshold() API sets the RX FIFO threshold
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enable the FIFO mode.
+  * @param hsmartcard SMARTCARD handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  uint32_t tmpcr1;
+
+  /* Check parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
+
+  /* Process Locked */
+  __HAL_LOCK(hsmartcard);
+
+  hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+  /* Save actual SMARTCARD configuration */
+  tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
+
+  /* Disable SMARTCARD */
+  __HAL_SMARTCARD_DISABLE(hsmartcard);
+
+  /* Enable FIFO mode */
+  SET_BIT(tmpcr1, USART_CR1_FIFOEN);
+  hsmartcard->FifoMode = SMARTCARD_FIFOMODE_ENABLE;
+
+  /* Restore SMARTCARD configuration */
+  WRITE_REG(hsmartcard->Instance->CR1, tmpcr1);
+
+  /* Determine the number of data to process during RX/TX ISR execution */
+  SMARTCARDEx_SetNbDataToProcess(hsmartcard);
+
+  hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsmartcard);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the FIFO mode.
+  * @param hsmartcard SMARTCARD handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  uint32_t tmpcr1;
+
+  /* Check parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
+
+  /* Process Locked */
+  __HAL_LOCK(hsmartcard);
+
+  hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+  /* Save actual SMARTCARD configuration */
+  tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
+
+  /* Disable SMARTCARD */
+  __HAL_SMARTCARD_DISABLE(hsmartcard);
+
+  /* Enable FIFO mode */
+  CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
+  hsmartcard->FifoMode = SMARTCARD_FIFOMODE_DISABLE;
+
+  /* Restore SMARTCARD configuration */
+  WRITE_REG(hsmartcard->Instance->CR1, tmpcr1);
+
+  hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsmartcard);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the TXFIFO threshold.
+  * @param hsmartcard      SMARTCARD handle.
+  * @param Threshold  TX FIFO threshold value
+  *          This parameter can be one of the following values:
+  *            @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_8
+  *            @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_4
+  *            @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_2
+  *            @arg @ref SMARTCARD_TXFIFO_THRESHOLD_3_4
+  *            @arg @ref SMARTCARD_TXFIFO_THRESHOLD_7_8
+  *            @arg @ref SMARTCARD_TXFIFO_THRESHOLD_8_8
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
+{
+  uint32_t tmpcr1;
+
+  /* Check parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
+  assert_param(IS_SMARTCARD_TXFIFO_THRESHOLD(Threshold));
+
+  /* Process Locked */
+  __HAL_LOCK(hsmartcard);
+
+  hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+  /* Save actual SMARTCARD configuration */
+  tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
+
+  /* Disable SMARTCARD */
+  __HAL_SMARTCARD_DISABLE(hsmartcard);
+
+  /* Update TX threshold configuration */
+  MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
+
+  /* Determine the number of data to process during RX/TX ISR execution */
+  SMARTCARDEx_SetNbDataToProcess(hsmartcard);
+
+  /* Restore SMARTCARD configuration */
+  MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_UE, tmpcr1);
+
+  hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsmartcard);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the RXFIFO threshold.
+  * @param hsmartcard      SMARTCARD handle.
+  * @param Threshold  RX FIFO threshold value
+  *          This parameter can be one of the following values:
+  *            @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_8
+  *            @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_4
+  *            @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_2
+  *            @arg @ref SMARTCARD_RXFIFO_THRESHOLD_3_4
+  *            @arg @ref SMARTCARD_RXFIFO_THRESHOLD_7_8
+  *            @arg @ref SMARTCARD_RXFIFO_THRESHOLD_8_8
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold)
+{
+  uint32_t tmpcr1;
+
+  /* Check parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance));
+  assert_param(IS_SMARTCARD_RXFIFO_THRESHOLD(Threshold));
+
+  /* Process Locked */
+  __HAL_LOCK(hsmartcard);
+
+  hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+  /* Save actual SMARTCARD configuration */
+  tmpcr1 = READ_REG(hsmartcard->Instance->CR1);
+
+  /* Disable SMARTCARD */
+  __HAL_SMARTCARD_DISABLE(hsmartcard);
+
+  /* Update RX threshold configuration */
+  MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
+
+  /* Determine the number of data to process during RX/TX ISR execution */
+  SMARTCARDEx_SetNbDataToProcess(hsmartcard);
+
+  /* Restore SMARTCARD configuration */
+  MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_UE, tmpcr1);
+
+  hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsmartcard);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARDEx_Private_Functions  SMARTCARD Extended Private Functions
+  * @{
+  */
+
+/**
+  * @brief Calculate the number of data to process in RX/TX ISR.
+  * @note The RX FIFO depth and the TX FIFO depth is extracted from
+  *       the USART configuration registers.
+  * @param hsmartcard SMARTCARD handle.
+  * @retval None
+  */
+static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  uint8_t rx_fifo_depth;
+  uint8_t tx_fifo_depth;
+  uint8_t rx_fifo_threshold;
+  uint8_t tx_fifo_threshold;
+  /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */
+  static const uint8_t numerator[]   = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
+  static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
+
+  if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_DISABLE)
+  {
+    hsmartcard->NbTxDataToProcess = 1U;
+    hsmartcard->NbRxDataToProcess = 1U;
+  }
+  else
+  {
+    rx_fifo_depth = RX_FIFO_DEPTH;
+    tx_fifo_depth = TX_FIFO_DEPTH;
+    rx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
+    tx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
+    hsmartcard->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / \
+                                    (uint16_t)denominator[tx_fifo_threshold];
+    hsmartcard->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / \
+                                    (uint16_t)denominator[rx_fifo_threshold];
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_smbus_ex.c

@@ -0,0 +1,250 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_smbus_ex.c
+  * @author  MCD Application Team
+  * @brief   SMBUS Extended HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of SMBUS Extended peripheral:
+  *           + Extended features functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+               ##### SMBUS peripheral Extended features  #####
+  ==============================================================================
+
+  [..] Comparing to other previous devices, the SMBUS interface for STM32G0xx
+       devices contains the following additional features
+
+       (+) Disable or enable wakeup from Stop mode(s)
+       (+) Disable or enable Fast Mode Plus
+
+                     ##### How to use this driver #####
+  ==============================================================================
+    (#) Configure the enable or disable of SMBUS Wake Up Mode using the functions :
+          (++) HAL_SMBUSEx_EnableWakeUp()
+          (++) HAL_SMBUSEx_DisableWakeUp()
+    (#) Configure the enable or disable of fast mode plus driving capability using the functions :
+          (++) HAL_SMBUSEx_EnableFastModePlus()
+          (++) HAL_SMBUSEx_DisableFastModePlus()
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal.h"
+
+/** @addtogroup STM32G0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SMBUSEx SMBUSEx
+  * @brief SMBUS Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup SMBUSEx_Exported_Functions_Group2 WakeUp Mode Functions
+  * @brief    WakeUp Mode Functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### WakeUp Mode Functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to:
+      (+) Configure Wake Up Feature
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enable SMBUS wakeup from Stop mode(s).
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUSx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUSEx_EnableWakeUp(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hsmbus->Instance));
+
+  if (hsmbus->State == HAL_SMBUS_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsmbus);
+
+    hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+    /* Disable the selected SMBUS peripheral */
+    __HAL_SMBUS_DISABLE(hsmbus);
+
+    /* Enable wakeup from stop mode */
+    hsmbus->Instance->CR1 |= I2C_CR1_WUPEN;
+
+    __HAL_SMBUS_ENABLE(hsmbus);
+
+    hsmbus->State = HAL_SMBUS_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Disable SMBUS wakeup from Stop mode(s).
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUSx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUSEx_DisableWakeUp(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hsmbus->Instance));
+
+  if (hsmbus->State == HAL_SMBUS_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsmbus);
+
+    hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+    /* Disable the selected SMBUS peripheral */
+    __HAL_SMBUS_DISABLE(hsmbus);
+
+    /* Disable wakeup from stop mode */
+    hsmbus->Instance->CR1 &= ~(I2C_CR1_WUPEN);
+
+    __HAL_SMBUS_ENABLE(hsmbus);
+
+    hsmbus->State = HAL_SMBUS_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup SMBUSEx_Exported_Functions_Group3 Fast Mode Plus Functions
+  * @brief    Fast Mode Plus Functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Fast Mode Plus Functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to:
+      (+) Configure Fast Mode Plus
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Enable the SMBUS fast mode plus driving capability.
+  * @param ConfigFastModePlus Selects the pin.
+  *   This parameter can be one of the @ref SMBUSEx_FastModePlus values
+  * @note  For I2C1, fast mode plus driving capability can be enabled on all selected
+  *        I2C1 pins using SMBUS_FASTMODEPLUS_I2C1 parameter or independently
+  *        on each one of the following pins PB6, PB7, PB8 and PB9.
+  * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+  *        can be enabled only by using SMBUS_FASTMODEPLUS_I2C1 parameter.
+  * @note  For all I2C2 pins fast mode plus driving capability can be enabled
+  *        only by using SMBUS_FASTMODEPLUS_I2C2 parameter.
+  * @note  For all I2C3 pins fast mode plus driving capability can be enabled
+  *        only by using SMBUS_FASTMODEPLUS_I2C3 parameter.
+  * @retval None
+  */
+void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  /* Check the parameter */
+  assert_param(IS_SMBUS_FASTMODEPLUS(ConfigFastModePlus));
+
+  /* Enable SYSCFG clock */
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+  /* Enable fast mode plus driving capability for selected pin */
+  SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
+}
+
+/**
+  * @brief Disable the SMBUS fast mode plus driving capability.
+  * @param ConfigFastModePlus Selects the pin.
+  *   This parameter can be one of the @ref SMBUSEx_FastModePlus values
+  * @note  For I2C1, fast mode plus driving capability can be disabled on all selected
+  *        I2C1 pins using SMBUS_FASTMODEPLUS_I2C1 parameter or independently
+  *        on each one of the following pins PB6, PB7, PB8 and PB9.
+  * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+  *        can be disabled only by using SMBUS_FASTMODEPLUS_I2C1 parameter.
+  * @note  For all I2C2 pins fast mode plus driving capability can be disabled
+  *        only by using SMBUS_FASTMODEPLUS_I2C2 parameter.
+  * @note  For all I2C3 pins fast mode plus driving capability can be disabled
+  *        only by using SMBUS_FASTMODEPLUS_I2C3 parameter.
+  * @retval None
+  */
+void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  /* Check the parameter */
+  assert_param(IS_SMBUS_FASTMODEPLUS(ConfigFastModePlus));
+
+  /* Enable SYSCFG clock */
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+  /* Disable fast mode plus driving capability for selected pin */
+  CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_spi_ex.c

@@ -0,0 +1,112 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_spi_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended SPI HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          SPI peripheral extended functionalities :
+  *           + IO operation functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal.h"
+
+/** @addtogroup STM32G0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SPIEx SPIEx
+  * @brief SPI Extended HAL module driver
+  * @{
+  */
+#ifdef HAL_SPI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup SPIEx_Private_Constants SPIEx Private Constants
+  * @{
+  */
+#define SPI_FIFO_SIZE       4UL
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions
+  * @{
+  */
+
+/** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions
+  *  @brief   Data transfers functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+ [..]
+    This subsection provides a set of extended functions to manage the SPI
+    data transfers.
+
+    (#) Rx data flush function:
+        (++) HAL_SPIEx_FlushRxFifo()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Flush the RX fifo.
+  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for the specified SPI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi)
+{
+  __IO uint32_t tmpreg;
+  uint8_t  count = 0U;
+  while ((hspi->Instance->SR & SPI_FLAG_FRLVL) !=  SPI_FRLVL_EMPTY)
+  {
+    count++;
+    tmpreg = hspi->Instance->DR;
+    UNUSED(tmpreg); /* To avoid GCC warning */
+    if (count == SPI_FIFO_SIZE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_usart_ex.c

@@ -0,0 +1,541 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_usart_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended USART HAL module driver.
+  *          This file provides firmware functions to manage the following extended
+  *          functionalities of the Universal Synchronous Receiver Transmitter Peripheral (USART).
+  *           + Peripheral Control functions
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+               ##### USART peripheral extended features  #####
+  ==============================================================================
+
+    (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
+
+        -@- When USART operates in FIFO mode, FIFO mode must be enabled prior
+            starting RX/TX transfers. Also RX/TX FIFO thresholds must be
+            configured prior starting RX/TX transfers.
+
+    (#) Slave mode enabling/disabling and NSS pin configuration.
+
+        -@- When USART operates in Slave mode, Slave mode must be enabled prior
+            starting RX/TX transfers.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal.h"
+
+/** @addtogroup STM32G0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup USARTEx USARTEx
+  * @brief USART Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_USART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/** @defgroup USARTEx_Private_Constants USARTEx Private Constants
+  * @{
+  */
+/* USART RX FIFO depth */
+#define RX_FIFO_DEPTH 8U
+
+/* USART TX FIFO depth */
+#define TX_FIFO_DEPTH 8U
+/**
+  * @}
+  */
+
+/* Private define ------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup USARTEx_Private_Functions USARTEx Private Functions
+  * @{
+  */
+static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup USARTEx_Exported_Functions  USARTEx Exported Functions
+  * @{
+  */
+
+/** @defgroup USARTEx_Exported_Functions_Group1 IO operation functions
+  * @brief Extended USART Transmit/Receive functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    This subsection provides a set of FIFO mode related callback functions.
+
+    (#) TX/RX Fifos Callbacks:
+        (+) HAL_USARTEx_RxFifoFullCallback()
+        (+) HAL_USARTEx_TxFifoEmptyCallback()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  USART RX Fifo full callback.
+  * @param  husart USART handle.
+  * @retval None
+  */
+__weak void HAL_USARTEx_RxFifoFullCallback(USART_HandleTypeDef *husart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_USARTEx_RxFifoFullCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  USART TX Fifo empty callback.
+  * @param  husart USART handle.
+  * @retval None
+  */
+__weak void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(husart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_USARTEx_TxFifoEmptyCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USARTEx_Exported_Functions_Group2 Peripheral Control functions
+  * @brief    Extended Peripheral Control functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..] This section provides the following functions:
+     (+) HAL_USARTEx_EnableSPISlaveMode() API enables the SPI slave mode
+     (+) HAL_USARTEx_DisableSPISlaveMode() API disables the SPI slave mode
+     (+) HAL_USARTEx_ConfigNSS API configures the Slave Select input pin (NSS)
+     (+) HAL_USARTEx_EnableFifoMode() API enables the FIFO mode
+     (+) HAL_USARTEx_DisableFifoMode() API disables the FIFO mode
+     (+) HAL_USARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
+     (+) HAL_USARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold
+
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enable the SPI slave mode.
+  * @note When the USART operates in SPI slave mode, it handles data flow using
+  *       the serial interface clock derived from the external SCLK signal
+  *       provided by the external master SPI device.
+  * @note In SPI slave mode, the USART must be enabled before starting the master
+  *       communications (or between frames while the clock is stable). Otherwise,
+  *       if the USART slave is enabled while the master is in the middle of a
+  *       frame, it will become desynchronized with the master.
+  * @note The data register of the slave needs to be ready before the first edge
+  *       of the communication clock or before the end of the ongoing communication,
+  *       otherwise the SPI slave will transmit zeros.
+  * @param husart      USART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart)
+{
+  uint32_t tmpcr1;
+
+  /* Check parameters */
+  assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance));
+
+  /* Process Locked */
+  __HAL_LOCK(husart);
+
+  husart->State = HAL_USART_STATE_BUSY;
+
+  /* Save actual USART configuration */
+  tmpcr1 = READ_REG(husart->Instance->CR1);
+
+  /* Disable USART */
+  __HAL_USART_DISABLE(husart);
+
+  /* In SPI slave mode mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bit in the USART_CR2 register
+  - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/
+  CLEAR_BIT(husart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(husart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
+  /* Enable SPI slave mode */
+  SET_BIT(husart->Instance->CR2, USART_CR2_SLVEN);
+
+  /* Restore USART configuration */
+  WRITE_REG(husart->Instance->CR1, tmpcr1);
+
+  husart->SlaveMode = USART_SLAVEMODE_ENABLE;
+
+  husart->State = HAL_USART_STATE_READY;
+
+  /* Enable USART */
+  __HAL_USART_ENABLE(husart);
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(husart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the SPI slave mode.
+  * @param husart      USART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart)
+{
+  uint32_t tmpcr1;
+
+  /* Check parameters */
+  assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance));
+
+  /* Process Locked */
+  __HAL_LOCK(husart);
+
+  husart->State = HAL_USART_STATE_BUSY;
+
+  /* Save actual USART configuration */
+  tmpcr1 = READ_REG(husart->Instance->CR1);
+
+  /* Disable USART */
+  __HAL_USART_DISABLE(husart);
+
+  /* Disable SPI slave mode */
+  CLEAR_BIT(husart->Instance->CR2, USART_CR2_SLVEN);
+
+  /* Restore USART configuration */
+  WRITE_REG(husart->Instance->CR1, tmpcr1);
+
+  husart->SlaveMode = USART_SLAVEMODE_DISABLE;
+
+  husart->State = HAL_USART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(husart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the Slave Select input pin (NSS).
+  * @note Software NSS management: SPI slave will always be selected and NSS
+  *       input pin will be ignored.
+  * @note Hardware NSS management: the SPI slave selection depends on NSS
+  *       input pin. The slave is selected when NSS is low and deselected when
+  *       NSS is high.
+  * @param husart      USART handle.
+  * @param NSSConfig   NSS configuration.
+  *          This parameter can be one of the following values:
+  *            @arg @ref USART_NSS_HARD
+  *            @arg @ref USART_NSS_SOFT
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig)
+{
+  uint32_t tmpcr1;
+
+  /* Check parameters */
+  assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance));
+  assert_param(IS_USART_NSS(NSSConfig));
+
+  /* Process Locked */
+  __HAL_LOCK(husart);
+
+  husart->State = HAL_USART_STATE_BUSY;
+
+  /* Save actual USART configuration */
+  tmpcr1 = READ_REG(husart->Instance->CR1);
+
+  /* Disable USART */
+  __HAL_USART_DISABLE(husart);
+
+  /* Program DIS_NSS bit in the USART_CR2 register */
+  MODIFY_REG(husart->Instance->CR2, USART_CR2_DIS_NSS, NSSConfig);
+
+  /* Restore USART configuration */
+  WRITE_REG(husart->Instance->CR1, tmpcr1);
+
+  husart->State = HAL_USART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(husart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the FIFO mode.
+  * @param husart      USART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart)
+{
+  uint32_t tmpcr1;
+
+  /* Check parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
+
+  /* Process Locked */
+  __HAL_LOCK(husart);
+
+  husart->State = HAL_USART_STATE_BUSY;
+
+  /* Save actual USART configuration */
+  tmpcr1 = READ_REG(husart->Instance->CR1);
+
+  /* Disable USART */
+  __HAL_USART_DISABLE(husart);
+
+  /* Enable FIFO mode */
+  SET_BIT(tmpcr1, USART_CR1_FIFOEN);
+  husart->FifoMode = USART_FIFOMODE_ENABLE;
+
+  /* Restore USART configuration */
+  WRITE_REG(husart->Instance->CR1, tmpcr1);
+
+  /* Determine the number of data to process during RX/TX ISR execution */
+  USARTEx_SetNbDataToProcess(husart);
+
+  husart->State = HAL_USART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(husart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the FIFO mode.
+  * @param husart      USART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart)
+{
+  uint32_t tmpcr1;
+
+  /* Check parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
+
+  /* Process Locked */
+  __HAL_LOCK(husart);
+
+  husart->State = HAL_USART_STATE_BUSY;
+
+  /* Save actual USART configuration */
+  tmpcr1 = READ_REG(husart->Instance->CR1);
+
+  /* Disable USART */
+  __HAL_USART_DISABLE(husart);
+
+  /* Enable FIFO mode */
+  CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
+  husart->FifoMode = USART_FIFOMODE_DISABLE;
+
+  /* Restore USART configuration */
+  WRITE_REG(husart->Instance->CR1, tmpcr1);
+
+  husart->State = HAL_USART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(husart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the TXFIFO threshold.
+  * @param husart      USART handle.
+  * @param Threshold  TX FIFO threshold value
+  *          This parameter can be one of the following values:
+  *            @arg @ref USART_TXFIFO_THRESHOLD_1_8
+  *            @arg @ref USART_TXFIFO_THRESHOLD_1_4
+  *            @arg @ref USART_TXFIFO_THRESHOLD_1_2
+  *            @arg @ref USART_TXFIFO_THRESHOLD_3_4
+  *            @arg @ref USART_TXFIFO_THRESHOLD_7_8
+  *            @arg @ref USART_TXFIFO_THRESHOLD_8_8
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold)
+{
+  uint32_t tmpcr1;
+
+  /* Check parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
+  assert_param(IS_USART_TXFIFO_THRESHOLD(Threshold));
+
+  /* Process Locked */
+  __HAL_LOCK(husart);
+
+  husart->State = HAL_USART_STATE_BUSY;
+
+  /* Save actual USART configuration */
+  tmpcr1 = READ_REG(husart->Instance->CR1);
+
+  /* Disable USART */
+  __HAL_USART_DISABLE(husart);
+
+  /* Update TX threshold configuration */
+  MODIFY_REG(husart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
+
+  /* Determine the number of data to process during RX/TX ISR execution */
+  USARTEx_SetNbDataToProcess(husart);
+
+  /* Restore USART configuration */
+  WRITE_REG(husart->Instance->CR1, tmpcr1);
+
+  husart->State = HAL_USART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(husart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the RXFIFO threshold.
+  * @param husart      USART handle.
+  * @param Threshold  RX FIFO threshold value
+  *          This parameter can be one of the following values:
+  *            @arg @ref USART_RXFIFO_THRESHOLD_1_8
+  *            @arg @ref USART_RXFIFO_THRESHOLD_1_4
+  *            @arg @ref USART_RXFIFO_THRESHOLD_1_2
+  *            @arg @ref USART_RXFIFO_THRESHOLD_3_4
+  *            @arg @ref USART_RXFIFO_THRESHOLD_7_8
+  *            @arg @ref USART_RXFIFO_THRESHOLD_8_8
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold)
+{
+  uint32_t tmpcr1;
+
+  /* Check the parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(husart->Instance));
+  assert_param(IS_USART_RXFIFO_THRESHOLD(Threshold));
+
+  /* Process Locked */
+  __HAL_LOCK(husart);
+
+  husart->State = HAL_USART_STATE_BUSY;
+
+  /* Save actual USART configuration */
+  tmpcr1 = READ_REG(husart->Instance->CR1);
+
+  /* Disable USART */
+  __HAL_USART_DISABLE(husart);
+
+  /* Update RX threshold configuration */
+  MODIFY_REG(husart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
+
+  /* Determine the number of data to process during RX/TX ISR execution */
+  USARTEx_SetNbDataToProcess(husart);
+
+  /* Restore USART configuration */
+  WRITE_REG(husart->Instance->CR1, tmpcr1);
+
+  husart->State = HAL_USART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(husart);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup USARTEx_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief Calculate the number of data to process in RX/TX ISR.
+  * @note The RX FIFO depth and the TX FIFO depth is extracted from
+  *       the USART configuration registers.
+  * @param husart USART handle.
+  * @retval None
+  */
+static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart)
+{
+  uint8_t rx_fifo_depth;
+  uint8_t tx_fifo_depth;
+  uint8_t rx_fifo_threshold;
+  uint8_t tx_fifo_threshold;
+  /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */
+  static const uint8_t numerator[]   = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
+  static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
+
+  if (husart->FifoMode == USART_FIFOMODE_DISABLE)
+  {
+    husart->NbTxDataToProcess = 1U;
+    husart->NbRxDataToProcess = 1U;
+  }
+  else
+  {
+    rx_fifo_depth = RX_FIFO_DEPTH;
+    tx_fifo_depth = TX_FIFO_DEPTH;
+    rx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3,
+                                            USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos) & 0xFFU);
+    tx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3,
+                                            USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos) & 0xFFU);
+    husart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
+                                (uint16_t)denominator[tx_fifo_threshold];
+    husart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
+                                (uint16_t)denominator[rx_fifo_threshold];
+  }
+}
+/**
+  * @}
+  */
+
+#endif /* HAL_USART_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_wwdg.c

@@ -0,0 +1,420 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_hal_wwdg.c
+  * @author  MCD Application Team
+  * @brief   WWDG HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Window Watchdog (WWDG) peripheral:
+  *           + Initialization and Configuration functions
+  *           + IO operation functions
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                      ##### WWDG Specific features #####
+  ==============================================================================
+  [..]
+    Once enabled the WWDG generates a system reset on expiry of a programmed
+    time period, unless the program refreshes the counter (T[6;0] downcounter)
+    before reaching 0x3F value (i.e. a reset is generated when the counter
+    value rolls down from 0x40 to 0x3F).
+
+    (+) An MCU reset is also generated if the counter value is refreshed
+        before the counter has reached the refresh window value. This
+        implies that the counter must be refreshed in a limited window.
+    (+) Once enabled the WWDG cannot be disabled except by a system reset.
+    (+) If required by application, an Early Wakeup Interrupt can be triggered
+        in order to be warned before WWDG expiration. The Early Wakeup Interrupt
+        (EWI) can be used if specific safety operations or data logging must
+        be performed before the actual reset is generated. When the downcounter
+        reaches 0x40, interrupt occurs. This mechanism requires WWDG interrupt
+        line to be enabled in NVIC. Once enabled, EWI interrupt cannot be
+        disabled except by a system reset.
+    (+) WWDGRST flag in RCC CSR register can be used to inform when a WWDG
+        reset occurs.
+    (+) The WWDG counter input clock is derived from the APB clock divided
+        by a programmable prescaler.
+    (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)
+    (+) WWDG timeout (mS) = 1000 * (T[5;0] + 1) / WWDG clock (Hz)
+        where T[5;0] are the lowest 6 bits of Counter.
+    (+) WWDG Counter refresh is allowed between the following limits :
+        (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
+        (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
+    (+) Typical values:
+        (++) Counter min (T[5;0] = 0x00) at 64 MHz (PCLK1) with zero prescaler:
+             max timeout before reset: approximately 64us
+        (++) Counter max (T[5;0] = 0x3F) at 64 MHz (PCLK1) with prescaler
+             dividing by 128:
+             max timeout before reset: approximately 524.28ms
+
+                     ##### How to use this driver #####
+  ==============================================================================
+
+    *** Common driver usage ***
+    ===========================
+
+  [..]
+    (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
+    (+) Configure the WWDG prescaler, refresh window value, counter value and early
+        interrupt status using HAL_WWDG_Init() function. This will automatically
+        enable WWDG and start its downcounter. Time reference can be taken from
+        function exit. Care must be taken to provide a counter value
+        greater than 0x40 to prevent generation of immediate reset.
+    (+) If the Early Wakeup Interrupt (EWI) feature is enabled, an interrupt is
+        generated when the counter reaches 0x40. When HAL_WWDG_IRQHandler is
+        triggered by the interrupt service routine, flag will be automatically
+        cleared and HAL_WWDG_WakeupCallback user callback will be executed. User
+        can add his own code by customization of callback HAL_WWDG_WakeupCallback.
+    (+) Then the application program must refresh the WWDG counter at regular
+        intervals during normal operation to prevent an MCU reset, using
+        HAL_WWDG_Refresh() function. This operation must occur only when
+        the counter is lower than the refresh window value already programmed.
+
+    *** Callback registration ***
+    =============================
+
+  [..]
+    The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
+    the user to configure dynamically the driver callbacks. Use Functions
+    HAL_WWDG_RegisterCallback() to register a user callback.
+
+    (+) Function HAL_WWDG_RegisterCallback() allows to register following
+        callbacks:
+        (++) EwiCallback : callback for Early WakeUp Interrupt.
+        (++) MspInitCallback : WWDG MspInit.
+    This function takes as parameters the HAL peripheral handle, the Callback ID
+    and a pointer to the user callback function.
+
+    (+) Use function HAL_WWDG_UnRegisterCallback() to reset a callback to
+    the default weak (surcharged) function. HAL_WWDG_UnRegisterCallback()
+    takes as parameters the HAL peripheral handle and the Callback ID.
+    This function allows to reset following callbacks:
+        (++) EwiCallback : callback for  Early WakeUp Interrupt.
+        (++) MspInitCallback : WWDG MspInit.
+
+    [..]
+    When calling HAL_WWDG_Init function, callbacks are reset to the
+    corresponding legacy weak (surcharged) functions:
+    HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have
+    not been registered before.
+
+    [..]
+    When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or
+    not defined, the callback registering feature is not available
+    and weak (surcharged) callbacks are used.
+
+    *** WWDG HAL driver macros list ***
+    ===================================
+    [..]
+      Below the list of available macros in WWDG HAL driver.
+      (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
+      (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
+      (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
+      (+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_hal.h"
+
+/** @addtogroup STM32G0xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+/** @defgroup WWDG WWDG
+  * @brief WWDG HAL module driver.
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Functions WWDG Exported Functions
+  * @{
+  */
+
+/** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions
+  *  @brief    Initialization and Configuration functions.
+  *
+@verbatim
+  ==============================================================================
+          ##### Initialization and Configuration functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+      (+) Initialize and start the WWDG according to the specified parameters
+          in the WWDG_InitTypeDef of associated handle.
+      (+) Initialize the WWDG MSP.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the WWDG according to the specified.
+  *         parameters in the WWDG_InitTypeDef of  associated handle.
+  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified WWDG module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
+{
+  /* Check the WWDG handle allocation */
+  if (hwwdg == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
+  assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
+  assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));
+  assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
+  assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode));
+
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+  /* Reset Callback pointers */
+  if (hwwdg->EwiCallback == NULL)
+  {
+    hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
+  }
+
+  if (hwwdg->MspInitCallback == NULL)
+  {
+    hwwdg->MspInitCallback = HAL_WWDG_MspInit;
+  }
+
+  /* Init the low level hardware */
+  hwwdg->MspInitCallback(hwwdg);
+#else
+  /* Init the low level hardware */
+  HAL_WWDG_MspInit(hwwdg);
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
+
+  /* Set WWDG Counter */
+  WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
+
+  /* Set WWDG Prescaler and Window */
+  WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window));
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Initialize the WWDG MSP.
+  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified WWDG module.
+  * @note   When rewriting this function in user file, mechanism may be added
+  *         to avoid multiple initialize when HAL_WWDG_Init function is called
+  *         again to change parameters.
+  * @retval None
+  */
+__weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hwwdg);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_WWDG_MspInit could be implemented in the user file
+   */
+}
+
+
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User WWDG Callback
+  *         To be used instead of the weak (surcharged) predefined callback
+  * @param  hwwdg WWDG handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
+  *           @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID,
+                                            pWWDG_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    switch (CallbackID)
+    {
+      case HAL_WWDG_EWI_CB_ID:
+        hwwdg->EwiCallback = pCallback;
+        break;
+
+      case HAL_WWDG_MSPINIT_CB_ID:
+        hwwdg->MspInitCallback = pCallback;
+        break;
+
+      default:
+        status = HAL_ERROR;
+        break;
+    }
+  }
+
+  return status;
+}
+
+
+/**
+  * @brief  Unregister a WWDG Callback
+  *         WWDG Callback is redirected to the weak (surcharged) predefined callback
+  * @param  hwwdg WWDG handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
+  *           @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  switch (CallbackID)
+  {
+    case HAL_WWDG_EWI_CB_ID:
+      hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
+      break;
+
+    case HAL_WWDG_MSPINIT_CB_ID:
+      hwwdg->MspInitCallback = HAL_WWDG_MspInit;
+      break;
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  return status;
+}
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
+  *  @brief    IO operation functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### IO operation functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Refresh the WWDG.
+    (+) Handle WWDG interrupt request and associated function callback.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Refresh the WWDG.
+  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified WWDG module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg)
+{
+  /* Write to WWDG CR the WWDG Counter value to refresh with */
+  WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter));
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle WWDG interrupt request.
+  * @note   The Early Wakeup Interrupt (EWI) can be used if specific safety operations
+  *         or data logging must be performed before the actual reset is generated.
+  *         The EWI interrupt is enabled by calling HAL_WWDG_Init function with
+  *         EWIMode set to WWDG_EWI_ENABLE.
+  *         When the downcounter reaches the value 0x40, and EWI interrupt is
+  *         generated and the corresponding Interrupt Service Routine (ISR) can
+  *         be used to trigger specific actions (such as communications or data
+  *         logging), before resetting the device.
+  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified WWDG module.
+  * @retval None
+  */
+void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
+{
+  /* Check if Early Wakeup Interrupt is enable */
+  if (__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
+  {
+    /* Check if WWDG Early Wakeup Interrupt occurred */
+    if (__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
+    {
+      /* Clear the WWDG Early Wakeup flag */
+      __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
+
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+      /* Early Wakeup registered callback */
+      hwwdg->EwiCallback(hwwdg);
+#else
+      /* Early Wakeup callback */
+      HAL_WWDG_EarlyWakeupCallback(hwwdg);
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
+    }
+  }
+}
+
+
+/**
+  * @brief  WWDG Early Wakeup callback.
+  * @param  hwwdg  pointer to a WWDG_HandleTypeDef structure that contains
+  *                the configuration information for the specified WWDG module.
+  * @retval None
+  */
+__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hwwdg);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_WWDG_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_adc.c

@@ -0,0 +1,787 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_ll_adc.c
+  * @author  MCD Application Team
+  * @brief   ADC LL module driver
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_ll_adc.h"
+#include "stm32g0xx_ll_bus.h"
+
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32G0xx_LL_Driver
+  * @{
+  */
+
+#if defined (ADC1)
+
+/** @addtogroup ADC_LL ADC
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup ADC_LL_Private_Constants
+  * @{
+  */
+
+/* Definitions of ADC hardware constraints delays */
+/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver,   */
+/*       not timeout values:                                                  */
+/*       Timeout values for ADC operations are dependent to device clock      */
+/*       configuration (system clock versus ADC clock),                       */
+/*       and therefore must be defined in user application.                   */
+/*       Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout     */
+/*       values definition.                                                   */
+/* Note: ADC timeout values are defined here in CPU cycles to be independent  */
+/*       of device clock setting.                                             */
+/*       In user application, ADC timeout values should be defined with       */
+/*       temporal values, in function of device clock settings.               */
+/*       Highest ratio CPU clock frequency vs ADC clock frequency:            */
+/*        - ADC clock from synchronous clock with AHB prescaler 512,          */
+/*          APB prescaler 16, ADC prescaler 4.                                */
+/*        - ADC clock from asynchronous clock (HSI) with prescaler 1,         */
+/*          with highest ratio CPU clock frequency vs HSI clock frequency:    */
+/*          CPU clock frequency max 56MHz, HSI frequency 16MHz: ratio 4.      */
+/* Unit: CPU cycles.                                                          */
+#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST          (512UL * 16UL * 4UL)
+#define ADC_TIMEOUT_DISABLE_CPU_CYCLES          (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
+#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES  (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
+/* Note: CCRDY handshake requires 1APB + 2 ADC + 3 APB cycles                 */
+/*       after the channel configuration has been changed.                    */
+/*       Driver timeout is approximated to 6 CPU cycles.                      */
+#define ADC_TIMEOUT_CCRDY_CPU_CYCLES            (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 6UL)
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup ADC_LL_Private_Macros
+  * @{
+  */
+
+/* Check of parameters for configuration of ADC hierarchical scope:           */
+/* common to several ADC instances.                                           */
+#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__)                                      \
+  (((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1)                                    \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2)                                 \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4)                                 \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6)                                 \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8)                                 \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10)                                \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12)                                \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16)                                \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32)                                \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64)                                \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128)                               \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256)                               \
+  )
+
+#define IS_LL_ADC_CLOCK_FREQ_MODE(__CLOCK_FREQ_MODE__)                         \
+  (((__CLOCK_FREQ_MODE__) == LL_ADC_CLOCK_FREQ_MODE_HIGH)                      \
+   || ((__CLOCK_FREQ_MODE__) == LL_ADC_CLOCK_FREQ_MODE_LOW)                    \
+  )
+
+/* Check of parameters for configuration of ADC hierarchical scope:           */
+/* ADC instance.                                                              */
+#define IS_LL_ADC_CLOCK(__CLOCK__)                                             \
+  (((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4)                                \
+   || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2)                             \
+   || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1)                             \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC)                                      \
+  )
+
+#define IS_LL_ADC_RESOLUTION(__RESOLUTION__)                                   \
+  (((__RESOLUTION__) == LL_ADC_RESOLUTION_12B)                                 \
+   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B)                              \
+   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B)                               \
+   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B)                               \
+  )
+
+#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__)                                   \
+  (((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT)                               \
+   || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT)                             \
+  )
+
+#define IS_LL_ADC_LOW_POWER(__LOW_POWER__)                                     \
+  (((__LOW_POWER__) == LL_ADC_LP_MODE_NONE)                                    \
+   || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT)                                  \
+   || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF)                              \
+   || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF)                     \
+  )
+
+/* Check of parameters for configuration of ADC hierarchical scope:           */
+/* ADC group regular                                                          */
+#if defined(TIM15) && defined(TIM6) && defined(TIM2)
+#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__)                         \
+  (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                         \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4 )                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)               \
+  )
+#elif defined(TIM15) && defined(TIM6)
+#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__)                         \
+  (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                         \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4 )                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)               \
+  )
+#elif defined(TIM2)
+#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__)                         \
+  (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                         \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4 )                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)               \
+  )
+#else
+#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__)                         \
+  (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                         \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4 )                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)               \
+  )
+#endif /* TIM15 && TIM6 && TIM2 */
+
+#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__)                 \
+  (((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE)                       \
+   || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS)                \
+  )
+
+#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__)                       \
+  (((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE)                    \
+   || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED)              \
+   || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED)            \
+  )
+
+#define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__)             \
+  (((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED)              \
+   || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN)         \
+  )
+
+#define IS_LL_ADC_REG_SEQ_MODE(__REG_SEQ_MODE__)                               \
+  (((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_FIXED)                                \
+   || ((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_CONFIGURABLE)                      \
+  )
+
+#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__)                 \
+  (((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE)                  \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS)         \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS)         \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS)         \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS)         \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS)         \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS)         \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS)         \
+  )
+
+#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__)          \
+  (((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE)              \
+   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK)             \
+  )
+
+/**
+  * @}
+  */
+
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup ADC_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize registers of all ADC instances belonging to
+  *         the same ADC common instance to their default reset values.
+  * @note   This function is performing a hard reset, using high level
+  *         clock source RCC ADC reset.
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ADC common registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
+
+  /* Prevent unused argument(s) compilation warning if no assert_param check */
+  (void)(ADCxy_COMMON);
+
+  /* Force reset of ADC clock (core clock) */
+  LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC);
+
+  /* Release reset of ADC clock (core clock) */
+  LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Initialize some features of ADC common parameters
+  *         (all ADC instances belonging to the same ADC common instance)
+  *         and multimode (for devices with several ADC instances available).
+  * @note   The setting of ADC common parameters is conditioned to
+  *         ADC instances state:
+  *         All ADC instances belonging to the same ADC common instance
+  *         must be disabled.
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ADC common registers are initialized
+  *          - ERROR: ADC common registers are not initialized
+  */
+ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
+  assert_param(IS_LL_ADC_COMMON_CLOCK(pADC_CommonInitStruct->CommonClock));
+
+  /* Note: Hardware constraint (refer to description of functions             */
+  /*       "LL_ADC_SetCommonXXX()":                                           */
+  /*       On this STM32 series, setting of these features is conditioned to  */
+  /*       ADC state:                                                         */
+  /*       All ADC instances of the ADC common group must be disabled.        */
+  if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)
+  {
+    /* Configuration of ADC hierarchical scope:                               */
+    /*  - common to several ADC                                               */
+    /*    (all ADC instances belonging to the same ADC common instance)       */
+    /*    - Set ADC clock (conversion clock)                                  */
+    LL_ADC_SetCommonClock(ADCxy_COMMON, pADC_CommonInitStruct->CommonClock);
+  }
+  else
+  {
+    /* Initialization error: One or several ADC instances belonging to        */
+    /* the same ADC common instance are not disabled.                         */
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_ADC_CommonInitTypeDef field to default value.
+  * @param  pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
+  *                              whose fields will be set to default values.
+  * @retval None
+  */
+void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
+{
+  /* Set pADC_CommonInitStruct fields to default values */
+  /* Set fields of ADC common */
+  /* (all ADC instances belonging to the same ADC common instance) */
+  pADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2;
+
+}
+
+/**
+  * @brief  De-initialize registers of the selected ADC instance
+  *         to their default reset values.
+  * @note   To reset all ADC instances quickly (perform a hard reset),
+  *         use function @ref LL_ADC_CommonDeInit().
+  * @note   If this functions returns error status, it means that ADC instance
+  *         is in an unknown state.
+  *         In this case, perform a hard reset using high level
+  *         clock source RCC ADC reset.
+  *         Refer to function @ref LL_ADC_CommonDeInit().
+  * @param  ADCx ADC instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ADC registers are de-initialized
+  *          - ERROR: ADC registers are not de-initialized
+  */
+ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
+{
+  ErrorStatus status = SUCCESS;
+
+  __IO uint32_t timeout_cpu_cycles = 0UL;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+
+  /* Disable ADC instance if not already disabled.                            */
+  if (LL_ADC_IsEnabled(ADCx) == 1UL)
+  {
+    /* Set ADC group regular trigger source to SW start to ensure to not      */
+    /* have an external trigger event occurring during the conversion stop    */
+    /* ADC disable process.                                                   */
+    LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
+
+    /* Stop potential ADC conversion on going on ADC group regular.           */
+    if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL)
+    {
+      if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL)
+      {
+        LL_ADC_REG_StopConversion(ADCx);
+      }
+    }
+
+    /* Wait for ADC conversions are effectively stopped                       */
+    timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
+    while (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 1UL)
+    {
+      timeout_cpu_cycles--;
+      if (timeout_cpu_cycles == 0UL)
+      {
+        /* Time-out error */
+        status = ERROR;
+        break;
+      }
+    }
+
+    /* Disable the ADC instance */
+    LL_ADC_Disable(ADCx);
+
+    /* Wait for ADC instance is effectively disabled */
+    timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
+    while (LL_ADC_IsDisableOngoing(ADCx) == 1UL)
+    {
+      timeout_cpu_cycles--;
+      if (timeout_cpu_cycles == 0UL)
+      {
+        /* Time-out error */
+        status = ERROR;
+        break;
+      }
+    }
+  }
+
+  /* Check whether ADC state is compliant with expected state */
+  if (READ_BIT(ADCx->CR,
+               (ADC_CR_ADSTP | ADC_CR_ADSTART
+                | ADC_CR_ADDIS | ADC_CR_ADEN)
+              )
+      == 0UL)
+  {
+    /* ========== Reset ADC registers ========== */
+    /* Reset register IER */
+    CLEAR_BIT(ADCx->IER,
+              (LL_ADC_IT_ADRDY
+               | LL_ADC_IT_EOC
+               | LL_ADC_IT_EOS
+               | LL_ADC_IT_OVR
+               | LL_ADC_IT_EOSMP
+               | LL_ADC_IT_AWD1
+               | LL_ADC_IT_AWD2
+               | LL_ADC_IT_AWD3
+               | LL_ADC_IT_EOCAL
+               | LL_ADC_IT_CCRDY
+              )
+             );
+
+    /* Reset register ISR */
+    SET_BIT(ADCx->ISR,
+            (LL_ADC_FLAG_ADRDY
+             | LL_ADC_FLAG_EOC
+             | LL_ADC_FLAG_EOS
+             | LL_ADC_FLAG_OVR
+             | LL_ADC_FLAG_EOSMP
+             | LL_ADC_FLAG_AWD1
+             | LL_ADC_FLAG_AWD2
+             | LL_ADC_FLAG_AWD3
+             | LL_ADC_FLAG_EOCAL
+             | LL_ADC_FLAG_CCRDY
+            )
+           );
+
+    /* Reset register CR */
+    /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode     */
+    /* "read-set": no direct reset applicable.                                */
+    CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN);
+
+    /* Reset register CFGR1 */
+    CLEAR_BIT(ADCx->CFGR1,
+              (ADC_CFGR1_AWD1CH  | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN
+               | ADC_CFGR1_AUTOFF  | ADC_CFGR1_WAIT   | ADC_CFGR1_CONT    | ADC_CFGR1_OVRMOD
+               | ADC_CFGR1_EXTEN   | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN   | ADC_CFGR1_RES
+               | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN)
+             );
+
+    /* Reset register CFGR2 */
+    /* Note: Update of ADC clock mode is conditioned to ADC state disabled:   */
+    /*       already done above.                                              */
+    CLEAR_BIT(ADCx->CFGR2,
+              (ADC_CFGR2_CKMODE
+               | ADC_CFGR2_TOVS   | ADC_CFGR2_OVSS  | ADC_CFGR2_OVSR
+               | ADC_CFGR2_OVSE)
+             );
+
+    /* Reset register SMPR */
+    CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP1 | ADC_SMPR_SMP2 | ADC_SMPR_SMPSEL);
+
+    /* Reset register AWD1TR */
+    MODIFY_REG(ADCx->AWD1TR, ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1, ADC_AWD1TR_HT1);
+
+    /* Reset register AWD2TR */
+    MODIFY_REG(ADCx->AWD2TR, ADC_AWD2TR_HT2 | ADC_AWD2TR_LT2, ADC_AWD2TR_HT2);
+
+    /* Reset register AWD3TR */
+    MODIFY_REG(ADCx->AWD3TR, ADC_AWD3TR_HT3 | ADC_AWD3TR_LT3, ADC_AWD3TR_HT3);
+
+    /* Reset register CHSELR */
+    CLEAR_BIT(ADCx->CHSELR,
+              (ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16
+               | ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12
+               | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9  | ADC_CHSELR_CHSEL8
+               | ADC_CHSELR_CHSEL7  | ADC_CHSELR_CHSEL6  | ADC_CHSELR_CHSEL5  | ADC_CHSELR_CHSEL4
+               | ADC_CHSELR_CHSEL3  | ADC_CHSELR_CHSEL2  | ADC_CHSELR_CHSEL1  | ADC_CHSELR_CHSEL0)
+             );
+
+    /* Wait for ADC channel configuration ready */
+    timeout_cpu_cycles = ADC_TIMEOUT_CCRDY_CPU_CYCLES;
+    while (LL_ADC_IsActiveFlag_CCRDY(ADCx) == 0UL)
+    {
+      timeout_cpu_cycles--;
+      if (timeout_cpu_cycles == 0UL)
+      {
+        /* Time-out error */
+        status = ERROR;
+        break;
+      }
+    }
+
+    /* Clear flag ADC channel configuration ready */
+    LL_ADC_ClearFlag_CCRDY(ADCx);
+
+    /* Reset register DR */
+    /* bits in access mode read only, no direct reset applicable */
+
+    /* Reset register CALFACT */
+    CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT);
+
+  }
+  else
+  {
+    /* ADC instance is in an unknown state */
+    /* Need to performing a hard reset of ADC instance, using high level      */
+    /* clock source RCC ADC reset.                                            */
+    /* Caution: On this STM32 series, if several ADC instances are available  */
+    /*          on the selected device, RCC ADC reset will reset              */
+    /*          all ADC instances belonging to the common ADC instance.       */
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Initialize some features of ADC instance.
+  * @note   These parameters have an impact on ADC scope: ADC instance.
+  *         Refer to corresponding unitary functions into
+  *         @ref ADC_LL_EF_Configuration_ADC_Instance .
+  * @note   The setting of these parameters by function @ref LL_ADC_Init()
+  *         is conditioned to ADC state:
+  *         ADC instance must be disabled.
+  *         This condition is applied to all ADC features, for efficiency
+  *         and compatibility over all STM32 families. However, the different
+  *         features can be set under different ADC state conditions
+  *         (setting possible with ADC enabled without conversion on going,
+  *         ADC enabled with conversion on going, ...)
+  *         Each feature can be updated afterwards with a unitary function
+  *         and potentially with ADC in a different state than disabled,
+  *         refer to description of each function for setting
+  *         conditioned to ADC state.
+  * @note   After using this function, some other features must be configured
+  *         using LL unitary functions.
+  *         The minimum configuration remaining to be done is:
+  *          - Set ADC group regular sequencer:
+  *            Depending on the sequencer mode (refer to
+  *            function @ref LL_ADC_REG_SetSequencerConfigurable() ):
+  *            - map channel on the selected sequencer rank.
+  *              Refer to function @ref LL_ADC_REG_SetSequencerRanks();
+  *            - map channel on rank corresponding to channel number.
+  *              Refer to function @ref LL_ADC_REG_SetSequencerChannels();
+  *          - Set ADC channel sampling time
+  *            Refer to function LL_ADC_SetSamplingTimeCommonChannels();
+  *            Refer to function LL_ADC_SetChannelSamplingTime();
+  * @param  ADCx ADC instance
+  * @param  pADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ADC registers are initialized
+  *          - ERROR: ADC registers are not initialized
+  */
+ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *pADC_InitStruct)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+
+  assert_param(IS_LL_ADC_CLOCK(pADC_InitStruct->Clock));
+  assert_param(IS_LL_ADC_RESOLUTION(pADC_InitStruct->Resolution));
+  assert_param(IS_LL_ADC_DATA_ALIGN(pADC_InitStruct->DataAlignment));
+  assert_param(IS_LL_ADC_LOW_POWER(pADC_InitStruct->LowPowerMode));
+
+  /* Note: Hardware constraint (refer to description of this function):       */
+  /*       ADC instance must be disabled.                                     */
+  if (LL_ADC_IsEnabled(ADCx) == 0UL)
+  {
+    /* Configuration of ADC hierarchical scope:                               */
+    /*  - ADC instance                                                        */
+    /*    - Set ADC data resolution                                           */
+    /*    - Set ADC conversion data alignment                                 */
+    /*    - Set ADC low power mode                                            */
+    MODIFY_REG(ADCx->CFGR1,
+               ADC_CFGR1_RES
+               | ADC_CFGR1_ALIGN
+               | ADC_CFGR1_WAIT
+               | ADC_CFGR1_AUTOFF
+               ,
+               pADC_InitStruct->Resolution
+               | pADC_InitStruct->DataAlignment
+               | pADC_InitStruct->LowPowerMode
+              );
+
+    MODIFY_REG(ADCx->CFGR2,
+               ADC_CFGR2_CKMODE
+               ,
+               pADC_InitStruct->Clock
+              );
+  }
+  else
+  {
+    /* Initialization error: ADC instance is not disabled. */
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_ADC_InitTypeDef field to default value.
+  * @param  pADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
+  *                        whose fields will be set to default values.
+  * @retval None
+  */
+void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct)
+{
+  /* Set pADC_InitStruct fields to default values */
+  /* Set fields of ADC instance */
+  pADC_InitStruct->Clock         = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
+  pADC_InitStruct->Resolution    = LL_ADC_RESOLUTION_12B;
+  pADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
+  pADC_InitStruct->LowPowerMode  = LL_ADC_LP_MODE_NONE;
+
+}
+
+/**
+  * @brief  Initialize some features of ADC group regular.
+  * @note   These parameters have an impact on ADC scope: ADC group regular.
+  *         Refer to corresponding unitary functions into
+  *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+  *         (functions with prefix "REG").
+  * @note   The setting of these parameters by function @ref LL_ADC_Init()
+  *         is conditioned to ADC state:
+  *         ADC instance must be disabled.
+  *         This condition is applied to all ADC features, for efficiency
+  *         and compatibility over all STM32 families. However, the different
+  *         features can be set under different ADC state conditions
+  *         (setting possible with ADC enabled without conversion on going,
+  *         ADC enabled with conversion on going, ...)
+  *         Each feature can be updated afterwards with a unitary function
+  *         and potentially with ADC in a different state than disabled,
+  *         refer to description of each function for setting
+  *         conditioned to ADC state.
+  * @note   Before using this function, ADC group regular sequencer
+  *         must be configured: refer to function
+  *         @ref LL_ADC_REG_SetSequencerConfigurable().
+  * @note   After using this function, other features must be configured
+  *         using LL unitary functions.
+  *         The minimum configuration remaining to be done is:
+  *          - Set ADC group regular sequencer:
+  *            Depending on the sequencer mode (refer to
+  *            function @ref LL_ADC_REG_SetSequencerConfigurable() ):
+  *            - map channel on the selected sequencer rank.
+  *              Refer to function @ref LL_ADC_REG_SetSequencerRanks();
+  *            - map channel on rank corresponding to channel number.
+  *              Refer to function @ref LL_ADC_REG_SetSequencerChannels();
+  *          - Set ADC channel sampling time
+  *            Refer to function LL_ADC_SetSamplingTimeCommonChannels();
+  *            Refer to function LL_ADC_SetChannelSamplingTime();
+  * @param  ADCx ADC instance
+  * @param  pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ADC registers are initialized
+  *          - ERROR: ADC registers are not initialized
+  */
+ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+  assert_param(IS_LL_ADC_REG_TRIG_SOURCE(pADC_RegInitStruct->TriggerSource));
+  assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(pADC_RegInitStruct->ContinuousMode));
+  assert_param(IS_LL_ADC_REG_DMA_TRANSFER(pADC_RegInitStruct->DMATransfer));
+  assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(pADC_RegInitStruct->Overrun));
+
+  if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED)
+  {
+    assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(pADC_RegInitStruct->SequencerLength));
+  }
+
+  if ((LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED)
+      || (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+     )
+  {
+    assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(pADC_RegInitStruct->SequencerDiscont));
+
+    /* ADC group regular continuous mode and discontinuous mode                 */
+    /* can not be enabled simultenaeously                                       */
+    assert_param((pADC_RegInitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
+                 || (pADC_RegInitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
+  }
+
+  /* Note: Hardware constraint (refer to description of this function):       */
+  /*       ADC instance must be disabled.                                     */
+  if (LL_ADC_IsEnabled(ADCx) == 0UL)
+  {
+    /* Configuration of ADC hierarchical scope:                               */
+    /*  - ADC group regular                                                   */
+    /*    - Set ADC group regular trigger source                              */
+    /*    - Set ADC group regular sequencer length                            */
+    /*    - Set ADC group regular sequencer discontinuous mode                */
+    /*    - Set ADC group regular continuous mode                             */
+    /*    - Set ADC group regular conversion data transfer: no transfer or    */
+    /*      transfer by DMA, and DMA requests mode                            */
+    /*    - Set ADC group regular overrun behavior                            */
+    /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by    */
+    /*       setting of trigger source to SW start.                           */
+    if ((LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED)
+        || (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+       )
+    {
+      /* Case of sequencer mode fixed
+         or sequencer length >= 2 ranks with sequencer mode fully configurable:
+         discontinuous mode configured */
+      MODIFY_REG(ADCx->CFGR1,
+                 ADC_CFGR1_EXTSEL
+                 | ADC_CFGR1_EXTEN
+                 | ADC_CFGR1_DISCEN
+                 | ADC_CFGR1_CONT
+                 | ADC_CFGR1_DMAEN
+                 | ADC_CFGR1_DMACFG
+                 | ADC_CFGR1_OVRMOD
+                 ,
+                 pADC_RegInitStruct->TriggerSource
+                 | pADC_RegInitStruct->SequencerDiscont
+                 | pADC_RegInitStruct->ContinuousMode
+                 | pADC_RegInitStruct->DMATransfer
+                 | pADC_RegInitStruct->Overrun
+                );
+    }
+    else
+    {
+      /* Case of sequencer mode fully configurable
+         and sequencer length 1 rank (sequencer disabled):
+         discontinuous mode discarded (fixed to disable) */
+      MODIFY_REG(ADCx->CFGR1,
+                 ADC_CFGR1_EXTSEL
+                 | ADC_CFGR1_EXTEN
+                 | ADC_CFGR1_DISCEN
+                 | ADC_CFGR1_CONT
+                 | ADC_CFGR1_DMAEN
+                 | ADC_CFGR1_DMACFG
+                 | ADC_CFGR1_OVRMOD
+                 ,
+                 pADC_RegInitStruct->TriggerSource
+                 | LL_ADC_REG_SEQ_DISCONT_DISABLE
+                 | pADC_RegInitStruct->ContinuousMode
+                 | pADC_RegInitStruct->DMATransfer
+                 | pADC_RegInitStruct->Overrun
+                );
+    }
+
+    /* Set ADC group regular sequencer length */
+    if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED)
+    {
+      LL_ADC_REG_SetSequencerLength(ADCx, pADC_RegInitStruct->SequencerLength);
+    }
+  }
+  else
+  {
+    /* Initialization error: ADC instance is not disabled. */
+    status = ERROR;
+  }
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_ADC_REG_InitTypeDef field to default value.
+  * @param  pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+  *                            whose fields will be set to default values.
+  * @retval None
+  */
+void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
+{
+  /* Set pADC_RegInitStruct fields to default values */
+  /* Set fields of ADC group regular */
+  /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by      */
+  /*       setting of trigger source to SW start.                             */
+  pADC_RegInitStruct->TriggerSource    = LL_ADC_REG_TRIG_SOFTWARE;
+  pADC_RegInitStruct->SequencerLength  = LL_ADC_REG_SEQ_SCAN_DISABLE;
+  pADC_RegInitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
+  pADC_RegInitStruct->ContinuousMode   = LL_ADC_REG_CONV_SINGLE;
+  pADC_RegInitStruct->DMATransfer      = LL_ADC_REG_DMA_TRANSFER_NONE;
+  pADC_RegInitStruct->Overrun          = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* ADC1 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_comp.c

@@ -0,0 +1,252 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_ll_comp.c
+  * @author  MCD Application Team
+  * @brief   COMP LL module driver
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_ll_comp.h"
+
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32G0xx_LL_Driver
+  * @{
+  */
+
+#if defined (COMP1) || defined (COMP2)
+
+/** @addtogroup COMP_LL COMP
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup COMP_LL_Private_Macros
+  * @{
+  */
+
+/* Check of parameters for configuration of COMP hierarchical scope:          */
+/* COMP instance.                                                             */
+
+#define IS_LL_COMP_POWER_MODE(__POWER_MODE__)                                  \
+  (   ((__POWER_MODE__) == LL_COMP_POWERMODE_HIGHSPEED)                        \
+   || ((__POWER_MODE__) == LL_COMP_POWERMODE_MEDIUMSPEED)                      \
+  )
+
+/* Note: On this STM32 series, comparator input plus parameters are           */
+/*       the same on all COMP instances.                                      */
+/*       However, comparator instance kept as macro parameter for             */
+/*       compatibility with other STM32 families.                             */
+#define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__)               \
+  (   ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1)                             \
+   || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2)                             \
+   || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO3)                             \
+  )
+
+/* Note: On this STM32 series, comparator input minus parameters are          */
+/*       the same on all COMP instances.                                      */
+/*       However, comparator instance kept as macro parameter for             */
+/*       compatibility with other STM32 families.                             */
+#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__)             \
+  (   ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT)                    \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT)                    \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT)                    \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT)                       \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1)                      \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2)                      \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1)                           \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2)                           \
+   || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO3)                           \
+  )
+
+#define IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__)                      \
+  (   ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_NONE)                      \
+   || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_LOW)                       \
+   || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_MEDIUM)                    \
+   || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_HIGH)                      \
+  )
+
+#define IS_LL_COMP_OUTPUT_POLARITY(__POLARITY__)                               \
+  (   ((__POLARITY__) == LL_COMP_OUTPUTPOL_NONINVERTED)                        \
+   || ((__POLARITY__) == LL_COMP_OUTPUTPOL_INVERTED)                           \
+  )
+
+#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__OUTPUT_BLANKING_SOURCE__)          \
+  (   ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE)               \
+   || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC4)           \
+   || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5)           \
+   || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3)           \
+   || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3)           \
+   || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC2)          \
+  )
+
+/**
+  * @}
+  */
+
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup COMP_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup COMP_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize registers of the selected COMP instance
+  *         to their default reset values.
+  * @note   If comparator is locked, de-initialization by software is
+  *         not possible.
+  *         The only way to unlock the comparator is a device hardware reset.
+  * @param  COMPx COMP instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: COMP registers are de-initialized
+  *          - ERROR: COMP registers are not de-initialized
+  */
+ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_COMP_ALL_INSTANCE(COMPx));
+
+  /* Note: Hardware constraint (refer to description of this function):       */
+  /*       COMP instance must not be locked.                                  */
+  if (LL_COMP_IsLocked(COMPx) == 0UL)
+  {
+    LL_COMP_WriteReg(COMPx, CSR, 0x00000000UL);
+
+  }
+  else
+  {
+    /* Comparator instance is locked: de-initialization by software is         */
+    /* not possible.                                                           */
+    /* The only way to unlock the comparator is a device hardware reset.       */
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Initialize some features of COMP instance.
+  * @note   This function configures features of the selected COMP instance.
+  *         Some features are also available at scope COMP common instance
+  *         (common to several COMP instances).
+  *         Refer to functions having argument "COMPxy_COMMON" as parameter.
+  * @param  COMPx COMP instance
+  * @param  COMP_InitStruct Pointer to a @ref LL_COMP_InitTypeDef structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: COMP registers are initialized
+  *          - ERROR: COMP registers are not initialized
+  */
+ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_COMP_ALL_INSTANCE(COMPx));
+  assert_param(IS_LL_COMP_POWER_MODE(COMP_InitStruct->PowerMode));
+  assert_param(IS_LL_COMP_INPUT_PLUS(COMPx, COMP_InitStruct->InputPlus));
+  assert_param(IS_LL_COMP_INPUT_MINUS(COMPx, COMP_InitStruct->InputMinus));
+  assert_param(IS_LL_COMP_INPUT_HYSTERESIS(COMP_InitStruct->InputHysteresis));
+  assert_param(IS_LL_COMP_OUTPUT_POLARITY(COMP_InitStruct->OutputPolarity));
+  assert_param(IS_LL_COMP_OUTPUT_BLANKING_SOURCE(COMP_InitStruct->OutputBlankingSource));
+
+  /* Note: Hardware constraint (refer to description of this function)        */
+  /*       COMP instance must not be locked.                                  */
+  if (LL_COMP_IsLocked(COMPx) == 0UL)
+  {
+    /* Configuration of comparator instance :                                 */
+    /*  - PowerMode                                                           */
+    /*  - InputPlus                                                           */
+    /*  - InputMinus                                                          */
+    /*  - InputHysteresis                                                     */
+    /*  - OutputPolarity                                                      */
+    /*  - OutputBlankingSource                                                */
+    MODIFY_REG(COMPx->CSR,
+               COMP_CSR_PWRMODE
+               | COMP_CSR_INPSEL
+               | COMP_CSR_INMSEL
+               | COMP_CSR_HYST
+               | COMP_CSR_POLARITY
+               | COMP_CSR_BLANKING
+               ,
+               COMP_InitStruct->PowerMode
+               | COMP_InitStruct->InputPlus
+               | COMP_InitStruct->InputMinus
+               | COMP_InitStruct->InputHysteresis
+               | COMP_InitStruct->OutputPolarity
+               | COMP_InitStruct->OutputBlankingSource
+              );
+
+  }
+  else
+  {
+    /* Initialization error: COMP instance is locked.                         */
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief Set each @ref LL_COMP_InitTypeDef field to default value.
+  * @param COMP_InitStruct Pointer to a @ref LL_COMP_InitTypeDef structure
+  *                        whose fields will be set to default values.
+  * @retval None
+  */
+void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct)
+{
+  /* Set COMP_InitStruct fields to default values */
+  COMP_InitStruct->PowerMode            = LL_COMP_POWERMODE_MEDIUMSPEED;
+  COMP_InitStruct->InputPlus            = LL_COMP_INPUT_PLUS_IO1;
+  COMP_InitStruct->InputMinus           = LL_COMP_INPUT_MINUS_VREFINT;
+  COMP_InitStruct->InputHysteresis      = LL_COMP_HYSTERESIS_NONE;
+  COMP_InitStruct->OutputPolarity       = LL_COMP_OUTPUTPOL_NONINVERTED;
+  COMP_InitStruct->OutputBlankingSource = LL_COMP_BLANKINGSRC_NONE;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* COMP1 || COMP2 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_crc.c

@@ -0,0 +1,103 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_ll_crc.c
+  * @author  MCD Application Team
+  * @brief   CRC LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_ll_crc.h"
+#include "stm32g0xx_ll_bus.h"
+
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32G0xx_LL_Driver
+  * @{
+  */
+
+#if defined (CRC)
+
+/** @addtogroup CRC_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CRC_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup CRC_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize CRC registers (Registers restored to their default values).
+  * @param  CRCx CRC Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: CRC registers are de-initialized
+  *          - ERROR: CRC registers are not de-initialized
+  */
+ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_CRC_ALL_INSTANCE(CRCx));
+
+  if (CRCx == CRC)
+  {
+    /* Force CRC reset */
+    LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CRC);
+
+    /* Release CRC reset */
+    LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC);
+  }
+  else
+  {
+    status = ERROR;
+  }
+
+  return (status);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (CRC) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_crs.c

@@ -0,0 +1,83 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_ll_crs.h
+  * @author  MCD Application Team
+  * @brief   CRS LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_ll_crs.h"
+#include "stm32g0xx_ll_bus.h"
+
+/** @addtogroup STM32G0xx_LL_Driver
+  * @{
+  */
+
+#if defined(CRS)
+
+/** @defgroup CRS_LL CRS
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CRS_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup CRS_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-Initializes CRS peripheral registers to their default reset values.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: CRS registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_CRS_DeInit(void)
+{
+  LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_CRS);
+  LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_CRS);
+
+  return  SUCCESS;
+}
+
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(CRS) */
+
+/**
+  * @}
+  */
+  
+#endif /* USE_FULL_LL_DRIVER */

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dac.c

@@ -0,0 +1,293 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_ll_dac.c
+  * @author  MCD Application Team
+  * @brief   DAC LL module driver
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_ll_dac.h"
+#include "stm32g0xx_ll_bus.h"
+
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32G0xx_LL_Driver
+  * @{
+  */
+
+#if defined(DAC1)
+
+/** @addtogroup DAC_LL DAC
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup DAC_LL_Private_Macros
+  * @{
+  */
+#define IS_LL_DAC_CHANNEL(__DAC_CHANNEL__)        \
+  (  ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1)      \
+     || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2)   \
+  )
+
+#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__)                           \
+  (   ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE)                           \
+   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO)                      \
+   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO)                      \
+   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO)                      \
+   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO)                      \
+   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO)                      \
+   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO)                     \
+   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM1_OUT)                     \
+   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_LPTIM2_OUT)                     \
+   || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9)                     \
+  )
+
+#define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__)              \
+  (   ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE)        \
+      || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE)    \
+      || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
+  )
+
+#define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_MODE__, __WAVE_AUTO_GENERATION_CONFIG__)  \
+  ( (((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE)                               \
+     && (  ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0)                           \
+           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0)                     \
+           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0)                     \
+           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0)                     \
+           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0)                     \
+           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0)                     \
+           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0)                     \
+           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0)                     \
+           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0)                     \
+           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0)                     \
+           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0)                    \
+           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0))                   \
+    )                                                                                                     \
+    ||(((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE)                          \
+       && (  ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1)                           \
+             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3)                        \
+             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7)                        \
+             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15)                       \
+             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31)                       \
+             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63)                       \
+             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127)                      \
+             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255)                      \
+             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511)                      \
+             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023)                     \
+             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047)                     \
+             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095))                    \
+      )                                                                                                   \
+  )
+
+#define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__)                             \
+  (   ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE)                     \
+      || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE)                 \
+  )
+
+#define IS_LL_DAC_OUTPUT_CONNECTION(__OUTPUT_CONNECTION__)                     \
+  (   ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_GPIO)                  \
+      || ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_INTERNAL)           \
+  )
+
+#define IS_LL_DAC_OUTPUT_MODE(__OUTPUT_MODE__)                                 \
+  (   ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_NORMAL)                         \
+      || ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD)             \
+  )
+
+/**
+  * @}
+  */
+
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DAC_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DAC_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize registers of the selected DAC instance
+  *         to their default reset values.
+  * @param  DACx DAC instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: DAC registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_ALL_INSTANCE(DACx));
+
+  /* Force reset of DAC clock */
+  LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC1);
+
+  /* Release reset of DAC clock */
+  LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC1);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Initialize some features of DAC channel.
+  * @note   @ref LL_DAC_Init() aims to ease basic configuration of a DAC channel.
+  *         Leaving it ready to be enabled and output:
+  *         a level by calling one of
+  *           @ref LL_DAC_ConvertData12RightAligned
+  *           @ref LL_DAC_ConvertData12LeftAligned
+  *           @ref LL_DAC_ConvertData8RightAligned
+  *         or one of the supported autogenerated wave.
+  * @note   This function allows configuration of:
+  *          - Output mode
+  *          - Trigger
+  *          - Wave generation
+  * @note   The setting of these parameters by function @ref LL_DAC_Init()
+  *         is conditioned to DAC state:
+  *         DAC channel must be disabled.
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2
+  * @param  DAC_InitStruct Pointer to a @ref LL_DAC_InitTypeDef structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: DAC registers are initialized
+  *          - ERROR: DAC registers are not initialized
+  */
+ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_DAC_ALL_INSTANCE(DACx));
+  assert_param(IS_LL_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_LL_DAC_TRIGGER_SOURCE(DAC_InitStruct->TriggerSource));
+  assert_param(IS_LL_DAC_OUTPUT_BUFFER(DAC_InitStruct->OutputBuffer));
+  assert_param(IS_LL_DAC_OUTPUT_CONNECTION(DAC_InitStruct->OutputConnection));
+  assert_param(IS_LL_DAC_OUTPUT_MODE(DAC_InitStruct->OutputMode));
+  assert_param(IS_LL_DAC_WAVE_AUTO_GENER_MODE(DAC_InitStruct->WaveAutoGeneration));
+  if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
+  {
+    assert_param(IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(DAC_InitStruct->WaveAutoGeneration,
+                                                  DAC_InitStruct->WaveAutoGenerationConfig));
+  }
+
+  /* Note: Hardware constraint (refer to description of this function)        */
+  /*       DAC instance must be disabled.                                     */
+  if (LL_DAC_IsEnabled(DACx, DAC_Channel) == 0UL)
+  {
+    /* Configuration of DAC channel:                                          */
+    /*  - TriggerSource                                                       */
+    /*  - WaveAutoGeneration                                                  */
+    /*  - OutputBuffer                                                        */
+    /*  - OutputConnection                                                    */
+    /*  - OutputMode                                                          */
+    if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
+    {
+      MODIFY_REG(DACx->CR,
+                 (DAC_CR_TSEL1
+                  | DAC_CR_WAVE1
+                  | DAC_CR_MAMP1
+                 ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                 ,
+                 (DAC_InitStruct->TriggerSource
+                  | DAC_InitStruct->WaveAutoGeneration
+                  | DAC_InitStruct->WaveAutoGenerationConfig
+                 ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                );
+    }
+    else
+    {
+      MODIFY_REG(DACx->CR,
+                 (DAC_CR_TSEL1
+                  | DAC_CR_WAVE1
+                 ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                 ,
+                 (DAC_InitStruct->TriggerSource
+                  | LL_DAC_WAVE_AUTO_GENERATION_NONE
+                 ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                );
+    }
+    MODIFY_REG(DACx->MCR,
+               (DAC_MCR_MODE1_1
+                | DAC_MCR_MODE1_0
+                | DAC_MCR_MODE1_2
+               ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+               ,
+               (DAC_InitStruct->OutputBuffer
+                | DAC_InitStruct->OutputConnection
+                | DAC_InitStruct->OutputMode
+               ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+              );
+  }
+  else
+  {
+    /* Initialization error: DAC instance is not disabled.                    */
+    status = ERROR;
+  }
+  return status;
+}
+
+/**
+  * @brief Set each @ref LL_DAC_InitTypeDef field to default value.
+  * @param DAC_InitStruct pointer to a @ref LL_DAC_InitTypeDef structure
+  *                       whose fields will be set to default values.
+  * @retval None
+  */
+void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct)
+{
+  /* Set DAC_InitStruct fields to default values */
+  DAC_InitStruct->TriggerSource            = LL_DAC_TRIG_SOFTWARE;
+  DAC_InitStruct->WaveAutoGeneration       = LL_DAC_WAVE_AUTO_GENERATION_NONE;
+  /* Note: Parameter discarded if wave auto generation is disabled,           */
+  /*       set anyway to its default value.                                   */
+  DAC_InitStruct->WaveAutoGenerationConfig = LL_DAC_NOISE_LFSR_UNMASK_BIT0;
+  DAC_InitStruct->OutputBuffer             = LL_DAC_OUTPUT_BUFFER_ENABLE;
+  DAC_InitStruct->OutputConnection         = LL_DAC_OUTPUT_CONNECT_GPIO;
+  DAC_InitStruct->OutputMode               = LL_DAC_OUTPUT_MODE_NORMAL;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* DAC1 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_exti.c

@@ -0,0 +1,293 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_ll_exti.c
+  * @author  MCD Application Team
+  * @brief   EXTI LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_ll_exti.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32G0xx_LL_Driver
+  * @{
+  */
+
+#if defined (EXTI)
+
+/** @defgroup EXTI_LL EXTI
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup EXTI_LL_Private_Macros
+  * @{
+  */
+
+#define IS_LL_EXTI_LINE_0_31(__VALUE__)              (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
+#if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
+#define IS_LL_EXTI_LINE_32_63(__VALUE__)             (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U)
+#endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
+#define IS_LL_EXTI_MODE(__VALUE__)                   (((__VALUE__) == LL_EXTI_MODE_IT)            \
+                                                   || ((__VALUE__) == LL_EXTI_MODE_EVENT)         \
+                                                   || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
+
+
+#define IS_LL_EXTI_TRIGGER(__VALUE__)                (((__VALUE__) == LL_EXTI_TRIGGER_NONE)       \
+                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_RISING)     \
+                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING)    \
+                                                   || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup EXTI_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup EXTI_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize the EXTI registers to their default reset values.
+  * @retval An ErrorStatus enumeration value:
+  *          - 0x00: EXTI registers are de-initialized
+  */
+uint32_t LL_EXTI_DeInit(void)
+{
+  /* Interrupt mask register set to default reset values */
+  LL_EXTI_WriteReg(IMR1,   0xFFF80000U);
+  /* Event mask register set to default reset values */
+  LL_EXTI_WriteReg(EMR1,   0x00000000U);
+  /* Rising Trigger selection register set to default reset values */
+  LL_EXTI_WriteReg(RTSR1,  0x00000000U);
+  /* Falling Trigger selection register set to default reset values */
+  LL_EXTI_WriteReg(FTSR1,  0x00000000U);
+  /* Software interrupt event register set to default reset values */
+  LL_EXTI_WriteReg(SWIER1, 0x00000000U);
+  /* Pending register set to default reset values */
+#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
+  LL_EXTI_WriteReg(RPR1,    0x0017FFFFU);
+  LL_EXTI_WriteReg(FPR1,    0x0017FFFFU);
+#elif defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G061xx) || defined(STM32G051xx)
+  LL_EXTI_WriteReg(RPR1,    0x0007FFFFU);
+  LL_EXTI_WriteReg(FPR1,    0x0007FFFFU);
+#elif defined(STM32G041xx) || defined(STM32G031xx)
+  LL_EXTI_WriteReg(RPR1,    0x0001FFFFU);
+  LL_EXTI_WriteReg(FPR1,    0x0001FFFFU);
+#elif defined(STM32G0B0xx) || defined(STM32G070xx) || defined(STM32G050xx) || defined(STM32G030xx)
+  LL_EXTI_WriteReg(RPR1,    0x0000FFFFU);
+  LL_EXTI_WriteReg(FPR1,    0x0000FFFFU);
+#endif /* STM32G0C1xx || STM32G0B1xx */
+
+#if defined(STM32G081xx) || defined(STM32G071xx)
+  /* Interrupt mask register 2 set to default reset values */
+  LL_EXTI_WriteReg(IMR2, 0x00000003U);
+  /* Event mask register 2 set to default reset values */
+  LL_EXTI_WriteReg(EMR2, 0x00000000U);
+#elif defined(STM32G0C1xx) || defined(STM32G0B1xx)
+  /* Interrupt mask register 2 set to default reset values */
+  LL_EXTI_WriteReg(IMR2, 0x0000001FU);
+  /* Event mask register 2 set to default reset values */
+  LL_EXTI_WriteReg(EMR2, 0x00000000U);
+  /* Rising Trigger selection register set to default reset values */
+  LL_EXTI_WriteReg(RTSR2, 0x00000000U);
+  /* Falling Trigger selection register set to default reset values */
+  LL_EXTI_WriteReg(FTSR2, 0x00000000U);
+  /* Software interrupt event register set to default reset values */
+  LL_EXTI_WriteReg(SWIER2, 0x00000000U);
+  /* Pending register set to default reset values */
+  LL_EXTI_WriteReg(RPR2, 0x00000004U);
+  LL_EXTI_WriteReg(FPR2, 0x00000004U);
+#elif defined(STM32G0B0xx)
+  /* Interrupt mask register 2 set to default reset values */
+  LL_EXTI_WriteReg(IMR2, 0x00000010U);
+  /* Event mask register 2 set to default reset values */
+  LL_EXTI_WriteReg(EMR2, 0x00000000U);
+#endif /* STM32G081xx || STM32G071xx */
+
+  return 0x00u;
+}
+
+/**
+  * @brief  Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
+  * @param  EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
+  * @retval An ErrorStatus enumeration value:
+  *          - 0x00: EXTI registers are initialized
+  *          - any other value : wrong configuration
+  */
+uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
+{
+  uint32_t status = 0x00u;
+
+  /* Check the parameters */
+  assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
+#if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
+  assert_param(IS_LL_EXTI_LINE_32_63(EXTI_InitStruct->Line_32_63));
+#endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
+  assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
+  assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
+
+  /* ENABLE LineCommand */
+  if (EXTI_InitStruct->LineCommand != DISABLE)
+  {
+    assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
+
+    /* Configure EXTI Lines in range from 0 to 31 */
+    if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
+    {
+      switch (EXTI_InitStruct->Mode)
+      {
+        case LL_EXTI_MODE_IT:
+          /* First Disable Event on provided Lines */
+          LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
+          /* Then Enable IT on provided Lines */
+          LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
+          break;
+        case LL_EXTI_MODE_EVENT:
+          /* First Disable IT on provided Lines */
+          LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
+          /* Then Enable Event on provided Lines */
+          LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
+          break;
+        case LL_EXTI_MODE_IT_EVENT:
+          /* Directly Enable IT & Event on provided Lines */
+          LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
+          LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
+          break;
+        default:
+          status = 0x01u;
+          break;
+      }
+      if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
+      {
+        switch (EXTI_InitStruct->Trigger)
+        {
+          case LL_EXTI_TRIGGER_RISING:
+            /* First Disable Falling Trigger on provided Lines */
+            LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            /* Then Enable Rising Trigger on provided Lines */
+            LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            break;
+          case LL_EXTI_TRIGGER_FALLING:
+            /* First Disable Rising Trigger on provided Lines */
+            LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            /* Then Enable Falling Trigger on provided Lines */
+            LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            break;
+          case LL_EXTI_TRIGGER_RISING_FALLING:
+            LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+            break;
+          default:
+            status |= 0x02u;
+            break;
+        }
+      }
+    }
+#if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
+    /* Configure EXTI Lines in range from 32 to 63 */
+    if (EXTI_InitStruct->Line_32_63 != LL_EXTI_LINE_NONE)
+    {
+      switch (EXTI_InitStruct->Mode)
+      {
+        case LL_EXTI_MODE_IT:
+          /* First Disable Event on provided Lines */
+          LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
+          /* Then Enable IT on provided Lines */
+          LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63);
+          break;
+        case LL_EXTI_MODE_EVENT:
+          /* First Disable IT on provided Lines */
+          LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
+          /* Then Enable Event on provided Lines */
+          LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
+          break;
+        case LL_EXTI_MODE_IT_EVENT:
+          /* Directly Enable IT & Event on provided Lines */
+          LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63);
+          LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
+          break;
+        default:
+          status |= 0x04u;
+          break;
+      }
+    }
+#endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
+  }
+  /* DISABLE LineCommand */
+  else
+  {
+    /* De-configure EXTI Lines in range from 0 to 31 */
+    LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
+    LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
+#if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
+    /* De-configure EXTI Lines in range from 32 to 63 */
+    LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
+    LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
+#endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_EXTI_InitTypeDef field to default value.
+  * @param  EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
+  * @retval None
+  */
+void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
+{
+  EXTI_InitStruct->Line_0_31      = LL_EXTI_LINE_NONE;
+#if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
+  EXTI_InitStruct->Line_32_63     = LL_EXTI_LINE_NONE;
+#endif /* STM32G081xx || STM32G071xx || STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
+  EXTI_InitStruct->LineCommand    = DISABLE;
+  EXTI_InitStruct->Mode           = LL_EXTI_MODE_IT;
+  EXTI_InitStruct->Trigger        = LL_EXTI_TRIGGER_FALLING;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (EXTI) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_gpio.c

@@ -0,0 +1,278 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_ll_gpio.c
+  * @author  MCD Application Team
+  * @brief   GPIO LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_ll_gpio.h"
+#include "stm32g0xx_ll_bus.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32G0xx_LL_Driver
+  * @{
+  */
+
+#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF)
+
+/** @addtogroup GPIO_LL
+  * @{
+  */
+/** MISRA C:2012 deviation rule has been granted for following rules:
+  * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of
+  * range of the shift operator in following API :
+  * LL_GPIO_Init
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup GPIO_LL_Private_Macros
+  * @{
+  */
+#define IS_LL_GPIO_PIN(__VALUE__)          (((0x00u) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
+
+#define IS_LL_GPIO_MODE(__VALUE__)         (((__VALUE__) == LL_GPIO_MODE_INPUT)     ||\
+                                            ((__VALUE__) == LL_GPIO_MODE_OUTPUT)    ||\
+                                            ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\
+                                            ((__VALUE__) == LL_GPIO_MODE_ANALOG))
+
+#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__)  (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL)  ||\
+                                            ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
+
+#define IS_LL_GPIO_SPEED(__VALUE__)        (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW)       ||\
+                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM)    ||\
+                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH)      ||\
+                                            ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH))
+
+#define IS_LL_GPIO_PULL(__VALUE__)         (((__VALUE__) == LL_GPIO_PULL_NO)   ||\
+                                            ((__VALUE__) == LL_GPIO_PULL_UP)   ||\
+                                            ((__VALUE__) == LL_GPIO_PULL_DOWN))
+
+#if defined(GPIOE)
+#define IS_LL_GPIO_ALTERNATE(__VALUE__)    (((__VALUE__) == LL_GPIO_AF_0  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_1  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_2  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_3  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_4  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_5  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_6  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_7  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_8  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_9  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_10 ))
+#else
+#define IS_LL_GPIO_ALTERNATE(__VALUE__)    (((__VALUE__) == LL_GPIO_AF_0  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_1  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_2  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_3  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_4  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_5  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_6  )   ||\
+                                            ((__VALUE__) == LL_GPIO_AF_7 ))
+#endif /* GPIOE */
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup GPIO_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup GPIO_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize GPIO registers (Registers restored to their default values).
+  * @param  GPIOx GPIO Port
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: GPIO registers are de-initialized
+  *          - ERROR:   Wrong GPIO Port
+  */
+ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+
+  /* Force and Release reset on clock of GPIOx Port */
+  if (GPIOx == GPIOA)
+  {
+    LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOA);
+    LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOA);
+  }
+  else if (GPIOx == GPIOB)
+  {
+    LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOB);
+    LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOB);
+  }
+  else if (GPIOx == GPIOC)
+  {
+    LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOC);
+    LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOC);
+  }
+#if defined(GPIOD)
+  else if (GPIOx == GPIOD)
+  {
+    LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOD);
+    LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOD);
+  }
+#endif /* GPIOD */
+#if defined(GPIOE)
+  else if (GPIOx == GPIOE)
+  {
+    LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOE);
+    LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOE);
+  }
+#endif /* GPIOE */
+#if defined(GPIOF)
+  else if (GPIOx == GPIOF)
+  {
+    LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOF);
+    LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOF);
+  }
+#endif /* GPIOF */
+  else
+  {
+    status = ERROR;
+  }
+
+  return (status);
+}
+
+/**
+  * @brief  Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
+  * @param  GPIOx GPIO Port
+  * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
+  *         that contains the configuration information for the specified GPIO peripheral.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
+  *          - ERROR:   Not applicable
+  */
+ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
+{
+  uint32_t pinpos;
+  uint32_t currentpin;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
+  assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
+  assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
+
+  /* ------------------------- Configure the port pins ---------------- */
+  /* Initialize  pinpos on first pin set */
+  pinpos = 0;
+
+  /* Configure the port pins */
+  while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00u)
+  {
+    /* Get current io position */
+    currentpin = (GPIO_InitStruct->Pin) & (0x00000001uL << pinpos);
+
+    if (currentpin != 0x00u)
+    {
+      if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
+      {
+        /* Check Speed mode parameters */
+        assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));
+
+        /* Speed mode configuration */
+        LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
+
+        /* Check Output mode parameters */
+        assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
+
+        /* Output mode configuration*/
+        LL_GPIO_SetPinOutputType(GPIOx, currentpin, GPIO_InitStruct->OutputType);
+      }
+
+      /* Pull-up Pull down resistor configuration*/
+      LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
+
+      if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)
+      {
+        /* Check Alternate parameter */
+        assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));
+
+        /* Speed mode configuration */
+        if (currentpin < LL_GPIO_PIN_8)
+        {
+          LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate);
+        }
+        else
+        {
+          LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
+        }
+      }
+
+      /* Pin Mode configuration */
+      LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
+    }
+    pinpos++;
+  }
+
+  return (SUCCESS);
+}
+
+/**
+  * @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
+  * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
+  *                          whose fields will be set to default values.
+  * @retval None
+  */
+
+void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
+{
+  /* Reset GPIO init structure parameters values */
+  GPIO_InitStruct->Pin        = LL_GPIO_PIN_ALL;
+  GPIO_InitStruct->Mode       = LL_GPIO_MODE_ANALOG;
+  GPIO_InitStruct->Speed      = LL_GPIO_SPEED_FREQ_LOW;
+  GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+  GPIO_InitStruct->Pull       = LL_GPIO_PULL_NO;
+  GPIO_InitStruct->Alternate  = LL_GPIO_AF_0;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_i2c.c

@@ -0,0 +1,234 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_ll_i2c.c
+  * @author  MCD Application Team
+  * @brief   I2C LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_ll_i2c.h"
+#include "stm32g0xx_ll_bus.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32G0xx_LL_Driver
+  * @{
+  */
+
+#if defined (I2C1) || defined (I2C2) || defined (I2C3)
+
+/** @defgroup I2C_LL I2C
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup I2C_LL_Private_Macros
+  * @{
+  */
+
+#define IS_LL_I2C_PERIPHERAL_MODE(__VALUE__)    (((__VALUE__) == LL_I2C_MODE_I2C)          || \
+                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_HOST)   || \
+                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
+                                                 ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))
+
+#define IS_LL_I2C_ANALOG_FILTER(__VALUE__)      (((__VALUE__) == LL_I2C_ANALOGFILTER_ENABLE) || \
+                                                 ((__VALUE__) == LL_I2C_ANALOGFILTER_DISABLE))
+
+#define IS_LL_I2C_DIGITAL_FILTER(__VALUE__)     ((__VALUE__) <= 0x0000000FU)
+
+#define IS_LL_I2C_OWN_ADDRESS1(__VALUE__)       ((__VALUE__) <= 0x000003FFU)
+
+#define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__)   (((__VALUE__) == LL_I2C_ACK) || \
+                                                 ((__VALUE__) == LL_I2C_NACK))
+
+#define IS_LL_I2C_OWN_ADDRSIZE(__VALUE__)       (((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \
+                                                 ((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT))
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2C_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup I2C_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize the I2C registers to their default reset values.
+  * @param  I2Cx I2C Instance.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: I2C registers are de-initialized
+  *          - ERROR: I2C registers are not de-initialized
+  */
+ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the I2C Instance I2Cx */
+  assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
+
+  if (I2Cx == I2C1)
+  {
+    /* Force reset of I2C clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1);
+
+    /* Release reset of I2C clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1);
+  }
+  else if (I2Cx == I2C2)
+  {
+    /* Force reset of I2C clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2);
+
+    /* Release reset of I2C clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2);
+
+  }
+#if defined(I2C3)
+  else if (I2Cx == I2C3)
+  {
+    /* Force reset of I2C clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3);
+
+    /* Release reset of I2C clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3);
+  }
+#endif /* I2C3 */
+  else
+  {
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
+  * @param  I2Cx I2C Instance.
+  * @param  I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: I2C registers are initialized
+  *          - ERROR: Not applicable
+  */
+ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
+{
+  /* Check the I2C Instance I2Cx */
+  assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
+
+  /* Check the I2C parameters from I2C_InitStruct */
+  assert_param(IS_LL_I2C_PERIPHERAL_MODE(I2C_InitStruct->PeripheralMode));
+  assert_param(IS_LL_I2C_ANALOG_FILTER(I2C_InitStruct->AnalogFilter));
+  assert_param(IS_LL_I2C_DIGITAL_FILTER(I2C_InitStruct->DigitalFilter));
+  assert_param(IS_LL_I2C_OWN_ADDRESS1(I2C_InitStruct->OwnAddress1));
+  assert_param(IS_LL_I2C_TYPE_ACKNOWLEDGE(I2C_InitStruct->TypeAcknowledge));
+  assert_param(IS_LL_I2C_OWN_ADDRSIZE(I2C_InitStruct->OwnAddrSize));
+
+  /* Disable the selected I2Cx Peripheral */
+  LL_I2C_Disable(I2Cx);
+
+  /*---------------------------- I2Cx CR1 Configuration ------------------------
+   * Configure the analog and digital noise filters with parameters :
+   * - AnalogFilter: I2C_CR1_ANFOFF bit
+   * - DigitalFilter: I2C_CR1_DNF[3:0] bits
+   */
+  LL_I2C_ConfigFilters(I2Cx, I2C_InitStruct->AnalogFilter, I2C_InitStruct->DigitalFilter);
+
+  /*---------------------------- I2Cx TIMINGR Configuration --------------------
+   * Configure the SDA setup, hold time and the SCL high, low period with parameter :
+   * - Timing: I2C_TIMINGR_PRESC[3:0], I2C_TIMINGR_SCLDEL[3:0], I2C_TIMINGR_SDADEL[3:0],
+   *           I2C_TIMINGR_SCLH[7:0] and I2C_TIMINGR_SCLL[7:0] bits
+   */
+  LL_I2C_SetTiming(I2Cx, I2C_InitStruct->Timing);
+
+  /* Enable the selected I2Cx Peripheral */
+  LL_I2C_Enable(I2Cx);
+
+  /*---------------------------- I2Cx OAR1 Configuration -----------------------
+   * Disable, Configure and Enable I2Cx device own address 1 with parameters :
+   * - OwnAddress1:  I2C_OAR1_OA1[9:0] bits
+   * - OwnAddrSize:  I2C_OAR1_OA1MODE bit
+   */
+  LL_I2C_DisableOwnAddress1(I2Cx);
+  LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize);
+
+  /* OwnAdress1 == 0 is reserved for General Call address */
+  if (I2C_InitStruct->OwnAddress1 != 0U)
+  {
+    LL_I2C_EnableOwnAddress1(I2Cx);
+  }
+
+  /*---------------------------- I2Cx MODE Configuration -----------------------
+  * Configure I2Cx peripheral mode with parameter :
+   * - PeripheralMode: I2C_CR1_SMBDEN and I2C_CR1_SMBHEN bits
+   */
+  LL_I2C_SetMode(I2Cx, I2C_InitStruct->PeripheralMode);
+
+  /*---------------------------- I2Cx CR2 Configuration ------------------------
+   * Configure the ACKnowledge or Non ACKnowledge condition
+   * after the address receive match code or next received byte with parameter :
+   * - TypeAcknowledge: I2C_CR2_NACK bit
+   */
+  LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Set each @ref LL_I2C_InitTypeDef field to default value.
+  * @param  I2C_InitStruct Pointer to a @ref LL_I2C_InitTypeDef structure.
+  * @retval None
+  */
+void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct)
+{
+  /* Set I2C_InitStruct fields to default values */
+  I2C_InitStruct->PeripheralMode  = LL_I2C_MODE_I2C;
+  I2C_InitStruct->Timing          = 0U;
+  I2C_InitStruct->AnalogFilter    = LL_I2C_ANALOGFILTER_ENABLE;
+  I2C_InitStruct->DigitalFilter   = 0U;
+  I2C_InitStruct->OwnAddress1     = 0U;
+  I2C_InitStruct->TypeAcknowledge = LL_I2C_NACK;
+  I2C_InitStruct->OwnAddrSize     = LL_I2C_OWNADDRESS1_7BIT;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* I2C1 || I2C2 || I2C3 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_lptim.c

@@ -0,0 +1,318 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_ll_lptim.c
+  * @author  MCD Application Team
+  * @brief   LPTIM LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_ll_lptim.h"
+#include "stm32g0xx_ll_bus.h"
+#include "stm32g0xx_ll_rcc.h"
+
+
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32G0xx_LL_Driver
+  * @{
+  */
+
+#if defined (LPTIM1) || defined (LPTIM2)
+
+/** @addtogroup LPTIM_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup LPTIM_LL_Private_Macros
+  * @{
+  */
+#define IS_LL_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \
+                                             || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL))
+
+#define IS_LL_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1)   \
+                                                || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2)   \
+                                                || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4)   \
+                                                || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8)   \
+                                                || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16)  \
+                                                || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32)  \
+                                                || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64)  \
+                                                || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128))
+
+#define IS_LL_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \
+                                         || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE))
+
+#define IS_LL_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \
+                                                || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE))
+/**
+  * @}
+  */
+
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
+  * @{
+  */
+/**
+  * @}
+  */
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup LPTIM_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup LPTIM_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  Set LPTIMx registers to their reset values.
+  * @param  LPTIMx LP Timer instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: LPTIMx registers are de-initialized
+  *          - ERROR: invalid LPTIMx instance
+  */
+ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx)
+{
+  ErrorStatus result = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(LPTIMx));
+
+  if (LPTIMx == LPTIM1)
+  {
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1);
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1);
+  }
+#if defined(LPTIM2)
+  else if (LPTIMx == LPTIM2)
+  {
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM2);
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM2);
+  }
+#endif /* LPTIM2 */
+  else
+  {
+    result = ERROR;
+  }
+
+  return result;
+}
+
+/**
+  * @brief  Set each fields of the LPTIM_InitStruct structure to its default
+  *         value.
+  * @param  LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure
+  * @retval None
+  */
+void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
+{
+  /* Set the default configuration */
+  LPTIM_InitStruct->ClockSource = LL_LPTIM_CLK_SOURCE_INTERNAL;
+  LPTIM_InitStruct->Prescaler   = LL_LPTIM_PRESCALER_DIV1;
+  LPTIM_InitStruct->Waveform    = LL_LPTIM_OUTPUT_WAVEFORM_PWM;
+  LPTIM_InitStruct->Polarity    = LL_LPTIM_OUTPUT_POLARITY_REGULAR;
+}
+
+/**
+  * @brief  Configure the LPTIMx peripheral according to the specified parameters.
+  * @note LL_LPTIM_Init can only be called when the LPTIM instance is disabled.
+  * @note LPTIMx can be disabled using unitary function @ref LL_LPTIM_Disable().
+  * @param  LPTIMx LP Timer Instance
+  * @param  LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: LPTIMx instance has been initialized
+  *          - ERROR: LPTIMx instance hasn't been initialized
+  */
+ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
+{
+  ErrorStatus result = SUCCESS;
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(LPTIMx));
+  assert_param(IS_LL_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource));
+  assert_param(IS_LL_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler));
+  assert_param(IS_LL_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform));
+  assert_param(IS_LL_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity));
+
+  /* The LPTIMx_CFGR register must only be modified when the LPTIM is disabled
+     (ENABLE bit is reset to 0).
+  */
+  if (LL_LPTIM_IsEnabled(LPTIMx) == 1UL)
+  {
+    result = ERROR;
+  }
+  else
+  {
+    /* Set CKSEL bitfield according to ClockSource value */
+    /* Set PRESC bitfield according to Prescaler value */
+    /* Set WAVE bitfield according to Waveform value */
+    /* Set WAVEPOL bitfield according to Polarity value */
+    MODIFY_REG(LPTIMx->CFGR,
+               (LPTIM_CFGR_CKSEL | LPTIM_CFGR_PRESC | LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL),
+               LPTIM_InitStruct->ClockSource | \
+               LPTIM_InitStruct->Prescaler | \
+               LPTIM_InitStruct->Waveform | \
+               LPTIM_InitStruct->Polarity);
+  }
+
+  return result;
+}
+
+/**
+  * @brief  Disable the LPTIM instance
+  * @rmtoll CR           ENABLE        LL_LPTIM_Disable
+  * @param  LPTIMx Low-Power Timer instance
+  * @note   The following sequence is required to solve LPTIM disable HW limitation.
+  *         Please check Errata Sheet ES0335 for more details under "MCU may remain
+  *         stuck in LPTIM interrupt when entering Stop mode" section.
+  * @retval None
+  */
+void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
+{
+  LL_RCC_ClocksTypeDef rcc_clock;
+  uint32_t tmpclksource = 0;
+  uint32_t tmpIER;
+  uint32_t tmpCFGR;
+  uint32_t tmpCMP;
+  uint32_t tmpARR;
+  uint32_t primask_bit;
+  uint32_t tmpCFGR2;
+
+  /* Check the parameters */
+  assert_param(IS_LPTIM_INSTANCE(LPTIMx));
+
+  /* Enter critical section */
+  primask_bit = __get_PRIMASK();
+  __set_PRIMASK(1) ;
+
+  /********** Save LPTIM Config *********/
+  /* Save LPTIM source clock */
+  switch ((uint32_t)LPTIMx)
+  {
+    case LPTIM1_BASE:
+      tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE);
+      break;
+#if defined(LPTIM2)
+    case LPTIM2_BASE:
+      tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE);
+      break;
+#endif /* LPTIM2 */
+    default:
+      break;
+  }
+
+  /* Save LPTIM configuration registers */
+  tmpIER = LPTIMx->IER;
+  tmpCFGR = LPTIMx->CFGR;
+  tmpCMP = LPTIMx->CMP;
+  tmpARR = LPTIMx->ARR;
+  tmpCFGR2 = LPTIMx->CFGR2;
+
+  /************* Reset LPTIM ************/
+  (void)LL_LPTIM_DeInit(LPTIMx);
+
+  /********* Restore LPTIM Config *******/
+  LL_RCC_GetSystemClocksFreq(&rcc_clock);
+
+  if ((tmpCMP != 0UL) || (tmpARR != 0UL))
+  {
+    /* Force LPTIM source kernel clock from APB */
+    switch ((uint32_t)LPTIMx)
+    {
+      case LPTIM1_BASE:
+        LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1);
+        break;
+#if defined(LPTIM2)
+      case LPTIM2_BASE:
+        LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE_PCLK1);
+        break;
+#endif /* LPTIM2 */
+      default:
+        break;
+    }
+
+    if (tmpCMP != 0UL)
+    {
+      /* Restore CMP and ARR registers (LPTIM should be enabled first) */
+      LPTIMx->CR |= LPTIM_CR_ENABLE;
+      LPTIMx->CMP = tmpCMP;
+
+      /* Polling on CMP write ok status after above restore operation */
+      do
+      {
+        rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
+      } while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
+
+      LL_LPTIM_ClearFlag_CMPOK(LPTIMx);
+    }
+
+    if (tmpARR != 0UL)
+    {
+      LPTIMx->CR |= LPTIM_CR_ENABLE;
+      LPTIMx->ARR = tmpARR;
+
+      LL_RCC_GetSystemClocksFreq(&rcc_clock);
+      /* Polling on ARR write ok status after above restore operation */
+      do
+      {
+        rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
+      }
+      while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
+
+      LL_LPTIM_ClearFlag_ARROK(LPTIMx);
+    }
+
+
+    /* Restore LPTIM source kernel clock */
+    LL_RCC_SetLPTIMClockSource(tmpclksource);
+  }
+
+  /* Restore configuration registers (LPTIM should be disabled first) */
+  LPTIMx->CR &= ~(LPTIM_CR_ENABLE);
+  LPTIMx->IER = tmpIER;
+  LPTIMx->CFGR = tmpCFGR;
+  LPTIMx->CFGR2 = tmpCFGR2;
+
+  /* Exit critical section: restore previous priority mask */
+  __set_PRIMASK(primask_bit);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* LPTIM1 || LPTIM2 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_lpuart.c

@@ -0,0 +1,311 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_ll_lpuart.c
+  * @author  MCD Application Team
+  * @brief   LPUART LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_ll_lpuart.h"
+#include "stm32g0xx_ll_rcc.h"
+#include "stm32g0xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32G0xx_LL_Driver
+  * @{
+  */
+
+#if defined (LPUART1) || defined (LPUART2)
+
+/** @addtogroup LPUART_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup LPUART_LL_Private_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup LPUART_LL_Private_Macros
+  * @{
+  */
+
+/* Check of parameters for configuration of LPUART registers                  */
+
+#define IS_LL_LPUART_PRESCALER(__VALUE__)  (((__VALUE__) == LL_LPUART_PRESCALER_DIV1) \
+                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV2) \
+                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV4) \
+                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV6) \
+                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV8) \
+                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV10) \
+                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV12) \
+                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV16) \
+                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV32) \
+                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV64) \
+                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV128) \
+                                            || ((__VALUE__) == LL_LPUART_PRESCALER_DIV256))
+
+/* __BAUDRATE__ Depending on constraints applicable for LPUART BRR register   */
+/*              value :                                                       */
+/*                - fck must be in the range [3 x baudrate, 4096 x baudrate]  */
+/*                - LPUART_BRR register value should be >= 0x300              */
+/*                - LPUART_BRR register value should be <= 0xFFFFF (20 bits)  */
+/*              Baudrate specified by the user should belong to [8, 21300000].*/
+#define IS_LL_LPUART_BAUDRATE(__BAUDRATE__) (((__BAUDRATE__) <= 21300000U) && ((__BAUDRATE__) >= 8U))
+
+/* __VALUE__ BRR content must be greater than or equal to 0x300. */
+#define IS_LL_LPUART_BRR_MIN(__VALUE__)   ((__VALUE__) >= 0x300U)
+
+/* __VALUE__ BRR content must be lower than or equal to 0xFFFFF. */
+#define IS_LL_LPUART_BRR_MAX(__VALUE__)   ((__VALUE__) <= 0x000FFFFFU)
+
+#define IS_LL_LPUART_DIRECTION(__VALUE__) (((__VALUE__) == LL_LPUART_DIRECTION_NONE) \
+                                           || ((__VALUE__) == LL_LPUART_DIRECTION_RX) \
+                                           || ((__VALUE__) == LL_LPUART_DIRECTION_TX) \
+                                           || ((__VALUE__) == LL_LPUART_DIRECTION_TX_RX))
+
+#define IS_LL_LPUART_PARITY(__VALUE__) (((__VALUE__) == LL_LPUART_PARITY_NONE) \
+                                        || ((__VALUE__) == LL_LPUART_PARITY_EVEN) \
+                                        || ((__VALUE__) == LL_LPUART_PARITY_ODD))
+
+#define IS_LL_LPUART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_LPUART_DATAWIDTH_7B) \
+                                           || ((__VALUE__) == LL_LPUART_DATAWIDTH_8B) \
+                                           || ((__VALUE__) == LL_LPUART_DATAWIDTH_9B))
+
+#define IS_LL_LPUART_STOPBITS(__VALUE__) (((__VALUE__) == LL_LPUART_STOPBITS_1) \
+                                          || ((__VALUE__) == LL_LPUART_STOPBITS_2))
+
+#define IS_LL_LPUART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_LPUART_HWCONTROL_NONE) \
+                                           || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS) \
+                                           || ((__VALUE__) == LL_LPUART_HWCONTROL_CTS) \
+                                           || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS_CTS))
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup LPUART_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup LPUART_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize LPUART registers (Registers restored to their default values).
+  * @param  LPUARTx LPUART Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: LPUART registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_LPUART_INSTANCE(LPUARTx));
+
+  if (LPUARTx == LPUART1)
+  {
+    /* Force reset of LPUART peripheral */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPUART1);
+
+    /* Release reset of LPUART peripheral */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPUART1);
+  }
+#if defined(LPUART2)
+  else if (LPUARTx == LPUART2)
+  {
+    /* Force reset of LPUART peripheral */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPUART2);
+
+    /* Release reset of LPUART peripheral */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPUART2);
+  }
+#endif /* LPUART2 */
+  else
+  {
+    status = ERROR;
+  }
+
+  return (status);
+}
+
+/**
+  * @brief  Initialize LPUART registers according to the specified
+  *         parameters in LPUART_InitStruct.
+  * @note   As some bits in LPUART configuration registers can only be written when
+  *         the LPUART is disabled (USART_CR1_UE bit =0),
+  *         LPUART Peripheral should be in disabled state prior calling this function.
+  *         Otherwise, ERROR result will be returned.
+  * @note   Baud rate value stored in LPUART_InitStruct BaudRate field, should be valid (different from 0).
+  * @param  LPUARTx LPUART Instance
+  * @param  LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure
+  *         that contains the configuration information for the specified LPUART peripheral.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: LPUART registers are initialized according to LPUART_InitStruct content
+  *          - ERROR: Problem occurred during LPUART Registers initialization
+  */
+ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct)
+{
+  ErrorStatus status = ERROR;
+#if defined(LPUART2)
+  uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
+#else
+  uint32_t periphclk;
+#endif /* LPUART2 */
+
+  /* Check the parameters */
+  assert_param(IS_LPUART_INSTANCE(LPUARTx));
+  assert_param(IS_LL_LPUART_PRESCALER(LPUART_InitStruct->PrescalerValue));
+  assert_param(IS_LL_LPUART_BAUDRATE(LPUART_InitStruct->BaudRate));
+  assert_param(IS_LL_LPUART_DATAWIDTH(LPUART_InitStruct->DataWidth));
+  assert_param(IS_LL_LPUART_STOPBITS(LPUART_InitStruct->StopBits));
+  assert_param(IS_LL_LPUART_PARITY(LPUART_InitStruct->Parity));
+  assert_param(IS_LL_LPUART_DIRECTION(LPUART_InitStruct->TransferDirection));
+  assert_param(IS_LL_LPUART_HWCONTROL(LPUART_InitStruct->HardwareFlowControl));
+
+  /* LPUART needs to be in disabled state, in order to be able to configure some bits in
+     CRx registers. Otherwise (LPUART not in Disabled state) => return ERROR */
+  if (LL_LPUART_IsEnabled(LPUARTx) == 0U)
+  {
+    /*---------------------------- LPUART CR1 Configuration -----------------------
+     * Configure LPUARTx CR1 (LPUART Word Length, Parity and Transfer Direction bits) with parameters:
+     * - DataWidth:          USART_CR1_M bits according to LPUART_InitStruct->DataWidth value
+     * - Parity:             USART_CR1_PCE, USART_CR1_PS bits according to LPUART_InitStruct->Parity value
+     * - TransferDirection:  USART_CR1_TE, USART_CR1_RE bits according to LPUART_InitStruct->TransferDirection value
+     */
+    MODIFY_REG(LPUARTx->CR1,
+               (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE),
+               (LPUART_InitStruct->DataWidth | LPUART_InitStruct->Parity | LPUART_InitStruct->TransferDirection));
+
+    /*---------------------------- LPUART CR2 Configuration -----------------------
+     * Configure LPUARTx CR2 (Stop bits) with parameters:
+     * - Stop Bits:          USART_CR2_STOP bits according to LPUART_InitStruct->StopBits value.
+     */
+    LL_LPUART_SetStopBitsLength(LPUARTx, LPUART_InitStruct->StopBits);
+
+    /*---------------------------- LPUART CR3 Configuration -----------------------
+     * Configure LPUARTx CR3 (Hardware Flow Control) with parameters:
+     * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according
+     *   to LPUART_InitStruct->HardwareFlowControl value.
+     */
+    LL_LPUART_SetHWFlowCtrl(LPUARTx, LPUART_InitStruct->HardwareFlowControl);
+
+    /*---------------------------- LPUART BRR Configuration -----------------------
+     * Retrieve Clock frequency used for LPUART Peripheral
+     */
+#if defined(LPUART2)
+    if (LPUARTx == LPUART1)
+    {
+      periphclk = LL_RCC_GetLPUARTClockFreq(LL_RCC_LPUART1_CLKSOURCE);
+    }
+    else if (LPUARTx == LPUART2)
+    {
+      periphclk = LL_RCC_GetLPUARTClockFreq(LL_RCC_LPUART2_CLKSOURCE);
+    }
+    else
+    {
+      /* Nothing to do, as error code is already assigned to ERROR value */
+    }
+#else
+    periphclk = LL_RCC_GetLPUARTClockFreq(LL_RCC_LPUART1_CLKSOURCE);
+#endif /* LPUART2 */
+
+    /* Configure the LPUART Baud Rate :
+       - prescaler value is required
+       - valid baud rate value (different from 0) is required
+       - Peripheral clock as returned by RCC service, should be valid (different from 0).
+    */
+    if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
+        && (LPUART_InitStruct->BaudRate != 0U))
+    {
+      status = SUCCESS;
+      LL_LPUART_SetBaudRate(LPUARTx,
+                            periphclk,
+                            LPUART_InitStruct->PrescalerValue,
+                            LPUART_InitStruct->BaudRate);
+
+      /* Check BRR is greater than or equal to 0x300 */
+      assert_param(IS_LL_LPUART_BRR_MIN(LPUARTx->BRR));
+
+      /* Check BRR is lower than or equal to 0xFFFFF */
+      assert_param(IS_LL_LPUART_BRR_MAX(LPUARTx->BRR));
+    }
+
+    /*---------------------------- LPUART PRESC Configuration -----------------------
+     * Configure LPUARTx PRESC (Prescaler) with parameters:
+     * - PrescalerValue: LPUART_PRESC_PRESCALER bits according to LPUART_InitStruct->PrescalerValue value.
+     */
+    LL_LPUART_SetPrescaler(LPUARTx, LPUART_InitStruct->PrescalerValue);
+  }
+
+  return (status);
+}
+
+/**
+  * @brief Set each @ref LL_LPUART_InitTypeDef field to default value.
+  * @param LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure
+  *                          whose fields will be set to default values.
+  * @retval None
+  */
+
+void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct)
+{
+  /* Set LPUART_InitStruct fields to default values */
+  LPUART_InitStruct->PrescalerValue      = LL_LPUART_PRESCALER_DIV1;
+  LPUART_InitStruct->BaudRate            = 9600U;
+  LPUART_InitStruct->DataWidth           = LL_LPUART_DATAWIDTH_8B;
+  LPUART_InitStruct->StopBits            = LL_LPUART_STOPBITS_1;
+  LPUART_InitStruct->Parity              = LL_LPUART_PARITY_NONE ;
+  LPUART_InitStruct->TransferDirection   = LL_LPUART_DIRECTION_TX_RX;
+  LPUART_InitStruct->HardwareFlowControl = LL_LPUART_HWCONTROL_NONE;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* LPUART1 || LPUART2 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_pwr.c

@@ -0,0 +1,82 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_ll_pwr.c
+  * @author  MCD Application Team
+  * @brief   PWR LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_ll_pwr.h"
+#include "stm32g0xx_ll_bus.h"
+
+/** @addtogroup STM32G0xx_LL_Driver
+  * @{
+  */
+
+#if defined(PWR)
+
+/** @defgroup PWR_LL PWR
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PWR_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup PWR_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize the PWR registers to their default reset values.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: PWR registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_PWR_DeInit(void)
+{
+  /* Force reset of PWR clock */
+  LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR);
+
+  /* Release reset of PWR clock */
+  LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR);
+
+  return SUCCESS;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* defined(PWR) */
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rng.c

@@ -0,0 +1,145 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_ll_rng.c
+  * @author  MCD Application Team
+  * @brief   RNG LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_ll_rng.h"
+#include "stm32g0xx_ll_bus.h"
+
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32G0xx_LL_Driver
+  * @{
+  */
+
+#if defined (RNG)
+
+/** @addtogroup RNG_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RNG_LL_Private_Macros RNG Private Macros
+  * @{
+  */
+#define IS_LL_RNG_CED(__MODE__) (((__MODE__) == LL_RNG_CED_ENABLE) || \
+                                 ((__MODE__) == LL_RNG_CED_DISABLE))
+
+/**
+  * @}
+  */
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RNG_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup RNG_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize RNG registers (Registers restored to their default values).
+  * @param  RNGx RNG Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RNG registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_RNG_ALL_INSTANCE(RNGx));
+  if (RNGx == RNG)
+  {
+    /* Enable RNG reset state */
+    LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_RNG);
+
+    /* Release RNG from reset state */
+    LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_RNG);
+  }
+  else
+  {
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Initialize RNG registers according to the specified parameters in RNG_InitStruct.
+  * @param  RNGx RNG Instance
+  * @param  RNG_InitStruct pointer to a LL_RNG_InitTypeDef structure
+  *         that contains the configuration information for the specified RNG peripheral.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RNG registers are initialized according to RNG_InitStruct content
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_RNG_ALL_INSTANCE(RNGx));
+  assert_param(IS_LL_RNG_CED(RNG_InitStruct->ClockErrorDetection));
+
+  /* Clock Error Detection configuration */
+  MODIFY_REG(RNGx->CR, RNG_CR_CED, RNG_InitStruct->ClockErrorDetection);
+
+  return (SUCCESS);
+}
+
+/**
+  * @brief Set each @ref LL_RNG_InitTypeDef field to default value.
+  * @param RNG_InitStruct pointer to a @ref LL_RNG_InitTypeDef structure
+  *                       whose fields will be set to default values.
+  * @retval None
+  */
+void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct)
+{
+  /* Set RNG_InitStruct fields to default values */
+  RNG_InitStruct->ClockErrorDetection = LL_RNG_CED_ENABLE;
+
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* RNG */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rtc.c

@@ -0,0 +1,861 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_ll_rtc.c
+  * @author  MCD Application Team
+  * @brief   RTC LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_ll_rtc.h"
+#include "stm32g0xx_ll_cortex.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32G0xx_LL_Driver
+  * @{
+  */
+
+#if defined(RTC)
+
+/** @addtogroup RTC_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup RTC_LL_Private_Constants
+  * @{
+  */
+/* Default values used for prescaler */
+#define RTC_ASYNCH_PRESC_DEFAULT     0x0000007FU
+#define RTC_SYNCH_PRESC_DEFAULT      0x000000FFU
+
+/* Values used for timeout */
+#define RTC_INITMODE_TIMEOUT         1000U /* 1s when tick set to 1ms */
+#define RTC_SYNCHRO_TIMEOUT          1000U /* 1s when tick set to 1ms */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RTC_LL_Private_Macros
+  * @{
+  */
+
+#define IS_LL_RTC_HOURFORMAT(__VALUE__) (((__VALUE__) == LL_RTC_HOURFORMAT_24HOUR) \
+                                      || ((__VALUE__) == LL_RTC_HOURFORMAT_AMPM))
+
+#define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__)   ((__VALUE__) <= 0x7FU)
+
+#define IS_LL_RTC_SYNCH_PREDIV(__VALUE__)    ((__VALUE__) <= 0x7FFFU)
+
+#define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \
+                                  || ((__VALUE__) == LL_RTC_FORMAT_BCD))
+
+#define IS_LL_RTC_TIME_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_TIME_FORMAT_AM_OR_24) \
+                                       || ((__VALUE__) == LL_RTC_TIME_FORMAT_PM))
+
+#define IS_LL_RTC_HOUR12(__HOUR__)            (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))
+#define IS_LL_RTC_HOUR24(__HOUR__)            ((__HOUR__) <= 23U)
+#define IS_LL_RTC_MINUTES(__MINUTES__)        ((__MINUTES__) <= 59U)
+#define IS_LL_RTC_SECONDS(__SECONDS__)        ((__SECONDS__) <= 59U)
+
+#define IS_LL_RTC_WEEKDAY(__VALUE__) (((__VALUE__) == LL_RTC_WEEKDAY_MONDAY) \
+                                   || ((__VALUE__) == LL_RTC_WEEKDAY_TUESDAY) \
+                                   || ((__VALUE__) == LL_RTC_WEEKDAY_WEDNESDAY) \
+                                   || ((__VALUE__) == LL_RTC_WEEKDAY_THURSDAY) \
+                                   || ((__VALUE__) == LL_RTC_WEEKDAY_FRIDAY) \
+                                   || ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \
+                                   || ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY))
+
+#define IS_LL_RTC_DAY(__DAY__)    (((__DAY__) >= 1U) && ((__DAY__) <= 31U))
+
+#define IS_LL_RTC_MONTH(__MONTH__) (((__MONTH__) >= 1U) && ((__MONTH__) <= 12U))
+
+#define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
+
+#define IS_LL_RTC_ALMA_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMA_MASK_NONE) \
+                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_DATEWEEKDAY) \
+                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_HOURS) \
+                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_MINUTES) \
+                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_SECONDS) \
+                                     || ((__VALUE__) == LL_RTC_ALMA_MASK_ALL))
+
+#define IS_LL_RTC_ALMB_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMB_MASK_NONE) \
+                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_DATEWEEKDAY) \
+                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_HOURS) \
+                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_MINUTES) \
+                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_SECONDS) \
+                                     || ((__VALUE__) == LL_RTC_ALMB_MASK_ALL))
+
+
+#define IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) || \
+                                                  ((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY))
+
+#define IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) || \
+                                                  ((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY))
+
+
+/**
+  * @}
+  */
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RTC_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup RTC_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-Initializes the RTC registers to their default reset values.
+  * @note   This function does not reset the RTC Clock source and RTC Backup Data
+  *         registers.
+  * @param  RTCx RTC Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC registers are de-initialized
+  *          - ERROR: RTC registers are not de-initialized
+  */
+ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx)
+{
+  ErrorStatus status = ERROR;
+
+  /* Check the parameter */
+  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+  /* Disable the write protection for RTC registers */
+  LL_RTC_DisableWriteProtection(RTCx);
+
+  /* Set Initialization mode */
+  if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+  {
+    /* Reset TR, DR and CR registers */
+    WRITE_REG(RTCx->TR,       0x00000000U);
+#if defined(RTC_WAKEUP_SUPPORT)
+    WRITE_REG(RTCx->WUTR,     RTC_WUTR_WUT);
+#endif /* RTC_WAKEUP_SUPPORT */
+    WRITE_REG(RTCx->DR  ,     (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
+    /* Reset All CR bits except CR[2:0] */
+#if defined(RTC_WAKEUP_SUPPORT)
+    WRITE_REG(RTCx->CR, (READ_REG(RTCx->CR) & RTC_CR_WUCKSEL));
+#else
+    WRITE_REG(RTCx->CR, 0x00000000U);
+#endif /* RTC_WAKEUP_SUPPORT */
+    WRITE_REG(RTCx->PRER,     (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT));
+    WRITE_REG(RTCx->ALRMAR,   0x00000000U);
+    WRITE_REG(RTCx->ALRMBR,   0x00000000U);
+    WRITE_REG(RTCx->SHIFTR,   0x00000000U);
+    WRITE_REG(RTCx->CALR,     0x00000000U);
+    WRITE_REG(RTCx->ALRMASSR, 0x00000000U);
+    WRITE_REG(RTCx->ALRMBSSR, 0x00000000U);
+
+    /* Exit Initialization mode */
+    LL_RTC_DisableInitMode(RTCx);
+
+    /* Wait till the RTC RSF flag is set */
+    status = LL_RTC_WaitForSynchro(RTCx);
+  }
+
+  /* Enable the write protection for RTC registers */
+  LL_RTC_EnableWriteProtection(RTCx);
+
+  return status;
+}
+
+/**
+  * @brief  Initializes the RTC registers according to the specified parameters
+  *         in RTC_InitStruct.
+  * @param  RTCx RTC Instance
+  * @param  RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure that contains
+  *         the configuration information for the RTC peripheral.
+  * @note   The RTC Prescaler register is write protected and can be written in
+  *         initialization mode only.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC registers are initialized
+  *          - ERROR: RTC registers are not initialized
+  */
+ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
+{
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+  assert_param(IS_LL_RTC_HOURFORMAT(RTC_InitStruct->HourFormat));
+  assert_param(IS_LL_RTC_ASYNCH_PREDIV(RTC_InitStruct->AsynchPrescaler));
+  assert_param(IS_LL_RTC_SYNCH_PREDIV(RTC_InitStruct->SynchPrescaler));
+
+  /* Disable the write protection for RTC registers */
+  LL_RTC_DisableWriteProtection(RTCx);
+
+  /* Set Initialization mode */
+  if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+  {
+    /* Set Hour Format */
+    LL_RTC_SetHourFormat(RTCx, RTC_InitStruct->HourFormat);
+
+    /* Configure Synchronous and Asynchronous prescaler factor */
+    LL_RTC_SetSynchPrescaler(RTCx, RTC_InitStruct->SynchPrescaler);
+    LL_RTC_SetAsynchPrescaler(RTCx, RTC_InitStruct->AsynchPrescaler);
+
+    /* Exit Initialization mode */
+    LL_RTC_DisableInitMode(RTCx);
+
+    status = SUCCESS;
+  }
+  /* Enable the write protection for RTC registers */
+  LL_RTC_EnableWriteProtection(RTCx);
+
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_RTC_InitTypeDef field to default value.
+  * @param  RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct)
+{
+  /* Set RTC_InitStruct fields to default values */
+  RTC_InitStruct->HourFormat      = LL_RTC_HOURFORMAT_24HOUR;
+  RTC_InitStruct->AsynchPrescaler = RTC_ASYNCH_PRESC_DEFAULT;
+  RTC_InitStruct->SynchPrescaler  = RTC_SYNCH_PRESC_DEFAULT;
+}
+
+/**
+  * @brief  Set the RTC current time.
+  * @param  RTCx RTC Instance
+  * @param  RTC_Format This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_FORMAT_BIN
+  *         @arg @ref LL_RTC_FORMAT_BCD
+  * @param  RTC_TimeStruct pointer to a RTC_TimeTypeDef structure that contains
+  *                        the time configuration information for the RTC.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Time register is configured
+  *          - ERROR: RTC Time register is not configured
+  */
+ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
+{
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+  assert_param(IS_LL_RTC_FORMAT(RTC_Format));
+
+  if (RTC_Format == LL_RTC_FORMAT_BIN)
+  {
+    if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+    {
+      assert_param(IS_LL_RTC_HOUR12(RTC_TimeStruct->Hours));
+      assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
+    }
+    else
+    {
+      RTC_TimeStruct->TimeFormat = 0x00U;
+      assert_param(IS_LL_RTC_HOUR24(RTC_TimeStruct->Hours));
+    }
+    assert_param(IS_LL_RTC_MINUTES(RTC_TimeStruct->Minutes));
+    assert_param(IS_LL_RTC_SECONDS(RTC_TimeStruct->Seconds));
+  }
+  else
+  {
+    if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+    {
+      assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
+      assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
+    }
+    else
+    {
+      RTC_TimeStruct->TimeFormat = 0x00U;
+      assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
+    }
+    assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes)));
+    assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds)));
+  }
+
+  /* Disable the write protection for RTC registers */
+  LL_RTC_DisableWriteProtection(RTCx);
+
+  /* Set Initialization mode */
+  if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+  {
+    /* Check the input parameters format */
+    if (RTC_Format != LL_RTC_FORMAT_BIN)
+    {
+      LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, RTC_TimeStruct->Hours,
+                         RTC_TimeStruct->Minutes, RTC_TimeStruct->Seconds);
+    }
+    else
+    {
+      LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Hours),
+                         __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Minutes),
+                         __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Seconds));
+    }
+
+    /* Exit Initialization mode */
+    LL_RTC_DisableInitMode(RTCx);
+
+    /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+    if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
+    {
+      status = LL_RTC_WaitForSynchro(RTCx);
+    }
+    else
+    {
+      status = SUCCESS;
+    }
+  }
+  /* Enable the write protection for RTC registers */
+  LL_RTC_EnableWriteProtection(RTCx);
+
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
+  * @param  RTC_TimeStruct pointer to a @ref LL_RTC_TimeTypeDef structure which will be initialized.
+  * @retval None
+  */
+void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct)
+{
+  /* Time = 00h:00min:00sec */
+  RTC_TimeStruct->TimeFormat = LL_RTC_TIME_FORMAT_AM_OR_24;
+  RTC_TimeStruct->Hours      = 0U;
+  RTC_TimeStruct->Minutes    = 0U;
+  RTC_TimeStruct->Seconds    = 0U;
+}
+
+/**
+  * @brief  Set the RTC current date.
+  * @param  RTCx RTC Instance
+  * @param  RTC_Format This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_FORMAT_BIN
+  *         @arg @ref LL_RTC_FORMAT_BCD
+  * @param  RTC_DateStruct pointer to a RTC_DateTypeDef structure that contains
+  *                         the date configuration information for the RTC.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Day register is configured
+  *          - ERROR: RTC Day register is not configured
+  */
+ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct)
+{
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+  assert_param(IS_LL_RTC_FORMAT(RTC_Format));
+
+  if ((RTC_Format == LL_RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10U) == 0x10U))
+  {
+    RTC_DateStruct->Month = (RTC_DateStruct->Month & (uint8_t)~(0x10U)) + 0x0AU;
+  }
+  if (RTC_Format == LL_RTC_FORMAT_BIN)
+  {
+    assert_param(IS_LL_RTC_YEAR(RTC_DateStruct->Year));
+    assert_param(IS_LL_RTC_MONTH(RTC_DateStruct->Month));
+    assert_param(IS_LL_RTC_DAY(RTC_DateStruct->Day));
+  }
+  else
+  {
+    assert_param(IS_LL_RTC_YEAR(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Year)));
+    assert_param(IS_LL_RTC_MONTH(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Month)));
+    assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Day)));
+  }
+  assert_param(IS_LL_RTC_WEEKDAY(RTC_DateStruct->WeekDay));
+
+  /* Disable the write protection for RTC registers */
+  LL_RTC_DisableWriteProtection(RTCx);
+
+  /* Set Initialization mode */
+  if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+  {
+    /* Check the input parameters format */
+    if (RTC_Format != LL_RTC_FORMAT_BIN)
+    {
+      LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, RTC_DateStruct->Day, RTC_DateStruct->Month, RTC_DateStruct->Year);
+    }
+    else
+    {
+      LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Day),
+                         __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Month), __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Year));
+    }
+
+    /* Exit Initialization mode */
+    LL_RTC_DisableInitMode(RTCx);
+
+    /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+    if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
+    {
+      status = LL_RTC_WaitForSynchro(RTCx);
+    }
+    else
+    {
+      status = SUCCESS;
+    }
+  }
+  /* Enable the write protection for RTC registers */
+  LL_RTC_EnableWriteProtection(RTCx);
+
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)
+  * @param  RTC_DateStruct pointer to a @ref LL_RTC_DateTypeDef structure which will be initialized.
+  * @retval None
+  */
+void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct)
+{
+  /* Monday, January 01 xx00 */
+  RTC_DateStruct->WeekDay = LL_RTC_WEEKDAY_MONDAY;
+  RTC_DateStruct->Day     = 1U;
+  RTC_DateStruct->Month   = LL_RTC_MONTH_JANUARY;
+  RTC_DateStruct->Year    = 0U;
+}
+
+/**
+  * @brief  Set the RTC Alarm A.
+  * @note   The Alarm register can only be written when the corresponding Alarm
+  *         is disabled (Use @ref LL_RTC_ALMA_Disable function).
+  * @param  RTCx RTC Instance
+  * @param  RTC_Format This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_FORMAT_BIN
+  *         @arg @ref LL_RTC_FORMAT_BCD
+  * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
+  *                         contains the alarm configuration parameters.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ALARMA registers are configured
+  *          - ERROR: ALARMA registers are not configured
+  */
+ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+  assert_param(IS_LL_RTC_FORMAT(RTC_Format));
+  assert_param(IS_LL_RTC_ALMA_MASK(RTC_AlarmStruct->AlarmMask));
+  assert_param(IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel));
+
+  if (RTC_Format == LL_RTC_FORMAT_BIN)
+  {
+    if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+    {
+      assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours));
+      assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
+    }
+    else
+    {
+      RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
+      assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
+    }
+    assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
+    assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
+
+    if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
+    {
+      assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay));
+    }
+    else
+    {
+      assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay));
+    }
+  }
+  else
+  {
+    if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+    {
+      assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
+      assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
+    }
+    else
+    {
+      RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
+      assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
+    }
+
+    assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
+    assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
+
+    if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
+    {
+      assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
+    }
+    else
+    {
+      assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
+    }
+  }
+
+  /* Disable the write protection for RTC registers */
+  LL_RTC_DisableWriteProtection(RTCx);
+
+  /* Select weekday selection */
+  if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
+  {
+    /* Set the date for ALARM */
+    LL_RTC_ALMA_DisableWeekday(RTCx);
+    if (RTC_Format != LL_RTC_FORMAT_BIN)
+    {
+      LL_RTC_ALMA_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
+    }
+    else
+    {
+      LL_RTC_ALMA_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay));
+    }
+  }
+  else
+  {
+    /* Set the week day for ALARM */
+    LL_RTC_ALMA_EnableWeekday(RTCx);
+    LL_RTC_ALMA_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
+  }
+
+  /* Configure the Alarm register */
+  if (RTC_Format != LL_RTC_FORMAT_BIN)
+  {
+    LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours,
+                           RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds);
+  }
+  else
+  {
+    LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat,
+                           __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours),
+                           __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes),
+                           __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds));
+  }
+  /* Set ALARM mask */
+  LL_RTC_ALMA_SetMask(RTCx, RTC_AlarmStruct->AlarmMask);
+
+  /* Enable the write protection for RTC registers */
+  LL_RTC_EnableWriteProtection(RTCx);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Set the RTC Alarm B.
+  * @note   The Alarm register can only be written when the corresponding Alarm
+  *         is disabled (@ref LL_RTC_ALMB_Disable function).
+  * @param  RTCx RTC Instance
+  * @param  RTC_Format This parameter can be one of the following values:
+  *         @arg @ref LL_RTC_FORMAT_BIN
+  *         @arg @ref LL_RTC_FORMAT_BCD
+  * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
+  *                         contains the alarm configuration parameters.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ALARMB registers are configured
+  *          - ERROR: ALARMB registers are not configured
+  */
+ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+  assert_param(IS_LL_RTC_FORMAT(RTC_Format));
+  assert_param(IS_LL_RTC_ALMB_MASK(RTC_AlarmStruct->AlarmMask));
+  assert_param(IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel));
+
+  if (RTC_Format == LL_RTC_FORMAT_BIN)
+  {
+    if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+    {
+      assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours));
+      assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
+    }
+    else
+    {
+      RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
+      assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
+    }
+    assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
+    assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
+
+    if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
+    {
+      assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay));
+    }
+    else
+    {
+      assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay));
+    }
+  }
+  else
+  {
+    if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
+    {
+      assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
+      assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
+    }
+    else
+    {
+      RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
+      assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
+    }
+
+    assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
+    assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
+
+    if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
+    {
+      assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
+    }
+    else
+    {
+      assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
+    }
+  }
+
+  /* Disable the write protection for RTC registers */
+  LL_RTC_DisableWriteProtection(RTCx);
+
+  /* Select weekday selection */
+  if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
+  {
+    /* Set the date for ALARM */
+    LL_RTC_ALMB_DisableWeekday(RTCx);
+    if (RTC_Format != LL_RTC_FORMAT_BIN)
+    {
+      LL_RTC_ALMB_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
+    }
+    else
+    {
+      LL_RTC_ALMB_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay));
+    }
+  }
+  else
+  {
+    /* Set the week day for ALARM */
+    LL_RTC_ALMB_EnableWeekday(RTCx);
+    LL_RTC_ALMB_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
+  }
+
+  /* Configure the Alarm register */
+  if (RTC_Format != LL_RTC_FORMAT_BIN)
+  {
+    LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours,
+                           RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds);
+  }
+  else
+  {
+    LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat,
+                           __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours),
+                           __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes),
+                           __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds));
+  }
+  /* Set ALARM mask */
+  LL_RTC_ALMB_SetMask(RTCx, RTC_AlarmStruct->AlarmMask);
+
+  /* Enable the write protection for RTC registers */
+  LL_RTC_EnableWriteProtection(RTCx);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec /
+  *         Day = 1st day of the month/Mask = all fields are masked).
+  * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
+  * @retval None
+  */
+void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
+{
+  /* Alarm Time Settings : Time = 00h:00mn:00sec */
+  RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMA_TIME_FORMAT_AM;
+  RTC_AlarmStruct->AlarmTime.Hours      = 0U;
+  RTC_AlarmStruct->AlarmTime.Minutes    = 0U;
+  RTC_AlarmStruct->AlarmTime.Seconds    = 0U;
+
+  /* Alarm Day Settings : Day = 1st day of the month */
+  RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMA_DATEWEEKDAYSEL_DATE;
+  RTC_AlarmStruct->AlarmDateWeekDay    = 1U;
+
+  /* Alarm Masks Settings : Mask =  all fields are not masked */
+  RTC_AlarmStruct->AlarmMask           = LL_RTC_ALMA_MASK_NONE;
+}
+
+/**
+  * @brief  Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec /
+  *         Day = 1st day of the month/Mask = all fields are masked).
+  * @param  RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
+  * @retval None
+  */
+void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
+{
+  /* Alarm Time Settings : Time = 00h:00mn:00sec */
+  RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMB_TIME_FORMAT_AM;
+  RTC_AlarmStruct->AlarmTime.Hours      = 0U;
+  RTC_AlarmStruct->AlarmTime.Minutes    = 0U;
+  RTC_AlarmStruct->AlarmTime.Seconds    = 0U;
+
+  /* Alarm Day Settings : Day = 1st day of the month */
+  RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMB_DATEWEEKDAYSEL_DATE;
+  RTC_AlarmStruct->AlarmDateWeekDay    = 1U;
+
+  /* Alarm Masks Settings : Mask =  all fields are not masked */
+  RTC_AlarmStruct->AlarmMask           = LL_RTC_ALMB_MASK_NONE;
+}
+
+/**
+  * @brief  Enters the RTC Initialization mode.
+  * @note   The RTC Initialization mode is write protected, use the
+  *         @ref LL_RTC_DisableWriteProtection before calling this function.
+  * @param  RTCx RTC Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC is in Init mode
+  *          - ERROR: RTC is not in Init mode
+  */
+ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx)
+{
+  __IO uint32_t timeout = RTC_INITMODE_TIMEOUT;
+  ErrorStatus status = SUCCESS;
+  uint32_t tmp;
+
+  /* Check the parameter */
+  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+  /* Check if the Initialization mode is set */
+  if (LL_RTC_IsActiveFlag_INIT(RTCx) == 0U)
+  {
+    /* Set the Initialization mode */
+    LL_RTC_EnableInitMode(RTCx);
+
+    /* Wait till RTC is in INIT state and if Time out is reached exit */
+    tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
+    while ((timeout != 0U) && (tmp != 1U))
+    {
+      if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
+      {
+        timeout --;
+      }
+      tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
+      if (timeout == 0U)
+      {
+        status = ERROR;
+      }
+    }
+  }
+  return status;
+}
+
+/**
+  * @brief  Exit the RTC Initialization mode.
+  * @note   When the initialization sequence is complete, the calendar restarts
+  *         counting after 4 RTCCLK cycles.
+  * @note   The RTC Initialization mode is write protected, use the
+  *         @ref LL_RTC_DisableWriteProtection before calling this function.
+  * @param  RTCx RTC Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC exited from in Init mode
+  *          - ERROR: Not applicable
+  */
+ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx)
+{
+  /* Check the parameter */
+  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+  /* Disable initialization mode */
+  LL_RTC_DisableInitMode(RTCx);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are
+  *         synchronized with RTC APB clock.
+  * @note   The RTC Resynchronization mode is write protected, use the
+  *         @ref LL_RTC_DisableWriteProtection before calling this function.
+  * @note   To read the calendar through the shadow registers after Calendar
+  *         initialization, calendar update or after wakeup from low power modes
+  *         the software must first clear the RSF flag.
+  *         The software must then wait until it is set again before reading
+  *         the calendar, which means that the calendar registers have been
+  *         correctly copied into the RTC_TR and RTC_DR shadow registers.
+  * @param  RTCx RTC Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC registers are synchronised
+  *          - ERROR: RTC registers are not synchronised
+  */
+ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx)
+{
+  __IO uint32_t timeout = RTC_SYNCHRO_TIMEOUT;
+  ErrorStatus status = SUCCESS;
+  uint32_t tmp;
+
+  /* Check the parameter */
+  assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+  /* Clear RSF flag */
+  LL_RTC_ClearFlag_RS(RTCx);
+
+  /* Wait the registers to be synchronised */
+  tmp = LL_RTC_IsActiveFlag_RS(RTCx);
+  while ((timeout != 0U) && (tmp != 0U))
+  {
+    if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
+    {
+      timeout--;
+    }
+    tmp = LL_RTC_IsActiveFlag_RS(RTCx);
+    if (timeout == 0U)
+    {
+      status = ERROR;
+    }
+  }
+
+  if (status != ERROR)
+  {
+    timeout = RTC_SYNCHRO_TIMEOUT;
+    tmp = LL_RTC_IsActiveFlag_RS(RTCx);
+    while ((timeout != 0U) && (tmp != 1U))
+    {
+      if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
+      {
+        timeout--;
+      }
+      tmp = LL_RTC_IsActiveFlag_RS(RTCx);
+      if (timeout == 0U)
+      {
+        status = ERROR;
+      }
+    }
+  }
+
+  return (status);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(RTC) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_spi.c

@@ -0,0 +1,547 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_ll_spi.c
+  * @author  MCD Application Team
+  * @brief   SPI LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_ll_spi.h"
+#include "stm32g0xx_ll_bus.h"
+#include "stm32g0xx_ll_rcc.h"
+
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32G0xx_LL_Driver
+  * @{
+  */
+
+#if defined (SPI1) || defined (SPI2) || defined (SPI3)
+
+/** @addtogroup SPI_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SPI_LL_Private_Constants SPI Private Constants
+  * @{
+  */
+/* SPI registers Masks */
+#define SPI_CR1_CLEAR_MASK                 (SPI_CR1_CPHA    | SPI_CR1_CPOL     | SPI_CR1_MSTR   | \
+                                            SPI_CR1_BR      | SPI_CR1_LSBFIRST | SPI_CR1_SSI    | \
+                                            SPI_CR1_SSM     | SPI_CR1_RXONLY   | SPI_CR1_CRCL   | \
+                                            SPI_CR1_CRCNEXT | SPI_CR1_CRCEN    | SPI_CR1_BIDIOE | \
+                                            SPI_CR1_BIDIMODE)
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SPI_LL_Private_Macros SPI Private Macros
+  * @{
+  */
+#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX)       \
+                                                 || ((__VALUE__) == LL_SPI_SIMPLEX_RX)     \
+                                                 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
+                                                 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
+
+#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
+                                   || ((__VALUE__) == LL_SPI_MODE_SLAVE))
+
+#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT)     \
+                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT)  \
+                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT)  \
+                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT)  \
+                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT)  \
+                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT)  \
+                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
+                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
+                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
+                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
+                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
+                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
+                                        || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
+
+#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
+                                       || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
+
+#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
+                                    || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
+
+#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT)          \
+                                  || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
+                                  || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
+
+#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2)      \
+                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4)   \
+                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8)   \
+                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16)  \
+                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32)  \
+                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64)  \
+                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
+                                       || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
+
+#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
+                                       || ((__VALUE__) == LL_SPI_MSB_FIRST))
+
+#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
+                                             || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
+
+#define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPI_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup SPI_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize the SPI registers to their default reset values.
+  * @param  SPIx SPI Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: SPI registers are de-initialized
+  *          - ERROR: SPI registers are not de-initialized
+  */
+ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
+{
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_INSTANCE(SPIx));
+
+#if defined(SPI1)
+  if (SPIx == SPI1)
+  {
+    /* Force reset of SPI clock */
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
+
+    /* Release reset of SPI clock */
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
+
+    status = SUCCESS;
+  }
+#endif /* SPI1 */
+#if defined(SPI2)
+  if (SPIx == SPI2)
+  {
+    /* Force reset of SPI clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
+
+    /* Release reset of SPI clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
+
+    status = SUCCESS;
+  }
+#endif /* SPI2 */
+#if defined(SPI3)
+  if (SPIx == SPI3)
+  {
+    /* Force reset of SPI clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
+
+    /* Release reset of SPI clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
+
+    status = SUCCESS;
+  }
+#endif /* SPI3 */
+
+  return status;
+}
+
+/**
+  * @brief  Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
+  * @note   As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
+  *         SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+  * @param  SPIx SPI Instance
+  * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
+  * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
+  */
+ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
+{
+  ErrorStatus status = ERROR;
+
+  /* Check the SPI Instance SPIx*/
+  assert_param(IS_SPI_ALL_INSTANCE(SPIx));
+
+  /* Check the SPI parameters from SPI_InitStruct*/
+  assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
+  assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
+  assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
+  assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
+  assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
+  assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
+  assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
+  assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
+  assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
+
+  if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
+  {
+    /*---------------------------- SPIx CR1 Configuration ------------------------
+     * Configure SPIx CR1 with parameters:
+     * - TransferDirection:  SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
+     * - Master/Slave Mode:  SPI_CR1_MSTR bit
+     * - ClockPolarity:      SPI_CR1_CPOL bit
+     * - ClockPhase:         SPI_CR1_CPHA bit
+     * - NSS management:     SPI_CR1_SSM bit
+     * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
+     * - BitOrder:           SPI_CR1_LSBFIRST bit
+     * - CRCCalculation:     SPI_CR1_CRCEN bit
+     */
+    MODIFY_REG(SPIx->CR1,
+               SPI_CR1_CLEAR_MASK,
+               SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode |
+               SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
+               SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
+               SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
+
+    /*---------------------------- SPIx CR2 Configuration ------------------------
+     * Configure SPIx CR2 with parameters:
+     * - DataWidth:          DS[3:0] bits
+     * - NSS management:     SSOE bit
+     */
+    MODIFY_REG(SPIx->CR2,
+               SPI_CR2_DS | SPI_CR2_SSOE,
+               SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U));
+
+    /* Set Rx FIFO to Quarter (1 Byte) in case of 8 Bits mode. No DataPacking by default */
+    if (SPI_InitStruct->DataWidth < LL_SPI_DATAWIDTH_9BIT)
+    {
+      LL_SPI_SetRxFIFOThreshold(SPIx, LL_SPI_RX_FIFO_TH_QUARTER);
+    }
+
+    /*---------------------------- SPIx CRCPR Configuration ----------------------
+     * Configure SPIx CRCPR with parameters:
+     * - CRCPoly:            CRCPOLY[15:0] bits
+     */
+    if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
+    {
+      assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
+      LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
+    }
+    status = SUCCESS;
+  }
+
+#if defined (SPI_I2S_SUPPORT)
+  /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
+  CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
+#endif /* SPI_I2S_SUPPORT */
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_SPI_InitTypeDef field to default value.
+  * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
+  * whose fields will be set to default values.
+  * @retval None
+  */
+void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
+{
+  /* Set SPI_InitStruct fields to default values */
+  SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
+  SPI_InitStruct->Mode              = LL_SPI_MODE_SLAVE;
+  SPI_InitStruct->DataWidth         = LL_SPI_DATAWIDTH_8BIT;
+  SPI_InitStruct->ClockPolarity     = LL_SPI_POLARITY_LOW;
+  SPI_InitStruct->ClockPhase        = LL_SPI_PHASE_1EDGE;
+  SPI_InitStruct->NSS               = LL_SPI_NSS_HARD_INPUT;
+  SPI_InitStruct->BaudRate          = LL_SPI_BAUDRATEPRESCALER_DIV2;
+  SPI_InitStruct->BitOrder          = LL_SPI_MSB_FIRST;
+  SPI_InitStruct->CRCCalculation    = LL_SPI_CRCCALCULATION_DISABLE;
+  SPI_InitStruct->CRCPoly           = 7U;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#if defined(SPI_I2S_SUPPORT)
+/** @addtogroup I2S_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2S_LL_Private_Constants I2S Private Constants
+  * @{
+  */
+/* I2S registers Masks */
+#define I2S_I2SCFGR_CLEAR_MASK             (SPI_I2SCFGR_CHLEN   | SPI_I2SCFGR_DATLEN | \
+                                            SPI_I2SCFGR_CKPOL   | SPI_I2SCFGR_I2SSTD | \
+                                            SPI_I2SCFGR_I2SCFG  | SPI_I2SCFGR_I2SMOD )
+
+#define I2S_I2SPR_CLEAR_MASK               0x0002U
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2S_LL_Private_Macros I2S Private Macros
+  * @{
+  */
+
+#define IS_LL_I2S_DATAFORMAT(__VALUE__)  (((__VALUE__) == LL_I2S_DATAFORMAT_16B)             \
+                                          || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
+                                          || ((__VALUE__) == LL_I2S_DATAFORMAT_24B)          \
+                                          || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
+
+#define IS_LL_I2S_CPOL(__VALUE__)        (((__VALUE__) == LL_I2S_POLARITY_LOW)  \
+                                          || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
+
+#define IS_LL_I2S_STANDARD(__VALUE__)    (((__VALUE__) == LL_I2S_STANDARD_PHILIPS)      \
+                                          || ((__VALUE__) == LL_I2S_STANDARD_MSB)       \
+                                          || ((__VALUE__) == LL_I2S_STANDARD_LSB)       \
+                                          || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
+                                          || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
+
+#define IS_LL_I2S_MODE(__VALUE__)        (((__VALUE__) == LL_I2S_MODE_SLAVE_TX)     \
+                                          || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX)  \
+                                          || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
+                                          || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
+
+#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
+                                          || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
+
+#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K)       \
+                                          && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
+                                         || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
+
+#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__)  ((__VALUE__) >= 0x2U)
+
+#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
+                                               || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2S_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup I2S_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize the SPI/I2S registers to their default reset values.
+  * @param  SPIx SPI Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: SPI registers are de-initialized
+  *          - ERROR: SPI registers are not de-initialized
+  */
+ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
+{
+  return LL_SPI_DeInit(SPIx);
+}
+
+/**
+  * @brief  Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
+  * @note   As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
+  *         SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+  * @param  SPIx SPI Instance
+  * @param  I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: SPI registers are Initialized
+  *          - ERROR: SPI registers are not Initialized
+  */
+ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
+{
+  uint32_t i2sdiv = 2U;
+  uint32_t i2sodd = 0U;
+  uint32_t packetlength = 1U;
+  uint32_t tmp;
+  LL_RCC_ClocksTypeDef rcc_clocks;
+  uint32_t sourceclock;
+  ErrorStatus status = ERROR;
+
+  /* Check the I2S parameters */
+  assert_param(IS_I2S_ALL_INSTANCE(SPIx));
+  assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
+  assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
+  assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
+  assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
+  assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
+  assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
+
+  if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
+  {
+    /*---------------------------- SPIx I2SCFGR Configuration --------------------
+     * Configure SPIx I2SCFGR with parameters:
+     * - Mode:          SPI_I2SCFGR_I2SCFG[1:0] bit
+     * - Standard:      SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
+     * - DataFormat:    SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
+     * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
+     */
+
+    /* Write to SPIx I2SCFGR */
+    MODIFY_REG(SPIx->I2SCFGR,
+               I2S_I2SCFGR_CLEAR_MASK,
+               I2S_InitStruct->Mode | I2S_InitStruct->Standard |
+               I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
+               SPI_I2SCFGR_I2SMOD);
+
+    /*---------------------------- SPIx I2SPR Configuration ----------------------
+     * Configure SPIx I2SPR with parameters:
+     * - MCLKOutput:    SPI_I2SPR_MCKOE bit
+     * - AudioFreq:     SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
+     */
+
+    /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
+     * else, default values are used:  i2sodd = 0U, i2sdiv = 2U.
+     */
+    if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
+    {
+      /* Check the frame length (For the Prescaler computing)
+       * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
+       */
+      if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
+      {
+        /* Packet length is 32 bits */
+        packetlength = 2U;
+      }
+
+      /* I2S Clock source is System clock: Get System Clock frequency */
+      LL_RCC_GetSystemClocksFreq(&rcc_clocks);
+
+      /* Get the source clock value: based on System Clock value */
+      sourceclock = rcc_clocks.SYSCLK_Frequency;
+
+      /* Compute the Real divider depending on the MCLK output state with a floating point */
+      if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
+      {
+        /* MCLK output is enabled */
+        tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
+      }
+      else
+      {
+        /* MCLK output is disabled */
+        tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
+      }
+
+      /* Remove the floating point */
+      tmp = tmp / 10U;
+
+      /* Check the parity of the divider */
+      i2sodd = (tmp & (uint16_t)0x0001U);
+
+      /* Compute the i2sdiv prescaler */
+      i2sdiv = ((tmp - i2sodd) / 2U);
+
+      /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
+      i2sodd = (i2sodd << 8U);
+    }
+
+    /* Test if the divider is 1 or 0 or greater than 0xFF */
+    if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
+    {
+      /* Set the default values */
+      i2sdiv = 2U;
+      i2sodd = 0U;
+    }
+
+    /* Write to SPIx I2SPR register the computed value */
+    WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
+
+    status = SUCCESS;
+  }
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_I2S_InitTypeDef field to default value.
+  * @param  I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
+  *         whose fields will be set to default values.
+  * @retval None
+  */
+void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
+{
+  /*--------------- Reset I2S init structure parameters values -----------------*/
+  I2S_InitStruct->Mode              = LL_I2S_MODE_SLAVE_TX;
+  I2S_InitStruct->Standard          = LL_I2S_STANDARD_PHILIPS;
+  I2S_InitStruct->DataFormat        = LL_I2S_DATAFORMAT_16B;
+  I2S_InitStruct->MCLKOutput        = LL_I2S_MCLK_OUTPUT_DISABLE;
+  I2S_InitStruct->AudioFreq         = LL_I2S_AUDIOFREQ_DEFAULT;
+  I2S_InitStruct->ClockPolarity     = LL_I2S_POLARITY_LOW;
+}
+
+/**
+  * @brief  Set linear and parity prescaler.
+  * @note   To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
+  *         Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
+  * @param  SPIx SPI Instance
+  * @param  PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF.
+  * @param  PrescalerParity This parameter can be one of the following values:
+  *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
+  *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
+  * @retval None
+  */
+void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
+{
+  /* Check the I2S parameters */
+  assert_param(IS_I2S_ALL_INSTANCE(SPIx));
+  assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
+  assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
+
+  /* Write to SPIx I2SPR */
+  MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* SPI_I2S_SUPPORT */
+
+#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_ucpd.c

@@ -0,0 +1,186 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_ll_ucpd.c
+  * @author  MCD Application Team
+  * @brief   UCPD LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_ll_ucpd.h"
+#include "stm32g0xx_ll_bus.h"
+#include "stm32g0xx_ll_rcc.h"
+
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32G0xx_LL_Driver
+  * @{
+  */
+#if defined (UCPD1) || defined (UCPD2)
+/** @addtogroup UCPD_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup UCPD_LL_Private_Constants UCPD Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UCPD_LL_Private_Macros UCPD Private Macros
+  * @{
+  */
+
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UCPD_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup UCPD_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize the UCPD registers to their default reset values.
+  * @param  UCPDx ucpd Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ucpd registers are de-initialized
+  *          - ERROR: ucpd registers are not de-initialized
+  */
+ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx)
+{
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_UCPD_ALL_INSTANCE(UCPDx));
+
+  LL_UCPD_Disable(UCPDx);
+
+  if (UCPD1 == UCPDx)
+  {
+    /* Force reset of ucpd clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UCPD1);
+
+    /* Release reset of ucpd clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UCPD1);
+
+    /* Disable ucpd clock */
+    LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_UCPD1);
+
+    status = SUCCESS;
+  }
+  if (UCPD2 == UCPDx)
+  {
+    /* Force reset of ucpd clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UCPD2);
+
+    /* Release reset of ucpd clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UCPD2);
+
+    /* Disable ucpd clock */
+    LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_UCPD2);
+
+    status = SUCCESS;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Initialize the ucpd registers according to the specified parameters in UCPD_InitStruct.
+  * @note   As some bits in ucpd configuration registers can only be written when the ucpd is disabled
+  *         (ucpd_CR1_SPE bit =0), UCPD peripheral should be in disabled state prior calling this function.
+  *         Otherwise, ERROR result will be returned.
+  * @param  UCPDx UCPD Instance
+  * @param  UCPD_InitStruct pointer to a @ref LL_UCPD_InitTypeDef structure that contains
+  *         the configuration information for the UCPD peripheral.
+  * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
+  */
+ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStruct)
+{
+  /* Check the ucpd Instance UCPDx*/
+  assert_param(IS_UCPD_ALL_INSTANCE(UCPDx));
+
+  if (UCPD1 == UCPDx)
+  {
+    LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_UCPD1);
+  }
+
+  if (UCPD2 == UCPDx)
+  {
+    LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_UCPD2);
+  }
+
+  LL_UCPD_Disable(UCPDx);
+
+  /*---------------------------- UCPDx CFG1 Configuration ------------------------*/
+  MODIFY_REG(UCPDx->CFG1,
+             UCPD_CFG1_PSC_UCPDCLK | UCPD_CFG1_TRANSWIN | UCPD_CFG1_IFRGAP | UCPD_CFG1_HBITCLKDIV,
+             UCPD_InitStruct->psc_ucpdclk | (UCPD_InitStruct->transwin  << UCPD_CFG1_TRANSWIN_Pos) |
+             (UCPD_InitStruct->IfrGap << UCPD_CFG1_IFRGAP_Pos) | UCPD_InitStruct->HbitClockDiv);
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Set each @ref LL_UCPD_InitTypeDef field to default value.
+  * @param  UCPD_InitStruct pointer to a @ref LL_UCPD_InitTypeDef structure
+  *         whose fields will be set to default values.
+  * @retval None
+  */
+void LL_UCPD_StructInit(LL_UCPD_InitTypeDef *UCPD_InitStruct)
+{
+  /* Set UCPD_InitStruct fields to default values */
+  UCPD_InitStruct->psc_ucpdclk  = LL_UCPD_PSC_DIV2;
+  UCPD_InitStruct->transwin     = 0x7;   /* Divide by 8                     */
+  UCPD_InitStruct->IfrGap       = 0x10;  /* Divide by 17                    */
+  UCPD_InitStruct->HbitClockDiv = 0x0D;  /* Divide by 14 to produce HBITCLK */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* defined (UCPD1) || defined (UCPD2) */
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_usart.c

@@ -0,0 +1,468 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_ll_usart.c
+  * @author  MCD Application Team
+  * @brief   USART LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_ll_usart.h"
+#include "stm32g0xx_ll_rcc.h"
+#include "stm32g0xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32G0xx_LL_Driver
+  * @{
+  */
+
+#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART4) || defined (USART5) || defined (USART6)
+
+/** @addtogroup USART_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup USART_LL_Private_Macros
+  * @{
+  */
+
+#define IS_LL_USART_PRESCALER(__VALUE__)  (((__VALUE__) == LL_USART_PRESCALER_DIV1) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV2) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV4) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV6) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV8) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV10) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV12) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV16) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV32) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV64) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV128) \
+                                           || ((__VALUE__) == LL_USART_PRESCALER_DIV256))
+
+/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
+ *              divided by the smallest oversampling used on the USART (i.e. 8)    */
+#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 8000000U)
+
+/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
+#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
+
+#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
+                                          || ((__VALUE__) == LL_USART_DIRECTION_RX) \
+                                          || ((__VALUE__) == LL_USART_DIRECTION_TX) \
+                                          || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
+
+#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
+                                       || ((__VALUE__) == LL_USART_PARITY_EVEN) \
+                                       || ((__VALUE__) == LL_USART_PARITY_ODD))
+
+#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
+                                          || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
+                                          || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
+
+#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
+                                             || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
+
+#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
+                                                 || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
+
+#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
+                                           || ((__VALUE__) == LL_USART_PHASE_2EDGE))
+
+#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
+                                              || ((__VALUE__) == LL_USART_POLARITY_HIGH))
+
+#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
+                                            || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
+
+#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
+                                         || ((__VALUE__) == LL_USART_STOPBITS_1) \
+                                         || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
+                                         || ((__VALUE__) == LL_USART_STOPBITS_2))
+
+#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
+                                          || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
+                                          || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
+                                          || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
+
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup USART_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup USART_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize USART registers (Registers restored to their default values).
+  * @param  USARTx USART Instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: USART registers are de-initialized
+  *          - ERROR: USART registers are not de-initialized
+  */
+ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_UART_INSTANCE(USARTx));
+
+  if (USARTx == USART1)
+  {
+    /* Force reset of USART clock */
+    LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
+
+    /* Release reset of USART clock */
+    LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
+  }
+  else if (USARTx == USART2)
+  {
+    /* Force reset of USART clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
+
+    /* Release reset of USART clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
+  }
+#if defined(USART3)
+  else if (USARTx == USART3)
+  {
+    /* Force reset of USART clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
+
+    /* Release reset of USART clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
+  }
+#endif /* USART3 */
+#if defined(USART4)
+  else if (USARTx == USART4)
+  {
+    /* Force reset of USART clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART4);
+
+    /* Release reset of USART clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART4);
+  }
+#endif /* USART4 */
+#if defined(USART5)
+  else if (USARTx == USART5)
+  {
+    /* Force reset of USART clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART5);
+
+    /* Release reset of USART clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART5);
+  }
+#endif /* USART5 */
+#if defined(USART6)
+  else if (USARTx == USART6)
+  {
+    /* Force reset of USART clock */
+    LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART6);
+
+    /* Release reset of USART clock */
+    LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART6);
+  }
+#endif /* USART6 */
+  else
+  {
+    status = ERROR;
+  }
+
+  return (status);
+}
+
+/**
+  * @brief  Initialize USART registers according to the specified
+  *         parameters in USART_InitStruct.
+  * @note   As some bits in USART configuration registers can only be written when
+  *         the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling
+  *         this function. Otherwise, ERROR result will be returned.
+  * @note   Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
+  * @param  USARTx USART Instance
+  * @param  USART_InitStruct pointer to a LL_USART_InitTypeDef structure
+  *         that contains the configuration information for the specified USART peripheral.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: USART registers are initialized according to USART_InitStruct content
+  *          - ERROR: Problem occurred during USART Registers initialization
+  */
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct)
+{
+  ErrorStatus status = ERROR;
+  uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
+#if !defined(RCC_CCIPR_USART3SEL)&&!defined(RCC_CCIPR_USART4SEL)||(!defined(RCC_CCIPR_USART2SEL))||!defined(RCC_CCIPR_USART5SEL)||!defined(RCC_CCIPR_USART6SEL)
+  LL_RCC_ClocksTypeDef RCC_Clocks;
+#endif /* USART clock selection flags */
+
+  /* Check the parameters */
+  assert_param(IS_UART_INSTANCE(USARTx));
+  assert_param(IS_LL_USART_PRESCALER(USART_InitStruct->PrescalerValue));
+  assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
+  assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
+  assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
+  assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
+  assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
+  assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
+  assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
+
+  /* USART needs to be in disabled state, in order to be able to configure some bits in
+     CRx registers */
+  if (LL_USART_IsEnabled(USARTx) == 0U)
+  {
+    /*---------------------------- USART CR1 Configuration ---------------------
+     * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
+     * - DataWidth:          USART_CR1_M bits according to USART_InitStruct->DataWidth value
+     * - Parity:             USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
+     * - TransferDirection:  USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
+     * - Oversampling:       USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
+     */
+    MODIFY_REG(USARTx->CR1,
+               (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
+                USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
+               (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
+                USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
+
+    /*---------------------------- USART CR2 Configuration ---------------------
+     * Configure USARTx CR2 (Stop bits) with parameters:
+     * - Stop Bits:          USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
+     * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
+     */
+    LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
+
+    /*---------------------------- USART CR3 Configuration ---------------------
+     * Configure USARTx CR3 (Hardware Flow Control) with parameters:
+     * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to
+     *   USART_InitStruct->HardwareFlowControl value.
+     */
+    LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
+
+    /*---------------------------- USART BRR Configuration ---------------------
+     * Retrieve Clock frequency used for USART Peripheral
+     */
+    if (USARTx == USART1)
+    {
+      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE);
+    }
+    else if (USARTx == USART2)
+    {
+#if defined(RCC_CCIPR_USART2SEL)
+      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE);
+#else
+      /* USART2 clock is PCLK */
+      LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
+      periphclk = RCC_Clocks.PCLK1_Frequency;
+#endif /* USART2 Clock selector flag */
+    }
+#if defined(USART3)
+    else if (USARTx == USART3)
+    {
+#if defined(RCC_CCIPR_USART3SEL)
+      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART3_CLKSOURCE);
+#else
+      /* USART3 clock is PCLK */
+      LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
+      periphclk = RCC_Clocks.PCLK1_Frequency;
+#endif /* USART3 Clock selector flag */
+    }
+#endif /* USART3 */
+#if defined(USART4)
+    else if (USARTx == USART4)
+    {
+#if defined(RCC_CCIPR_USART4SEL)
+      periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART4_CLKSOURCE);
+#else
+      /* USART4 clock is PCLK1 */
+      LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
+      periphclk = RCC_Clocks.PCLK1_Frequency;
+#endif /* RCC_CCIPR_USART4SEL */
+    }
+#endif /* USART4 */
+#if defined(USART5)
+    else if (USARTx == USART5)
+    {
+      /* USART5 clock is PCLK1 */
+      LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
+      periphclk = RCC_Clocks.PCLK1_Frequency;
+    }
+#endif /* USART5 */
+#if defined(USART6)
+    else if (USARTx == USART6)
+    {
+      /* USART6 clock is PCLK1 */
+      LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
+      periphclk = RCC_Clocks.PCLK1_Frequency;
+    }
+#endif /* USART6 */
+    else
+    {
+      /* Nothing to do, as error code is already assigned to ERROR value */
+    }
+
+    /* Configure the USART Baud Rate :
+       - prescaler value is required
+       - valid baud rate value (different from 0) is required
+       - Peripheral clock as returned by RCC service, should be valid (different from 0).
+    */
+    if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
+        && (USART_InitStruct->BaudRate != 0U))
+    {
+      status = SUCCESS;
+      LL_USART_SetBaudRate(USARTx,
+                           periphclk,
+                           USART_InitStruct->PrescalerValue,
+                           USART_InitStruct->OverSampling,
+                           USART_InitStruct->BaudRate);
+
+      /* Check BRR is greater than or equal to 16d */
+      assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
+    }
+
+    /*---------------------------- USART PRESC Configuration -----------------------
+     * Configure USARTx PRESC (Prescaler) with parameters:
+     * - PrescalerValue: USART_PRESC_PRESCALER bits according to USART_InitStruct->PrescalerValue value.
+     */
+    LL_USART_SetPrescaler(USARTx, USART_InitStruct->PrescalerValue);
+  }
+  /* Endif (=> USART not in Disabled state => return ERROR) */
+
+  return (status);
+}
+
+/**
+  * @brief Set each @ref LL_USART_InitTypeDef field to default value.
+  * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
+  *                         whose fields will be set to default values.
+  * @retval None
+  */
+
+void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
+{
+  /* Set USART_InitStruct fields to default values */
+  USART_InitStruct->PrescalerValue      = LL_USART_PRESCALER_DIV1;
+  USART_InitStruct->BaudRate            = 9600U;
+  USART_InitStruct->DataWidth           = LL_USART_DATAWIDTH_8B;
+  USART_InitStruct->StopBits            = LL_USART_STOPBITS_1;
+  USART_InitStruct->Parity              = LL_USART_PARITY_NONE ;
+  USART_InitStruct->TransferDirection   = LL_USART_DIRECTION_TX_RX;
+  USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
+  USART_InitStruct->OverSampling        = LL_USART_OVERSAMPLING_16;
+}
+
+/**
+  * @brief  Initialize USART Clock related settings according to the
+  *         specified parameters in the USART_ClockInitStruct.
+  * @note   As some bits in USART configuration registers can only be written when
+  *         the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling
+  *         this function. Otherwise, ERROR result will be returned.
+  * @param  USARTx USART Instance
+  * @param  USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
+  *         that contains the Clock configuration information for the specified USART peripheral.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: USART registers related to Clock settings are initialized according
+  *                     to USART_ClockInitStruct content
+  *          - ERROR: Problem occurred during USART Registers initialization
+  */
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check USART Instance and Clock signal output parameters */
+  assert_param(IS_UART_INSTANCE(USARTx));
+  assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
+
+  /* USART needs to be in disabled state, in order to be able to configure some bits in
+     CRx registers */
+  if (LL_USART_IsEnabled(USARTx) == 0U)
+  {
+    /* Ensure USART instance is USART capable */
+    assert_param(IS_USART_INSTANCE(USARTx));
+
+    /* Check clock related parameters */
+    assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
+    assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
+    assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
+
+    /*---------------------------- USART CR2 Configuration -----------------------
+     * Configure USARTx CR2 (Clock signal related bits) with parameters:
+     * - Clock Output:                USART_CR2_CLKEN bit according to USART_ClockInitStruct->ClockOutput value
+     * - Clock Polarity:              USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
+     * - Clock Phase:                 USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
+     * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
+     */
+    MODIFY_REG(USARTx->CR2,
+               USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
+               USART_ClockInitStruct->ClockOutput | USART_ClockInitStruct->ClockPolarity |
+               USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
+  }
+  /* Else (USART not in Disabled state => return ERROR */
+  else
+  {
+    status = ERROR;
+  }
+
+  return (status);
+}
+
+/**
+  * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
+  * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
+  *                              whose fields will be set to default values.
+  * @retval None
+  */
+void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
+{
+  /* Set LL_USART_ClockInitStruct fields with default values */
+  USART_ClockInitStruct->ClockOutput       = LL_USART_CLOCK_DISABLE;
+  USART_ClockInitStruct->ClockPolarity     = LL_USART_POLARITY_LOW;            /* Not relevant when ClockOutput =
+                                                                                  LL_USART_CLOCK_DISABLE */
+  USART_ClockInitStruct->ClockPhase        = LL_USART_PHASE_1EDGE;             /* Not relevant when ClockOutput =
+                                                                                  LL_USART_CLOCK_DISABLE */
+  USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT;  /* Not relevant when ClockOutput =
+                                                                                  LL_USART_CLOCK_DISABLE */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* USART1 || USART2 || USART3 || USART4 || USART5 || USART6 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+

Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_utils.c

@@ -0,0 +1,574 @@
+/**
+  ******************************************************************************
+  * @file    stm32g0xx_ll_utils.c
+  * @author  MCD Application Team
+  * @brief   UTILS LL module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g0xx_ll_utils.h"
+#include "stm32g0xx_ll_rcc.h"
+#include "stm32g0xx_ll_system.h"
+#include "stm32g0xx_ll_pwr.h"
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32G0xx_LL_Driver
+  * @{
+  */
+
+/** @addtogroup UTILS_LL
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Private_Constants
+  * @{
+  */
+#define UTILS_MAX_FREQUENCY          64000000U     /*!< Maximum frequency for system clock, in Hz */
+
+/* Defines used for PLL range */
+#define UTILS_PLLVCO_INPUT_MIN       4000000U      /*!< Frequency min for PLLVCO input, in Hz   */
+#define UTILS_PLLVCO_INPUT_MAX       8000000U      /*!< Frequency max for PLLVCO input, in Hz   */
+#define UTILS_PLLVCO_OUTPUT_MIN      64000000U     /*!< Frequency min for PLLVCO output, in Hz  */
+#define UTILS_PLLVCO_OUTPUT_MAX      344000000U    /*!< Frequency max for PLLVCO output, in Hz  */
+
+/* Defines used for HSE range */
+#define UTILS_HSE_FREQUENCY_MIN      4000000U      /*!< Frequency min for HSE frequency, in Hz   */
+#define UTILS_HSE_FREQUENCY_MAX      48000000U     /*!< Frequency max for HSE frequency, in Hz   */
+
+/* Defines used for FLASH latency according to HCLK Frequency */
+#define UTILS_SCALE1_LATENCY1_FREQ  24000000U       /*!< HCLK frequency to set FLASH latency 1 in power scale 1  */
+#define UTILS_SCALE1_LATENCY2_FREQ  48000000U       /*!< HCLK frequency to set FLASH latency 2 in power scale 1  */
+#define UTILS_SCALE1_LATENCY3_FREQ  64000000U       /*!< HCLK frequency to set FLASH latency 3 in power scale 1  */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Private_Macros
+  * @{
+  */
+#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1)   \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2)   \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4)   \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8)   \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16)  \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64)  \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
+                                        || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
+
+#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
+                                      || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
+                                      || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
+                                      || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
+                                      || ((__VALUE__) == LL_RCC_APB1_DIV_16))
+
+#define IS_LL_UTILS_HSI_DIV(__VALUE__)  (((__VALUE__) == LL_RCC_HSI_DIV_1)  \
+                                      || ((__VALUE__) == LL_RCC_HSI_DIV_2)  \
+                                      || ((__VALUE__) == LL_RCC_HSI_DIV_4)  \
+                                      || ((__VALUE__) == LL_RCC_HSI_DIV_8)  \
+                                      || ((__VALUE__) == LL_RCC_HSI_DIV_16) \
+                                      || ((__VALUE__) == LL_RCC_HSI_DIV_32) \
+                                      || ((__VALUE__) == LL_RCC_HSI_DIV_64) \
+                                      || ((__VALUE__) == LL_RCC_HSI_DIV_128))
+
+#define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_1) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_2) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \
+                                        || ((__VALUE__) == LL_RCC_PLLM_DIV_8))
+
+#define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
+
+#define IS_LL_UTILS_PLLR_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLR_DIV_2) \
+                                        || ((__VALUE__) == LL_RCC_PLLR_DIV_3) \
+                                        || ((__VALUE__) == LL_RCC_PLLR_DIV_4) \
+                                        || ((__VALUE__) == LL_RCC_PLLR_DIV_5) \
+                                        || ((__VALUE__) == LL_RCC_PLLR_DIV_6) \
+                                        || ((__VALUE__) == LL_RCC_PLLR_DIV_7) \
+                                        || ((__VALUE__) == LL_RCC_PLLR_DIV_8))
+
+#define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__)  ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
+
+#define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
+
+#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((__VALUE__) <= UTILS_MAX_FREQUENCY)
+
+#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
+                                        || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
+
+#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
+/**
+  * @}
+  */
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Functions UTILS Private functions
+  * @{
+  */
+static uint32_t    UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
+                                               LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
+static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+static ErrorStatus UTILS_PLL_IsBusy(void);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup UTILS_LL_EF_DELAY
+  * @{
+  */
+
+/**
+  * @brief  This function configures the Cortex-M SysTick source to have 1ms time base.
+  * @note   When a RTOS is used, it is recommended to avoid changing the Systick
+  *         configuration by calling this function, for a delay use rather osDelay RTOS service.
+  * @param  HCLKFrequency HCLK frequency in Hz
+  * @note   HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
+  * @retval None
+  */
+void LL_Init1msTick(uint32_t HCLKFrequency)
+{
+  /* Use frequency provided in argument */
+  LL_InitTick(HCLKFrequency, 1000U);
+}
+
+/**
+  * @brief  This function provides accurate delay (in milliseconds) based
+  *         on SysTick counter flag
+  * @note   When a RTOS is used, it is recommended to avoid using blocking delay
+  *         and use rather osDelay service.
+  * @note   To respect 1ms timebase, user should call @ref LL_Init1msTick function which
+  *         will configure Systick to 1ms
+  * @param  Delay specifies the delay time length, in milliseconds.
+  * @retval None
+  */
+void LL_mDelay(uint32_t Delay)
+{
+  __IO uint32_t  tmp = SysTick->CTRL;  /* Clear the COUNTFLAG first */
+   uint32_t tmpDelay; /* MISRAC2012-Rule-17.8 */
+  /* Add this code to indicate that local variable is not used */
+  ((void)tmp);
+  tmpDelay  = Delay;
+  /* Add a period to guaranty minimum wait */
+  if (tmpDelay  < LL_MAX_DELAY)
+  {
+    tmpDelay ++;
+  }
+
+  while (tmpDelay  != 0U)
+  {
+    if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
+    {
+      tmpDelay --;
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup UTILS_EF_SYSTEM
+  *  @brief    System Configuration functions
+  *
+  @verbatim
+ ===============================================================================
+           ##### System Configuration functions #####
+ ===============================================================================
+    [..]
+         System, AHB and APB buses clocks configuration
+
+         (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 is 64000000 Hz.
+  @endverbatim
+  @internal
+             Depending on the device voltage range, the maximum frequency should be
+             adapted accordingly:
+
+             (++)  Table 1. HCLK clock frequency.
+             (++)  +-------------------------------------------------------+
+             (++)  | Latency         |    HCLK clock frequency (MHz)       |
+             (++)  |                 |-------------------------------------|
+             (++)  |                 | voltage range 1  | voltage range 2  |
+             (++)  |                 |   1.08V - 1.32V  |  0.9 V - 1.10V   |
+             (++)  |-----------------|------------------|------------------|
+             (++)  |0WS(1 CPU cycles)|      HCLK <= 24  |      HCLK <= 8   |
+             (++)  |-----------------|------------------|------------------|
+             (++)  |1WS(2 CPU cycles)|      HCLK <= 48  |      HCLK <= 16  |
+             (++)  |-----------------|------------------|------------------|
+             (++)  |2WS(3 CPU cycles)|      HCLK <= 64  |        -         |
+             (++)  |-----------------|------------------|------------------|
+
+  @endinternal
+  * @{
+  */
+
+/**
+  * @brief  This function sets directly SystemCoreClock CMSIS variable.
+  * @note   Variable can be calculated also through SystemCoreClockUpdate function.
+  * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
+  * @retval None
+  */
+void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
+{
+  /* HCLK clock frequency */
+  SystemCoreClock = HCLKFrequency;
+}
+
+/**
+  * @brief  This function configures system clock at maximum frequency with HSI as clock source of the PLL
+  * @note   The application need to ensure that PLL is disabled.
+  * @note   Function is based on the following formula:
+  *         - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLR)
+  *         - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = HSI frequency / PLLM)
+  *         - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
+  *         - PLLR: ensure that max frequency at 64000000 Hz is reach (PLLVCO_output / PLLR)
+  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+  *                             the configuration information for the PLL.
+  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+  *                             the configuration information for the BUS prescalers.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Max frequency configuration done
+  *          - ERROR: Max frequency configuration not done
+  */
+ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+  ErrorStatus status;
+  uint32_t pllfreq;
+
+  /* Check if one of the PLL is enabled */
+  if (UTILS_PLL_IsBusy() == SUCCESS)
+  {
+    /* Calculate the new PLL output frequency */
+    pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
+
+    /* Enable HSI if not enabled */
+    if (LL_RCC_HSI_IsReady() != 1U)
+    {
+      LL_RCC_HSI_Enable();
+      while (LL_RCC_HSI_IsReady() != 1U)
+      {
+        /* Wait for HSI ready */
+      }
+    }
+
+    /* Configure PLL */
+    LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
+                                UTILS_PLLInitStruct->PLLR);
+
+    /* Enable PLL and switch system clock to PLL */
+    status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
+  }
+  else
+  {
+    /* Current PLL configuration cannot be modified */
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  This function configures system clock with HSE as clock source of the PLL
+  * @note   The application need to ensure that PLL is disabled.
+  * @note   Function is based on the following formula:
+  *         - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLR)
+  *         - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLLVCO_input = HSE frequency / PLLM)
+  *         - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
+  *         - PLLR: ensure that max frequency at 64000000 Hz is reached (PLLVCO_output / PLLR)
+  * @param  HSEFrequency Value between Min_Data = 4000000 and Max_Data = 48000000
+  * @param  HSEBypass This parameter can be one of the following values:
+  *         @arg @ref LL_UTILS_HSEBYPASS_ON
+  *         @arg @ref LL_UTILS_HSEBYPASS_OFF
+  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+  *                             the configuration information for the PLL.
+  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+  *                             the configuration information for the BUS prescalers.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Max frequency configuration done
+  *          - ERROR: Max frequency configuration not done
+  */
+ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
+                                         LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+  ErrorStatus status;
+  uint32_t pllfreq;
+
+  /* Check the parameters */
+  assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
+  assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
+
+  /* Check if one of the PLL is enabled */
+  if (UTILS_PLL_IsBusy() == SUCCESS)
+  {
+    /* Calculate the new PLL output frequency */
+    pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
+
+    /* Enable HSE if not enabled */
+    if (LL_RCC_HSE_IsReady() != 1U)
+    {
+      /* Check if need to enable HSE bypass feature or not */
+      if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
+      {
+        LL_RCC_HSE_EnableBypass();
+      }
+      else
+      {
+        LL_RCC_HSE_DisableBypass();
+      }
+
+      /* Enable HSE */
+      LL_RCC_HSE_Enable();
+      while (LL_RCC_HSE_IsReady() != 1U)
+      {
+        /* Wait for HSE ready */
+      }
+    }
+
+    /* Configure PLL */
+    LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
+                                UTILS_PLLInitStruct->PLLR);
+
+    /* Enable PLL and switch system clock to PLL */
+    status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
+  }
+  else
+  {
+    /* Current PLL configuration cannot be modified */
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Update number of Flash wait states in line with new frequency and current
+  *         voltage range.
+  * @param  HCLKFrequency  HCLK frequency
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Latency has been modified
+  *          - ERROR: Latency cannot be modified
+  */
+ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency)
+{
+  uint32_t timeout;
+  uint32_t getlatency;
+  uint32_t latency;
+  ErrorStatus status;
+
+  /* Frequency cannot be equal to 0 or greater than max clock */
+  if ((HCLKFrequency == 0U) || (HCLKFrequency > UTILS_SCALE1_LATENCY3_FREQ))
+  {
+    status = ERROR;
+  }
+  else
+  {
+    if (HCLKFrequency > UTILS_SCALE1_LATENCY2_FREQ)
+    {
+      /* 48 < HCLK <= 64 => 2WS (3 CPU cycles) */
+      latency = LL_FLASH_LATENCY_2;
+    }
+    else
+    {
+      if (HCLKFrequency > UTILS_SCALE1_LATENCY1_FREQ)
+      {
+        /* 24 < HCLK <= 48 => 1WS (2 CPU cycles) */
+        latency = LL_FLASH_LATENCY_1;
+      }
+      else
+      {
+        /* else HCLKFrequency < 24MHz default LL_FLASH_LATENCY_0 0WS */
+        latency = LL_FLASH_LATENCY_0;
+      }
+    }
+
+    LL_FLASH_SetLatency(latency);
+
+    /* Check that the new number of wait states is taken into account to access the Flash
+       memory by reading the FLASH_ACR register */
+    timeout = 2u;
+    do
+    {
+      /* Wait for Flash latency to be updated */
+      getlatency = LL_FLASH_GetLatency();
+      timeout--;
+    } while ((getlatency != latency) && (timeout > 0u));
+
+    if(getlatency != latency)
+    {
+      status = ERROR;
+    }
+    else
+    {
+      status = SUCCESS;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup UTILS_LL_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Function to check that PLL can be modified
+  * @param  PLL_InputFrequency  PLL input frequency (in Hz)
+  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+  *                             the configuration information for the PLL.
+  * @retval PLL output frequency (in Hz)
+  */
+static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
+{
+  uint32_t pllfreq;
+
+  /* Check the parameters */
+  assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
+  assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
+  assert_param(IS_LL_UTILS_PLLR_VALUE(UTILS_PLLInitStruct->PLLR));
+
+  /* Check different PLL parameters according to RM                          */
+  /*  - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz.   */
+  pllfreq = PLL_InputFrequency / (((UTILS_PLLInitStruct->PLLM >> RCC_PLLCFGR_PLLM_Pos) + 1U));
+  assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq));
+
+  /*  - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz.*/
+  pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos));
+  assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));
+
+  /*  - PLLR: ensure that max frequency at 64000000 Hz is reached                   */
+  pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLR >> RCC_PLLCFGR_PLLR_Pos) + 1U));
+  assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
+
+  return pllfreq;
+}
+
+/**
+  * @brief  Function to check that PLL can be modified
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: PLL modification can be done
+  *          - ERROR: PLL is busy
+  */
+static ErrorStatus UTILS_PLL_IsBusy(void)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check if PLL is busy*/
+  if (LL_RCC_PLL_IsReady() != 0U)
+  {
+    /* PLL configuration cannot be modified */
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Function to enable PLL and switch system clock to PLL
+  * @param  SYSCLK_Frequency SYSCLK frequency
+  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+  *                             the configuration information for the BUS prescalers.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: No problem to switch system to PLL
+  *          - ERROR: Problem to switch system to PLL
+  */
+static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+  ErrorStatus status = SUCCESS;
+  uint32_t hclk_frequency;
+
+  assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
+  assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
+
+  /* Calculate HCLK frequency */
+  hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
+
+  /* Increasing the number of wait states because of higher CPU frequency */
+  if (SystemCoreClock < hclk_frequency)
+  {
+    /* Set FLASH latency to highest latency */
+    status = LL_SetFlashLatency(hclk_frequency);
+  }
+
+  /* Update system clock configuration */
+  if (status == SUCCESS)
+  {
+    /* Enable PLL */
+    LL_RCC_PLL_Enable();
+    LL_RCC_PLL_EnableDomain_SYS();
+    while (LL_RCC_PLL_IsReady() != 1U)
+    {
+      /* Wait for PLL ready */
+    }
+
+    /* Sysclk activation on the main PLL */
+    LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
+    LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
+    while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
+    {
+      /* Wait for system clock switch to PLL */
+    }
+
+    /* Set APB1 & APB2 prescaler*/
+    LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
+  }
+
+  /* Decreasing the number of wait states because of lower CPU frequency */
+  if (SystemCoreClock > hclk_frequency)
+  {
+    /* Set FLASH latency to lowest latency */
+    status = LL_SetFlashLatency(hclk_frequency);
+  }
+
+  /* Update SystemCoreClock variable */
+  if (status == SUCCESS)
+  {
+    LL_SetSystemCoreClock(hclk_frequency);
+  }
+
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */