11
This commit is contained in:
Mysteo
171
.cproject
Normal file
171
.cproject
Normal file
@@ -0,0 +1,171 @@
|
|||||||
|
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||||
|
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
|
||||||
|
<storageModule moduleId="org.eclipse.cdt.core.settings">
|
||||||
|
<cconfiguration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1978493364">
|
||||||
|
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1978493364" moduleId="org.eclipse.cdt.core.settings" name="Debug">
|
||||||
|
<externalSettings/>
|
||||||
|
<extensions>
|
||||||
|
<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
|
||||||
|
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||||
|
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||||
|
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||||
|
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||||
|
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||||
|
</extensions>
|
||||||
|
</storageModule>
|
||||||
|
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||||
|
<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1978493364" name="Debug" parent="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug">
|
||||||
|
<folderInfo id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1978493364." name="/" resourcePath="">
|
||||||
|
<toolChain id="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.debug.1493043228" name="MCU ARM GCC" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.debug">
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.2086550637" name="MCU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" value="STM32G070CBTx" valueType="string"/>
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.25849733" name="CPU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" value="0" valueType="string"/>
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.409440975" name="Core" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" value="0" valueType="string"/>
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.124430228" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" value="genericBoard" valueType="string"/>
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.201018160" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.6 || Debug || true || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || STM32G070CBTx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Core/Inc | ../Drivers/STM32G0xx_HAL_Driver/Inc | ../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy | ../Drivers/CMSIS/Device/ST/STM32G0xx/Include | ../Drivers/CMSIS/Include || || || USE_HAL_DRIVER | STM32G070xx || || Drivers | Core/Startup | Core || || || ${workspace_loc:/${ProjName}/STM32G070CBTX_FLASH.ld} || true || NonSecure || || secure_nsclib.o || || None || || || " valueType="string"/>
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.debug.option.cpuclock.1374904357" superClass="com.st.stm32cube.ide.mcu.debug.option.cpuclock" value="16" valueType="string"/>
|
||||||
|
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.1584764133" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
|
||||||
|
<builder buildPath="${workspace_loc:/gm60}/Debug" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.597859245" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.1360190943" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.853228228" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.value.g3" valueType="enumerated"/>
|
||||||
|
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.definedsymbols.440482240" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.definedsymbols" valueType="definedSymbols">
|
||||||
|
<listOptionValue builtIn="false" value="DEBUG"/>
|
||||||
|
</option>
|
||||||
|
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input.789342195" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input"/>
|
||||||
|
</tool>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.2131631042" name="MCU GCC Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler">
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.724781283" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.value.g3" valueType="enumerated"/>
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.955791778" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level"/>
|
||||||
|
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols.322583212" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols" valueType="definedSymbols">
|
||||||
|
<listOptionValue builtIn="false" value="DEBUG"/>
|
||||||
|
<listOptionValue builtIn="false" value="USE_HAL_DRIVER"/>
|
||||||
|
<listOptionValue builtIn="false" value="STM32G070xx"/>
|
||||||
|
</option>
|
||||||
|
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths.1429890915" name="Include paths (-I)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths" valueType="includePath">
|
||||||
|
<listOptionValue builtIn="false" value="../Core/Inc"/>
|
||||||
|
<listOptionValue builtIn="false" value="../Drivers/STM32G0xx_HAL_Driver/Inc"/>
|
||||||
|
<listOptionValue builtIn="false" value="../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy"/>
|
||||||
|
<listOptionValue builtIn="false" value="../Drivers/CMSIS/Device/ST/STM32G0xx/Include"/>
|
||||||
|
<listOptionValue builtIn="false" value="../Drivers/CMSIS/Include"/>
|
||||||
|
</option>
|
||||||
|
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.1190216382" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c"/>
|
||||||
|
</tool>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.28762604" name="MCU G++ Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler">
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.1007936134" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.value.g3" valueType="enumerated"/>
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.142979602" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level"/>
|
||||||
|
</tool>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.1244870991" name="MCU GCC Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker">
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script.24208028" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script" value="${workspace_loc:/${ProjName}/STM32G070CBTX_FLASH.ld}" valueType="string"/>
|
||||||
|
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input.389880567" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input">
|
||||||
|
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
|
||||||
|
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
|
||||||
|
</inputType>
|
||||||
|
</tool>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.1985163122" name="MCU G++ Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker"/>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver.263436789" name="MCU GCC Archiver" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver"/>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size.423625116" name="MCU Size" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size"/>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile.560011929" name="MCU Output Converter list file" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile"/>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex.1082118386" name="MCU Output Converter Hex" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex"/>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary.404407657" name="MCU Output Converter Binary" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary"/>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog.757372492" name="MCU Output Converter Verilog" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog"/>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec.302883105" name="MCU Output Converter Motorola S-rec" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec"/>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec.1036306403" name="MCU Output Converter Motorola S-rec with symbols" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec"/>
|
||||||
|
</toolChain>
|
||||||
|
</folderInfo>
|
||||||
|
<sourceEntries>
|
||||||
|
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Core"/>
|
||||||
|
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Drivers"/>
|
||||||
|
</sourceEntries>
|
||||||
|
</configuration>
|
||||||
|
</storageModule>
|
||||||
|
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
|
||||||
|
</cconfiguration>
|
||||||
|
<cconfiguration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.1620537088">
|
||||||
|
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.1620537088" moduleId="org.eclipse.cdt.core.settings" name="Release">
|
||||||
|
<externalSettings/>
|
||||||
|
<extensions>
|
||||||
|
<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
|
||||||
|
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||||
|
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||||
|
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||||
|
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||||
|
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||||
|
</extensions>
|
||||||
|
</storageModule>
|
||||||
|
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||||
|
<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="rm -rf" description="" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.1620537088" name="Release" parent="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release">
|
||||||
|
<folderInfo id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.1620537088." name="/" resourcePath="">
|
||||||
|
<toolChain id="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.release.1306717767" name="MCU ARM GCC" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.release">
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.1318666561" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" value="STM32G070CBTx" valueType="string"/>
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.484966952" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" value="0" valueType="string"/>
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.1465104717" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" value="0" valueType="string"/>
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.2058696250" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" value="genericBoard" valueType="string"/>
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.695960716" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.6 || Release || false || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || STM32G070CBTx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Core/Inc | ../Drivers/STM32G0xx_HAL_Driver/Inc | ../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy | ../Drivers/CMSIS/Device/ST/STM32G0xx/Include | ../Drivers/CMSIS/Include || || || USE_HAL_DRIVER | STM32G070xx || || Drivers | Core/Startup | Core || || || ${workspace_loc:/${ProjName}/STM32G070CBTX_FLASH.ld} || true || NonSecure || || secure_nsclib.o || || None || || || " valueType="string"/>
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.debug.option.cpuclock.278712525" superClass="com.st.stm32cube.ide.mcu.debug.option.cpuclock" value="16" valueType="string"/>
|
||||||
|
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.32267443" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
|
||||||
|
<builder buildPath="${workspace_loc:/gm60}/Release" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.844751989" managedBuildOn="true" name="Gnu Make Builder.Release" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.993669418" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.1254574027" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.value.g0" valueType="enumerated"/>
|
||||||
|
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input.1505384194" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input"/>
|
||||||
|
</tool>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.957478371" name="MCU GCC Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler">
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.575015945" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.value.g0" valueType="enumerated"/>
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.1031524766" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.value.os" valueType="enumerated"/>
|
||||||
|
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols.626156408" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols" valueType="definedSymbols">
|
||||||
|
<listOptionValue builtIn="false" value="USE_HAL_DRIVER"/>
|
||||||
|
<listOptionValue builtIn="false" value="STM32G070xx"/>
|
||||||
|
</option>
|
||||||
|
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths.350405669" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths" valueType="includePath">
|
||||||
|
<listOptionValue builtIn="false" value="../Core/Inc"/>
|
||||||
|
<listOptionValue builtIn="false" value="../Drivers/STM32G0xx_HAL_Driver/Inc"/>
|
||||||
|
<listOptionValue builtIn="false" value="../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy"/>
|
||||||
|
<listOptionValue builtIn="false" value="../Drivers/CMSIS/Device/ST/STM32G0xx/Include"/>
|
||||||
|
<listOptionValue builtIn="false" value="../Drivers/CMSIS/Include"/>
|
||||||
|
</option>
|
||||||
|
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.1687260976" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c"/>
|
||||||
|
</tool>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.508194609" name="MCU G++ Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler">
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.1529996964" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.value.g0" valueType="enumerated"/>
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.285101998" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.value.os" valueType="enumerated"/>
|
||||||
|
</tool>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.2016815408" name="MCU GCC Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker">
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script.133926077" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script" value="${workspace_loc:/${ProjName}/STM32G070CBTX_FLASH.ld}" valueType="string"/>
|
||||||
|
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input.747153715" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input">
|
||||||
|
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
|
||||||
|
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
|
||||||
|
</inputType>
|
||||||
|
</tool>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.423812299" name="MCU G++ Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker"/>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver.1472589655" name="MCU GCC Archiver" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver"/>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size.2084285407" name="MCU Size" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size"/>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile.59998760" name="MCU Output Converter list file" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile"/>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex.1891476921" name="MCU Output Converter Hex" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex"/>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary.1005967800" name="MCU Output Converter Binary" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary"/>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog.1190347618" name="MCU Output Converter Verilog" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog"/>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec.2146027663" name="MCU Output Converter Motorola S-rec" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec"/>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec.801874154" name="MCU Output Converter Motorola S-rec with symbols" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec"/>
|
||||||
|
</toolChain>
|
||||||
|
</folderInfo>
|
||||||
|
<sourceEntries>
|
||||||
|
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Core"/>
|
||||||
|
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Drivers"/>
|
||||||
|
</sourceEntries>
|
||||||
|
</configuration>
|
||||||
|
</storageModule>
|
||||||
|
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
|
||||||
|
</cconfiguration>
|
||||||
|
</storageModule>
|
||||||
|
<storageModule moduleId="org.eclipse.cdt.core.pathentry"/>
|
||||||
|
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||||
|
<project id="gm60.null.1317832652" name="gm60"/>
|
||||||
|
</storageModule>
|
||||||
|
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
|
||||||
|
<storageModule moduleId="scannerConfiguration">
|
||||||
|
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||||
|
<scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1978493364;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1978493364.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.2131631042;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.1190216382">
|
||||||
|
<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
|
||||||
|
</scannerConfigBuildInfo>
|
||||||
|
<scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.1620537088;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.1620537088.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.957478371;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.1687260976">
|
||||||
|
<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
|
||||||
|
</scannerConfigBuildInfo>
|
||||||
|
</storageModule>
|
||||||
|
</cproject>
|
||||||
8
.idea/.gitignore
generated
vendored
Normal file
8
.idea/.gitignore
generated
vendored
Normal file
@@ -0,0 +1,8 @@
|
|||||||
|
# Default ignored files
|
||||||
|
/shelf/
|
||||||
|
/workspace.xml
|
||||||
|
# Editor-based HTTP Client requests
|
||||||
|
/httpRequests/
|
||||||
|
# Datasource local storage ignored files
|
||||||
|
/dataSources/
|
||||||
|
/dataSources.local.xml
|
||||||
2
.idea/gm60.iml
generated
Normal file
2
.idea/gm60.iml
generated
Normal file
@@ -0,0 +1,2 @@
|
|||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<module classpath="CMake" type="CPP_MODULE" version="4" />
|
||||||
6
.idea/misc.xml
generated
Normal file
6
.idea/misc.xml
generated
Normal file
@@ -0,0 +1,6 @@
|
|||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<project version="4">
|
||||||
|
<component name="CMakeWorkspace" PROJECT_DIR="$PROJECT_DIR$/Boot">
|
||||||
|
<contentRoot DIR="$PROJECT_DIR$" />
|
||||||
|
</component>
|
||||||
|
</project>
|
||||||
8
.idea/modules.xml
generated
Normal file
8
.idea/modules.xml
generated
Normal file
@@ -0,0 +1,8 @@
|
|||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<project version="4">
|
||||||
|
<component name="ProjectModuleManager">
|
||||||
|
<modules>
|
||||||
|
<module fileurl="file://$PROJECT_DIR$/.idea/gm60.iml" filepath="$PROJECT_DIR$/.idea/gm60.iml" />
|
||||||
|
</modules>
|
||||||
|
</component>
|
||||||
|
</project>
|
||||||
10
.idea/runConfigurations/OCD_gm60.xml
generated
Normal file
10
.idea/runConfigurations/OCD_gm60.xml
generated
Normal file
@@ -0,0 +1,10 @@
|
|||||||
|
<component name="ProjectRunConfigurationManager">
|
||||||
|
<configuration name="OCD gm60" type="com.jetbrains.cidr.embedded.openocd.conf.type" factoryName="com.jetbrains.cidr.embedded.openocd.conf.factory" REDIRECT_INPUT="false" ELEVATE="false" USE_EXTERNAL_CONSOLE="false" PASS_PARENT_ENVS_2="true" PROJECT_NAME="gm60" TARGET_NAME="gm60.elf" version="1" RUN_TARGET_PROJECT_NAME="gm60" RUN_TARGET_NAME="gm60.elf">
|
||||||
|
<openocd version="1" gdb-port="3333" telnet-port="4444" board-config="board/st_nucleo_g0.cfg" reset-type="INIT" download-type="UPDATED_ONLY">
|
||||||
|
<debugger kind="GDB" isBundled="true" />
|
||||||
|
</openocd>
|
||||||
|
<method v="2">
|
||||||
|
<option name="CLION.COMPOUND.BUILD" enabled="true" />
|
||||||
|
</method>
|
||||||
|
</configuration>
|
||||||
|
</component>
|
||||||
6
.idea/vcs.xml
generated
Normal file
6
.idea/vcs.xml
generated
Normal file
@@ -0,0 +1,6 @@
|
|||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<project version="4">
|
||||||
|
<component name="VcsDirectoryMappings">
|
||||||
|
<mapping directory="$PROJECT_DIR$" vcs="Git" />
|
||||||
|
</component>
|
||||||
|
</project>
|
||||||
33
.mxproject
Normal file
33
.mxproject
Normal file
File diff suppressed because one or more lines are too long
32
.project
Normal file
32
.project
Normal file
@@ -0,0 +1,32 @@
|
|||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<projectDescription>
|
||||||
|
<name>gm60</name>
|
||||||
|
<comment></comment>
|
||||||
|
<projects>
|
||||||
|
</projects>
|
||||||
|
<buildSpec>
|
||||||
|
<buildCommand>
|
||||||
|
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||||
|
<triggers>clean,full,incremental,</triggers>
|
||||||
|
<arguments>
|
||||||
|
</arguments>
|
||||||
|
</buildCommand>
|
||||||
|
<buildCommand>
|
||||||
|
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||||
|
<triggers>full,incremental,</triggers>
|
||||||
|
<arguments>
|
||||||
|
</arguments>
|
||||||
|
</buildCommand>
|
||||||
|
</buildSpec>
|
||||||
|
<natures>
|
||||||
|
<nature>com.st.stm32cube.ide.mcu.MCUProjectNature</nature>
|
||||||
|
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||||
|
<nature>com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature</nature>
|
||||||
|
<nature>com.st.stm32cube.ide.mcu.MCUCubeProjectNature</nature>
|
||||||
|
<nature>com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature</nature>
|
||||||
|
<nature>com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature</nature>
|
||||||
|
<nature>com.st.stm32cube.ide.mcu.MCURootProjectNature</nature>
|
||||||
|
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||||
|
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||||
|
</natures>
|
||||||
|
</projectDescription>
|
||||||
67
App/app.c
Normal file
67
App/app.c
Normal file
@@ -0,0 +1,67 @@
|
|||||||
|
/************************************************************************************//**
|
||||||
|
* \file Demo/ARMCM0_STM32G0_Nucleo_G071RB_CubeIDE/Prog/App/app.c
|
||||||
|
* \brief User program application source file.
|
||||||
|
* \ingroup Prog_ARMCM0_STM32G0_Nucleo_G071RB_CubeIDE
|
||||||
|
* \internal
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* C O P Y R I G H T
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
|
||||||
|
*
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* L I C E N S E
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as published by the Free
|
||||||
|
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||||
|
* version.
|
||||||
|
*
|
||||||
|
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||||
|
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||||
|
* PURPOSE. See the GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||||
|
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||||
|
*
|
||||||
|
* \endinternal
|
||||||
|
****************************************************************************************/
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Include files
|
||||||
|
****************************************************************************************/
|
||||||
|
#include "header.h" /* generic header */
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Initializes the user program application. Should be called once during
|
||||||
|
** software program initialization.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
void AppInit(void)
|
||||||
|
{
|
||||||
|
/* Initialize the timer driver. */
|
||||||
|
TimerInit();
|
||||||
|
/* Initialize the led driver. */
|
||||||
|
LedInit();
|
||||||
|
/* initialize the bootloader interface */
|
||||||
|
BootComInit();
|
||||||
|
} /*** end of AppInit ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Task function of the user program application. Should be called
|
||||||
|
** continuously in the program loop.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
void AppTask(void)
|
||||||
|
{
|
||||||
|
/* Toggle LED with a fixed frequency. */
|
||||||
|
LedToggle();
|
||||||
|
/* check for bootloader activation request */
|
||||||
|
BootComCheckActivationRequest();
|
||||||
|
} /*** end of AppTask ***/
|
||||||
|
|
||||||
|
|
||||||
|
/*********************************** end of app.c **************************************/
|
||||||
39
App/app.h
Normal file
39
App/app.h
Normal file
@@ -0,0 +1,39 @@
|
|||||||
|
/************************************************************************************//**
|
||||||
|
* \file Demo/ARMCM0_STM32G0_Nucleo_G071RB_CubeIDE/Prog/App/app.h
|
||||||
|
* \brief User program application header file.
|
||||||
|
* \ingroup Prog_ARMCM0_STM32G0_Nucleo_G071RB_CubeIDE
|
||||||
|
* \internal
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* C O P Y R I G H T
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
|
||||||
|
*
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* L I C E N S E
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as published by the Free
|
||||||
|
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||||
|
* version.
|
||||||
|
*
|
||||||
|
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||||
|
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||||
|
* PURPOSE. See the GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||||
|
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||||
|
*
|
||||||
|
* \endinternal
|
||||||
|
****************************************************************************************/
|
||||||
|
#ifndef APP_H
|
||||||
|
#define APP_H
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Function prototypes
|
||||||
|
****************************************************************************************/
|
||||||
|
void AppInit(void);
|
||||||
|
void AppTask(void);
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* APP_H */
|
||||||
|
/*********************************** end of app.h **************************************/
|
||||||
226
App/boot.c
Normal file
226
App/boot.c
Normal file
@@ -0,0 +1,226 @@
|
|||||||
|
/************************************************************************************//**
|
||||||
|
* \file Demo/ARMCM0_STM32G0_Nucleo_G071RB_CubeIDE/Prog/App/boot.c
|
||||||
|
* \brief Demo program bootloader interface source file.
|
||||||
|
* \ingroup Prog_ARMCM0_STM32G0_Nucleo_G071RB_CubeIDE
|
||||||
|
* \internal
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* C O P Y R I G H T
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
|
||||||
|
*
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* L I C E N S E
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as published by the Free
|
||||||
|
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||||
|
* version.
|
||||||
|
*
|
||||||
|
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||||
|
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||||
|
* PURPOSE. See the GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||||
|
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||||
|
*
|
||||||
|
* \endinternal
|
||||||
|
****************************************************************************************/
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Include files
|
||||||
|
****************************************************************************************/
|
||||||
|
#include "header.h" /* generic header */
|
||||||
|
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Function prototypes
|
||||||
|
****************************************************************************************/
|
||||||
|
#if (BOOT_COM_RS232_ENABLE > 0)
|
||||||
|
static void BootComRs232Init(void);
|
||||||
|
static void BootComRs232CheckActivationRequest(void);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Initializes the communication interface.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
void BootComInit(void)
|
||||||
|
{
|
||||||
|
#if (BOOT_COM_RS232_ENABLE > 0)
|
||||||
|
BootComRs232Init();
|
||||||
|
#endif
|
||||||
|
} /*** end of BootComInit ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Receives the CONNECT request from the host, which indicates that the
|
||||||
|
** bootloader should be activated and, if so, activates it.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
void BootComCheckActivationRequest(void)
|
||||||
|
{
|
||||||
|
#if (BOOT_COM_RS232_ENABLE > 0)
|
||||||
|
BootComRs232CheckActivationRequest();
|
||||||
|
#endif
|
||||||
|
} /*** end of BootComCheckActivationRequest ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Bootloader activation function.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
void BootActivate(void)
|
||||||
|
{
|
||||||
|
/* perform software reset to activate the bootoader again */
|
||||||
|
NVIC_SystemReset();
|
||||||
|
} /*** end of BootActivate ***/
|
||||||
|
|
||||||
|
|
||||||
|
#if (BOOT_COM_RS232_ENABLE > 0)
|
||||||
|
/****************************************************************************************
|
||||||
|
* U N I V E R S A L A S Y N C H R O N O U S R X T X I N T E R F A C E
|
||||||
|
****************************************************************************************/
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Macro definitions
|
||||||
|
****************************************************************************************/
|
||||||
|
/** \brief Timeout time for the reception of a CTO packet. The timer is started upon
|
||||||
|
* reception of the first packet byte.
|
||||||
|
*/
|
||||||
|
#define RS232_CTO_RX_PACKET_TIMEOUT_MS (100u)
|
||||||
|
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Local data declarations
|
||||||
|
****************************************************************************************/
|
||||||
|
/** \brief UART handle to be used in API calls. */
|
||||||
|
static UART_HandleTypeDef rs232Handle;
|
||||||
|
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Function prototypes
|
||||||
|
****************************************************************************************/
|
||||||
|
static unsigned char Rs232ReceiveByte(unsigned char *data);
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Initializes the UART communication interface.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
static void BootComRs232Init(void)
|
||||||
|
{
|
||||||
|
/* Configure UART peripheral. */
|
||||||
|
rs232Handle.Instance = USART2;
|
||||||
|
rs232Handle.Init.BaudRate = BOOT_COM_RS232_BAUDRATE;
|
||||||
|
rs232Handle.Init.WordLength = UART_WORDLENGTH_8B;
|
||||||
|
rs232Handle.Init.StopBits = UART_STOPBITS_1;
|
||||||
|
rs232Handle.Init.Parity = UART_PARITY_NONE;
|
||||||
|
rs232Handle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
||||||
|
rs232Handle.Init.Mode = UART_MODE_TX_RX;
|
||||||
|
rs232Handle.Init.OverSampling = UART_OVERSAMPLING_16;
|
||||||
|
rs232Handle.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_ENABLE;
|
||||||
|
rs232Handle.Init.ClockPrescaler = UART_PRESCALER_DIV1;
|
||||||
|
/* Initialize the UART peripheral. */
|
||||||
|
HAL_UART_Init(&rs232Handle);
|
||||||
|
} /*** end of BootComRs232Init ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Receives the CONNECT request from the host, which indicates that the
|
||||||
|
** bootloader should be activated and, if so, activates it.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
static void BootComRs232CheckActivationRequest(void)
|
||||||
|
{
|
||||||
|
static unsigned char xcpCtoReqPacket[BOOT_COM_RS232_RX_MAX_DATA+1];
|
||||||
|
static unsigned char xcpCtoRxLength;
|
||||||
|
static unsigned char xcpCtoRxInProgress = 0;
|
||||||
|
static unsigned long xcpCtoRxStartTime = 0;
|
||||||
|
|
||||||
|
/* start of cto packet received? */
|
||||||
|
if (xcpCtoRxInProgress == 0)
|
||||||
|
{
|
||||||
|
/* store the message length when received */
|
||||||
|
if (Rs232ReceiveByte(&xcpCtoReqPacket[0]) == 1)
|
||||||
|
{
|
||||||
|
/* check that the length has a valid value. it should not be 0 */
|
||||||
|
if ( (xcpCtoReqPacket[0] > 0) &&
|
||||||
|
(xcpCtoReqPacket[0] <= BOOT_COM_RS232_RX_MAX_DATA) )
|
||||||
|
{
|
||||||
|
/* store the start time */
|
||||||
|
xcpCtoRxStartTime = TimerGet();
|
||||||
|
/* indicate that a cto packet is being received */
|
||||||
|
xcpCtoRxInProgress = 1;
|
||||||
|
/* reset packet data count */
|
||||||
|
xcpCtoRxLength = 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* store the next packet byte */
|
||||||
|
if (Rs232ReceiveByte(&xcpCtoReqPacket[xcpCtoRxLength+1]) == 1)
|
||||||
|
{
|
||||||
|
/* increment the packet data count */
|
||||||
|
xcpCtoRxLength++;
|
||||||
|
|
||||||
|
/* check to see if the entire packet was received */
|
||||||
|
if (xcpCtoRxLength == xcpCtoReqPacket[0])
|
||||||
|
{
|
||||||
|
/* done with cto packet reception */
|
||||||
|
xcpCtoRxInProgress = 0;
|
||||||
|
|
||||||
|
/* check if this was an XCP CONNECT command */
|
||||||
|
if ((xcpCtoReqPacket[1] == 0xff) && (xcpCtoRxLength == 2))
|
||||||
|
{
|
||||||
|
/* connection request received so start the bootloader */
|
||||||
|
BootActivate();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* check packet reception timeout */
|
||||||
|
if (TimerGet() > (xcpCtoRxStartTime + RS232_CTO_RX_PACKET_TIMEOUT_MS))
|
||||||
|
{
|
||||||
|
/* cancel cto packet reception due to timeout. note that this automatically
|
||||||
|
* discards the already received packet bytes, allowing the host to retry.
|
||||||
|
*/
|
||||||
|
xcpCtoRxInProgress = 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
} /*** end of BootComRs232CheckActivationRequest ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Receives a communication interface byte if one is present.
|
||||||
|
** \param data Pointer to byte where the data is to be stored.
|
||||||
|
** \return 1 if a byte was received, 0 otherwise.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
static unsigned char Rs232ReceiveByte(unsigned char *data)
|
||||||
|
{
|
||||||
|
HAL_StatusTypeDef result;
|
||||||
|
|
||||||
|
/* receive a byte in a non-blocking manner */
|
||||||
|
result = HAL_UART_Receive(&rs232Handle, data, 1, 0);
|
||||||
|
/* process the result */
|
||||||
|
if (result == HAL_OK)
|
||||||
|
{
|
||||||
|
/* success */
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
/* error occurred */
|
||||||
|
return 0;
|
||||||
|
} /*** end of Rs232ReceiveByte ***/
|
||||||
|
#endif /* BOOT_COM_RS232_ENABLE > 0 */
|
||||||
|
|
||||||
|
|
||||||
|
/*********************************** end of boot.c *************************************/
|
||||||
40
App/boot.h
Normal file
40
App/boot.h
Normal file
@@ -0,0 +1,40 @@
|
|||||||
|
/************************************************************************************//**
|
||||||
|
* \file Demo/ARMCM0_STM32G0_Nucleo_G071RB_CubeIDE/Prog/App/boot.h
|
||||||
|
* \brief Demo program bootloader interface header file.
|
||||||
|
* \ingroup Prog_ARMCM0_STM32G0_Nucleo_G071RB_CubeIDE
|
||||||
|
* \internal
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* C O P Y R I G H T
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
|
||||||
|
*
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* L I C E N S E
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as published by the Free
|
||||||
|
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||||
|
* version.
|
||||||
|
*
|
||||||
|
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||||
|
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||||
|
* PURPOSE. See the GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||||
|
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||||
|
*
|
||||||
|
* \endinternal
|
||||||
|
****************************************************************************************/
|
||||||
|
#ifndef BOOT_H
|
||||||
|
#define BOOT_H
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Function prototypes
|
||||||
|
****************************************************************************************/
|
||||||
|
void BootComInit(void);
|
||||||
|
void BootComCheckActivationRequest(void);
|
||||||
|
void BootActivate(void);
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* BOOT_H */
|
||||||
|
/*********************************** end of boot.h *************************************/
|
||||||
43
App/header.h
Normal file
43
App/header.h
Normal file
@@ -0,0 +1,43 @@
|
|||||||
|
/************************************************************************************//**
|
||||||
|
* \file Demo/ARMCM0_STM32G0_Nucleo_G071RB_CubeIDE/Prog/App/header.h
|
||||||
|
* \brief Generic header file.
|
||||||
|
* \ingroup Prog_ARMCM0_STM32G0_Nucleo_G071RB_CubeIDE
|
||||||
|
* \internal
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* C O P Y R I G H T
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
|
||||||
|
*
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* L I C E N S E
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as published by the Free
|
||||||
|
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||||
|
* version.
|
||||||
|
*
|
||||||
|
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||||
|
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||||
|
* PURPOSE. See the GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||||
|
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||||
|
*
|
||||||
|
* \endinternal
|
||||||
|
****************************************************************************************/
|
||||||
|
#ifndef HEADER_H
|
||||||
|
#define HEADER_H
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Include files
|
||||||
|
****************************************************************************************/
|
||||||
|
#include "../../Boot/App/blt_conf.h" /* bootloader configuration */
|
||||||
|
#include "stm32g0xx.h" /* STM32 CPU and HAL header */
|
||||||
|
#include "app.h" /* Application header */
|
||||||
|
#include "boot.h" /* bootloader interface driver */
|
||||||
|
#include "led.h" /* LED driver */
|
||||||
|
#include "timer.h" /* Timer driver */
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* HEADER_H */
|
||||||
|
/*********************************** end of header.h ***********************************/
|
||||||
94
App/led.c
Normal file
94
App/led.c
Normal file
@@ -0,0 +1,94 @@
|
|||||||
|
/************************************************************************************//**
|
||||||
|
* \file Demo/ARMCM0_STM32G0_Nucleo_G071RB_CubeIDE/Prog/App/led.c
|
||||||
|
* \brief LED driver source file.
|
||||||
|
* \ingroup Prog_ARMCM0_STM32G0_Nucleo_G071RB_CubeIDE
|
||||||
|
* \internal
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* C O P Y R I G H T
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
|
||||||
|
*
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* L I C E N S E
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as published by the Free
|
||||||
|
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||||
|
* version.
|
||||||
|
*
|
||||||
|
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||||
|
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||||
|
* PURPOSE. See the GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||||
|
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||||
|
*
|
||||||
|
* \endinternal
|
||||||
|
****************************************************************************************/
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Include files
|
||||||
|
****************************************************************************************/
|
||||||
|
#include "header.h" /* generic header */
|
||||||
|
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Macro definitions
|
||||||
|
****************************************************************************************/
|
||||||
|
/** \brief Toggle interval time in milliseconds. */
|
||||||
|
#define LED_TOGGLE_MS (500)
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Initializes the LED.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
void LedInit(void)
|
||||||
|
{
|
||||||
|
/* Note that the initialization of the LED GPIO pin is done in HAL_MspInit(). All that
|
||||||
|
* is left to do here is to make sure the LED is turned off after initialization.
|
||||||
|
*/
|
||||||
|
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_RESET);
|
||||||
|
} /*** end of LedInit ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Toggles the LED at a fixed time interval.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
void LedToggle(void)
|
||||||
|
{
|
||||||
|
static unsigned char led_toggle_state = 0;
|
||||||
|
static unsigned long timer_counter_last = 0;
|
||||||
|
unsigned long timer_counter_now;
|
||||||
|
|
||||||
|
/* check if toggle interval time passed */
|
||||||
|
timer_counter_now = TimerGet();
|
||||||
|
if ( (timer_counter_now - timer_counter_last) < LED_TOGGLE_MS)
|
||||||
|
{
|
||||||
|
/* not yet time to toggle */
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* determine toggle action */
|
||||||
|
if (led_toggle_state == 0)
|
||||||
|
{
|
||||||
|
led_toggle_state = 1;
|
||||||
|
/* turn the LED on */
|
||||||
|
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_SET);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
led_toggle_state = 0;
|
||||||
|
/* turn the LED off */
|
||||||
|
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_RESET);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* store toggle time to determine next toggle interval */
|
||||||
|
timer_counter_last = timer_counter_now;
|
||||||
|
} /*** end of LedToggle ***/
|
||||||
|
|
||||||
|
|
||||||
|
/*********************************** end of led.c **************************************/
|
||||||
39
App/led.h
Normal file
39
App/led.h
Normal file
@@ -0,0 +1,39 @@
|
|||||||
|
/************************************************************************************//**
|
||||||
|
* \file Demo/ARMCM0_STM32G0_Nucleo_G071RB_CubeIDE/Prog/App/led.h
|
||||||
|
* \brief LED driver header file.
|
||||||
|
* \ingroup Prog_ARMCM0_STM32G0_Nucleo_G071RB_CubeIDE
|
||||||
|
* \internal
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* C O P Y R I G H T
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
|
||||||
|
*
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* L I C E N S E
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as published by the Free
|
||||||
|
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||||
|
* version.
|
||||||
|
*
|
||||||
|
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||||
|
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||||
|
* PURPOSE. See the GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||||
|
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||||
|
*
|
||||||
|
* \endinternal
|
||||||
|
****************************************************************************************/
|
||||||
|
#ifndef LED_H
|
||||||
|
#define LED_H
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Function prototypes
|
||||||
|
****************************************************************************************/
|
||||||
|
void LedInit(void);
|
||||||
|
void LedToggle(void);
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* LED_H */
|
||||||
|
/*********************************** end of led.h **************************************/
|
||||||
60
App/timer.c
Normal file
60
App/timer.c
Normal file
@@ -0,0 +1,60 @@
|
|||||||
|
/************************************************************************************//**
|
||||||
|
* \file Demo/ARMCM0_STM32G0_Nucleo_G071RB_CubeIDE/Prog/App/timer.c
|
||||||
|
* \brief Timer driver source file.
|
||||||
|
* \ingroup Prog_ARMCM0_STM32G0_Nucleo_G071RB_CubeIDE
|
||||||
|
* \internal
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* C O P Y R I G H T
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
|
||||||
|
*
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* L I C E N S E
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as published by the Free
|
||||||
|
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||||
|
* version.
|
||||||
|
*
|
||||||
|
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||||
|
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||||
|
* PURPOSE. See the GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||||
|
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||||
|
*
|
||||||
|
* \endinternal
|
||||||
|
****************************************************************************************/
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Include files
|
||||||
|
****************************************************************************************/
|
||||||
|
#include "header.h" /* generic header */
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Initializes the timer.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
void TimerInit(void)
|
||||||
|
{
|
||||||
|
/* The HAL initialization already configured the Systick interrupt to generate an
|
||||||
|
* interrupt every 1 millisecond. Nothing more needs to be done here.
|
||||||
|
*/
|
||||||
|
} /*** end of TimerInit ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Obtains the counter value of the millisecond timer.
|
||||||
|
** \return Current value of the millisecond timer.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
unsigned long TimerGet(void)
|
||||||
|
{
|
||||||
|
/* Read and return the tick counter value. */
|
||||||
|
return HAL_GetTick();
|
||||||
|
} /*** end of TimerGet ***/
|
||||||
|
|
||||||
|
|
||||||
|
/*********************************** end of timer.c ************************************/
|
||||||
38
App/timer.h
Normal file
38
App/timer.h
Normal file
@@ -0,0 +1,38 @@
|
|||||||
|
/************************************************************************************//**
|
||||||
|
* \file Demo/ARMCM0_STM32G0_Nucleo_G071RB_CubeIDE/Prog/App/timer.h
|
||||||
|
* \brief Timer driver header file.
|
||||||
|
* \ingroup Prog_ARMCM0_STM32G0_Nucleo_G071RB_CubeIDE
|
||||||
|
* \internal
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* C O P Y R I G H T
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
|
||||||
|
*
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* L I C E N S E
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as published by the Free
|
||||||
|
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||||
|
* version.
|
||||||
|
*
|
||||||
|
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||||
|
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||||
|
* PURPOSE. See the GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||||
|
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||||
|
*
|
||||||
|
* \endinternal
|
||||||
|
****************************************************************************************/
|
||||||
|
#ifndef TIMER_H
|
||||||
|
#define TIMER_H
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Function prototypes
|
||||||
|
****************************************************************************************/
|
||||||
|
void TimerInit(void);
|
||||||
|
unsigned long TimerGet(void);
|
||||||
|
|
||||||
|
#endif /* TIMER_H */
|
||||||
|
/*********************************** end of timer.h ************************************/
|
||||||
196
Boot/.cproject
Normal file
196
Boot/.cproject
Normal file
@@ -0,0 +1,196 @@
|
|||||||
|
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||||
|
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
|
||||||
|
<storageModule moduleId="org.eclipse.cdt.core.settings">
|
||||||
|
<cconfiguration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1190274931">
|
||||||
|
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1190274931" moduleId="org.eclipse.cdt.core.settings" name="Debug">
|
||||||
|
<externalSettings/>
|
||||||
|
<extensions>
|
||||||
|
<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
|
||||||
|
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||||
|
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||||
|
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||||
|
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||||
|
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||||
|
</extensions>
|
||||||
|
</storageModule>
|
||||||
|
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||||
|
<configuration artifactExtension="elf" artifactName="openblt_stm32g071" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1190274931" name="Debug" parent="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug">
|
||||||
|
<folderInfo id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1190274931." name="/" resourcePath="">
|
||||||
|
<toolChain id="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.debug.790899895" name="MCU ARM GCC" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.debug">
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.type.1414316593" name="Internal Toolchain Type" superClass="com.st.stm32cube.ide.mcu.option.internal.toolchain.type" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32" valueType="string"/>
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.version.610559525" name="Internal Toolchain Version" superClass="com.st.stm32cube.ide.mcu.option.internal.toolchain.version" useByScannerDiscovery="false" value="7-2018-q2-update" valueType="string"/>
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.320533220" name="MCU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" useByScannerDiscovery="false" value="STM32G071RBTx" valueType="string"/>
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.1495893734" name="CPU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" useByScannerDiscovery="false" value="0" valueType="string"/>
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.397961040" name="Core" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" useByScannerDiscovery="false" value="0" valueType="string"/>
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.359055718" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="NUCLEO-G071RB" valueType="string"/>
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1211812695" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.5 || Debug || true || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32 || NUCLEO-G071RB || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Drivers/CMSIS/Include | ../Core/Inc | ../Drivers/STM32G0xx_HAL_Driver/Inc | ../Drivers/CMSIS/Device/ST/STM32G0xx/Include | ../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy || || || STM32G071xx | USE_HAL_DRIVER | USE_FULL_LL_DRIVER || || Drivers | Core/Startup | Core || || || ${workspace_loc:/${ProjName}/STM32G071RBTX_FLASH.ld} || true || NonSecure || || secure_nsclib.o || || None || " valueType="string"/>
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.convertbinary.561675928" name="Convert to binary file (-O binary)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.convertbinary" useByScannerDiscovery="false" value="false" valueType="boolean"/>
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.convertsrec.1067549904" name="Convert to Motorola S-record file (-O srec)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.convertsrec" useByScannerDiscovery="false" value="true" valueType="boolean"/>
|
||||||
|
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.831664364" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
|
||||||
|
<builder buildPath="${workspace_loc:/Boot}/Debug" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.720273484" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.829259011" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.818193378" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.value.g3" valueType="enumerated"/>
|
||||||
|
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.definedsymbols.43020047" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.definedsymbols" useByScannerDiscovery="false" valueType="definedSymbols">
|
||||||
|
<listOptionValue builtIn="false" value="DEBUG"/>
|
||||||
|
</option>
|
||||||
|
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input.2068755612" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input"/>
|
||||||
|
</tool>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.1531103548" name="MCU GCC Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler">
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.1107469485" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.value.g3" valueType="enumerated"/>
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.709423442" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.value.og" valueType="enumerated"/>
|
||||||
|
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols.610630256" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols" useByScannerDiscovery="false" valueType="definedSymbols">
|
||||||
|
<listOptionValue builtIn="false" value="STM32G071xx"/>
|
||||||
|
<listOptionValue builtIn="false" value="USE_HAL_DRIVER"/>
|
||||||
|
<listOptionValue builtIn="false" value="USE_FULL_LL_DRIVER"/>
|
||||||
|
<listOptionValue builtIn="false" value="DEBUG"/>
|
||||||
|
</option>
|
||||||
|
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths.905278072" name="Include paths (-I)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths" useByScannerDiscovery="false" valueType="includePath">
|
||||||
|
<listOptionValue builtIn="false" value="../Core/Inc"/>
|
||||||
|
<listOptionValue builtIn="false" value="../Drivers/STM32G0xx_HAL_Driver/Inc"/>
|
||||||
|
<listOptionValue builtIn="false" value="../Drivers/CMSIS/Device/ST/STM32G0xx/Include"/>
|
||||||
|
<listOptionValue builtIn="false" value="../Drivers/CMSIS/Include"/>
|
||||||
|
<listOptionValue builtIn="false" value="../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy"/>
|
||||||
|
<listOptionValue builtIn="false" value="../App"/>
|
||||||
|
<listOptionValue builtIn="false" value="../../../../Source"/>
|
||||||
|
<listOptionValue builtIn="false" value="../../../../Source/ARMCM0_STM32G0"/>
|
||||||
|
</option>
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.fdata.145194903" name="Place data in their own sections (-fdata-sections)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.fdata" useByScannerDiscovery="false" value="true" valueType="boolean"/>
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.languagestandard.259210343" name="Language standard" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.languagestandard" useByScannerDiscovery="true" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.languagestandard.value.gnu11" valueType="enumerated"/>
|
||||||
|
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.896341113" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c"/>
|
||||||
|
</tool>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.1671227917" name="MCU G++ Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler">
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.1636188900" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.value.g3" valueType="enumerated"/>
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.1020265466" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level" useByScannerDiscovery="false"/>
|
||||||
|
</tool>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.547817905" name="MCU GCC Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker">
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script.719831566" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script" useByScannerDiscovery="false" value="../STM32G071RBTX.ld" valueType="string"/>
|
||||||
|
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input.1566251720" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input">
|
||||||
|
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
|
||||||
|
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
|
||||||
|
</inputType>
|
||||||
|
</tool>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.1131867451" name="MCU G++ Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker">
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.option.script.1323412574" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.option.script" value="${workspace_loc:/${ProjName}/STM32G071RBTX_FLASH.ld}" valueType="string"/>
|
||||||
|
</tool>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver.2072465052" name="MCU GCC Archiver" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver"/>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size.1934462938" name="MCU Size" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size"/>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile.420427570" name="MCU Output Converter list file" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile"/>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex.1184159403" name="MCU Output Converter Hex" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex"/>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary.1667244240" name="MCU Output Converter Binary" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary"/>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog.1843928617" name="MCU Output Converter Verilog" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog"/>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec.1350719203" name="MCU Output Converter Motorola S-rec" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec"/>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec.51940351" name="MCU Output Converter Motorola S-rec with symbols" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec"/>
|
||||||
|
</toolChain>
|
||||||
|
</folderInfo>
|
||||||
|
<sourceEntries>
|
||||||
|
<entry flags="VALUE_WORKSPACE_PATH" kind="sourcePath" name="App"/>
|
||||||
|
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Core"/>
|
||||||
|
<entry flags="VALUE_WORKSPACE_PATH" kind="sourcePath" name="Loader"/>
|
||||||
|
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Drivers"/>
|
||||||
|
</sourceEntries>
|
||||||
|
</configuration>
|
||||||
|
</storageModule>
|
||||||
|
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
|
||||||
|
</cconfiguration>
|
||||||
|
<cconfiguration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.1093787208">
|
||||||
|
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.1093787208" moduleId="org.eclipse.cdt.core.settings" name="Release">
|
||||||
|
<externalSettings/>
|
||||||
|
<extensions>
|
||||||
|
<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
|
||||||
|
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||||
|
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||||
|
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||||
|
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||||
|
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||||
|
</extensions>
|
||||||
|
</storageModule>
|
||||||
|
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||||
|
<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="rm -rf" description="" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.1093787208" name="Release" parent="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release">
|
||||||
|
<folderInfo id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.1093787208." name="/" resourcePath="">
|
||||||
|
<toolChain id="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.release.1108553868" name="MCU ARM GCC" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.release">
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.type.1666213559" name="Internal Toolchain Type" superClass="com.st.stm32cube.ide.mcu.option.internal.toolchain.type" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32" valueType="string"/>
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.version.2026553254" name="Internal Toolchain Version" superClass="com.st.stm32cube.ide.mcu.option.internal.toolchain.version" useByScannerDiscovery="false" value="7-2018-q2-update" valueType="string"/>
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.1522400403" name="MCU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" useByScannerDiscovery="true" value="STM32G071RBTx" valueType="string"/>
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.1513702454" name="CPU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" useByScannerDiscovery="false" value="0" valueType="string"/>
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.1643778463" name="Core" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" useByScannerDiscovery="false" value="0" valueType="string"/>
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.479129512" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="NUCLEO-G071RB" valueType="string"/>
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.11633990" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.5 || Release || false || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32 || NUCLEO-G071RB || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Drivers/CMSIS/Include | ../Core/Inc | ../Drivers/STM32G0xx_HAL_Driver/Inc | ../Drivers/CMSIS/Device/ST/STM32G0xx/Include | ../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy || || || STM32G071xx | USE_HAL_DRIVER | USE_FULL_LL_DRIVER || || Drivers | Core/Startup | Core || || || ${workspace_loc:/${ProjName}/STM32G071RBTX_FLASH.ld} || true || NonSecure || || secure_nsclib.o || || None || " valueType="string"/>
|
||||||
|
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.977550986" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
|
||||||
|
<builder buildPath="${workspace_loc:/Boot}/Release" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.1558907680" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.1989676835" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.662904735" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.value.g0" valueType="enumerated"/>
|
||||||
|
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input.1278457716" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input"/>
|
||||||
|
</tool>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.1877832415" name="MCU GCC Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler">
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.297540613" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.value.g0" valueType="enumerated"/>
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.1132430832" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.value.os" valueType="enumerated"/>
|
||||||
|
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols.1271556026" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols" useByScannerDiscovery="false" valueType="definedSymbols">
|
||||||
|
<listOptionValue builtIn="false" value="STM32G071xx"/>
|
||||||
|
<listOptionValue builtIn="false" value="USE_HAL_DRIVER"/>
|
||||||
|
<listOptionValue builtIn="false" value="USE_FULL_LL_DRIVER"/>
|
||||||
|
</option>
|
||||||
|
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths.107714465" name="Include paths (-I)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths" useByScannerDiscovery="false" valueType="includePath">
|
||||||
|
<listOptionValue builtIn="false" value="../Core/Inc"/>
|
||||||
|
<listOptionValue builtIn="false" value="../Drivers/STM32G0xx_HAL_Driver/Inc"/>
|
||||||
|
<listOptionValue builtIn="false" value="../Drivers/CMSIS/Device/ST/STM32G0xx/Include"/>
|
||||||
|
<listOptionValue builtIn="false" value="../Drivers/CMSIS/Include"/>
|
||||||
|
<listOptionValue builtIn="false" value="../Drivers/STM32G0xx_HAL_Driver/Inc/Legacy"/>
|
||||||
|
</option>
|
||||||
|
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.59285058" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c"/>
|
||||||
|
</tool>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.170675806" name="MCU G++ Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler">
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.1931755686" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.value.g0" valueType="enumerated"/>
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.1010076990" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.value.os" valueType="enumerated"/>
|
||||||
|
</tool>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.687976174" name="MCU GCC Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker">
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script.261526681" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script" value="${workspace_loc:/${ProjName}/STM32G071RBTX_FLASH.ld}" valueType="string"/>
|
||||||
|
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input.1188668828" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input">
|
||||||
|
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
|
||||||
|
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
|
||||||
|
</inputType>
|
||||||
|
</tool>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.1115859448" name="MCU G++ Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker">
|
||||||
|
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.option.script.877500018" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.option.script" value="${workspace_loc:/${ProjName}/STM32G071RBTX_FLASH.ld}" valueType="string"/>
|
||||||
|
</tool>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver.319483229" name="MCU GCC Archiver" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver"/>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size.1554199598" name="MCU Size" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size"/>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile.1820020525" name="MCU Output Converter list file" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile"/>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex.637433287" name="MCU Output Converter Hex" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex"/>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary.1254958248" name="MCU Output Converter Binary" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary"/>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog.1260965653" name="MCU Output Converter Verilog" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog"/>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec.1842764133" name="MCU Output Converter Motorola S-rec" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec"/>
|
||||||
|
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec.1082065457" name="MCU Output Converter Motorola S-rec with symbols" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec"/>
|
||||||
|
</toolChain>
|
||||||
|
</folderInfo>
|
||||||
|
<sourceEntries>
|
||||||
|
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Core"/>
|
||||||
|
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Drivers"/>
|
||||||
|
</sourceEntries>
|
||||||
|
</configuration>
|
||||||
|
</storageModule>
|
||||||
|
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
|
||||||
|
</cconfiguration>
|
||||||
|
</storageModule>
|
||||||
|
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||||
|
<project id="Boot.null.1055895233" name="Boot"/>
|
||||||
|
</storageModule>
|
||||||
|
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
|
||||||
|
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
|
||||||
|
<storageModule moduleId="scannerConfiguration">
|
||||||
|
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||||
|
<scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.1093787208;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.1093787208.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.1877832415;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.59285058">
|
||||||
|
<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
|
||||||
|
</scannerConfigBuildInfo>
|
||||||
|
<scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1190274931;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1190274931.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.1531103548;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.896341113">
|
||||||
|
<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
|
||||||
|
</scannerConfigBuildInfo>
|
||||||
|
</storageModule>
|
||||||
|
<storageModule moduleId="refreshScope" versionNumber="2">
|
||||||
|
<configuration configurationName="Debug">
|
||||||
|
<resource resourceType="PROJECT" workspacePath="/Boot"/>
|
||||||
|
</configuration>
|
||||||
|
<configuration configurationName="Release">
|
||||||
|
<resource resourceType="PROJECT" workspacePath="/Boot"/>
|
||||||
|
</configuration>
|
||||||
|
</storageModule>
|
||||||
|
</cproject>
|
||||||
64
Boot/.gitignore
vendored
Normal file
64
Boot/.gitignore
vendored
Normal file
@@ -0,0 +1,64 @@
|
|||||||
|
**/cmake-build-debug/
|
||||||
|
**/.idea/
|
||||||
|
**/cmake-build-release/
|
||||||
|
**/cmake-build**
|
||||||
|
**/cmake-build-relwithdebinfo/
|
||||||
|
**/cmake-build-test/
|
||||||
|
**/cmake-build-arm/
|
||||||
|
**/cmake-build-release-arm/
|
||||||
|
/bootloader/cmake-build-debug/
|
||||||
|
/bootloader/cmake-build-minsizerel/
|
||||||
|
/bootloader/cmake-build-release/
|
||||||
|
|
||||||
|
# Prerequisites
|
||||||
|
*.d
|
||||||
|
|
||||||
|
# Object files
|
||||||
|
*.o
|
||||||
|
*.ko
|
||||||
|
*.obj
|
||||||
|
*.elf
|
||||||
|
|
||||||
|
# Linker output
|
||||||
|
*.ilk
|
||||||
|
*.map
|
||||||
|
*.exp
|
||||||
|
|
||||||
|
# Precompiled Headers
|
||||||
|
*.gch
|
||||||
|
*.pch
|
||||||
|
|
||||||
|
# Libraries
|
||||||
|
*.lib
|
||||||
|
*.a
|
||||||
|
*.la
|
||||||
|
*.lo
|
||||||
|
|
||||||
|
# Shared objects (inc. Windows DLLs)
|
||||||
|
*.dll
|
||||||
|
*.so
|
||||||
|
*.so.*
|
||||||
|
*.dylib
|
||||||
|
|
||||||
|
# Executables
|
||||||
|
*.exe
|
||||||
|
*.out
|
||||||
|
*.app
|
||||||
|
*.i*86
|
||||||
|
*.x86_64
|
||||||
|
*.hex
|
||||||
|
|
||||||
|
# Debug files
|
||||||
|
*.dSYM/
|
||||||
|
*.su
|
||||||
|
*.idb
|
||||||
|
*.pdb
|
||||||
|
|
||||||
|
# Kernel Module Compile Results
|
||||||
|
*.mod*
|
||||||
|
*.cmd
|
||||||
|
.tmp_versions/
|
||||||
|
modules.order
|
||||||
|
Module.symvers
|
||||||
|
Mkfile.old
|
||||||
|
dkms.conf
|
||||||
34
Boot/.mxproject
Normal file
34
Boot/.mxproject
Normal file
File diff suppressed because one or more lines are too long
39
Boot/.project
Normal file
39
Boot/.project
Normal file
@@ -0,0 +1,39 @@
|
|||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<projectDescription>
|
||||||
|
<name>Boot</name>
|
||||||
|
<comment></comment>
|
||||||
|
<projects>
|
||||||
|
</projects>
|
||||||
|
<buildSpec>
|
||||||
|
<buildCommand>
|
||||||
|
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||||
|
<triggers>clean,full,incremental,</triggers>
|
||||||
|
<arguments>
|
||||||
|
</arguments>
|
||||||
|
</buildCommand>
|
||||||
|
<buildCommand>
|
||||||
|
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||||
|
<triggers>full,incremental,</triggers>
|
||||||
|
<arguments>
|
||||||
|
</arguments>
|
||||||
|
</buildCommand>
|
||||||
|
</buildSpec>
|
||||||
|
<natures>
|
||||||
|
<nature>com.st.stm32cube.ide.mcu.MCUProjectNature</nature>
|
||||||
|
<nature>com.st.stm32cube.ide.mcu.MCUCubeProjectNature</nature>
|
||||||
|
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||||
|
<nature>com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature</nature>
|
||||||
|
<nature>com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature</nature>
|
||||||
|
<nature>com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature</nature>
|
||||||
|
<nature>com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature</nature>
|
||||||
|
<nature>com.st.stm32cube.ide.mcu.MCURootProjectNature</nature>
|
||||||
|
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||||
|
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||||
|
</natures>
|
||||||
|
<variableList>
|
||||||
|
<variable>
|
||||||
|
<name>OPENBLT_ROOT</name>
|
||||||
|
<value>$%7BPARENT-3-PROJECT_LOC%7D/Source</value>
|
||||||
|
</variable>
|
||||||
|
</variableList>
|
||||||
|
</projectDescription>
|
||||||
27
Boot/.settings/language.settings.xml
Normal file
27
Boot/.settings/language.settings.xml
Normal file
@@ -0,0 +1,27 @@
|
|||||||
|
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||||
|
<project>
|
||||||
|
<configuration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1190274931" name="Debug">
|
||||||
|
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
|
||||||
|
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
|
||||||
|
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
|
||||||
|
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
|
||||||
|
<provider copy-of="extension" id="org.eclipse.cdt.managedbuilder.core.GCCBuildCommandParser"/>
|
||||||
|
<provider class="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" console="false" env-hash="195472777576109418" id="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" keep-relative-paths="false" name="MCU ARM GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
|
||||||
|
<language-scope id="org.eclipse.cdt.core.gcc"/>
|
||||||
|
<language-scope id="org.eclipse.cdt.core.g++"/>
|
||||||
|
</provider>
|
||||||
|
</extension>
|
||||||
|
</configuration>
|
||||||
|
<configuration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.1093787208" name="Release">
|
||||||
|
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
|
||||||
|
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
|
||||||
|
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
|
||||||
|
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
|
||||||
|
<provider copy-of="extension" id="org.eclipse.cdt.managedbuilder.core.GCCBuildCommandParser"/>
|
||||||
|
<provider class="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" console="false" env-hash="287956616701908586" id="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" keep-relative-paths="false" name="MCU ARM GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
|
||||||
|
<language-scope id="org.eclipse.cdt.core.gcc"/>
|
||||||
|
<language-scope id="org.eclipse.cdt.core.g++"/>
|
||||||
|
</provider>
|
||||||
|
</extension>
|
||||||
|
</configuration>
|
||||||
|
</project>
|
||||||
56
Boot/ARMCM0_STM32G0/GCC/cpu_comp.c
Normal file
56
Boot/ARMCM0_STM32G0/GCC/cpu_comp.c
Normal file
@@ -0,0 +1,56 @@
|
|||||||
|
/************************************************************************************//**
|
||||||
|
* \file Source/ARMCM0_STM32G0/GCC/cpu_comp.c
|
||||||
|
* \brief Bootloader cpu module source file.
|
||||||
|
* \ingroup Target_ARMCM0_STM32G0
|
||||||
|
* \internal
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* C O P Y R I G H T
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* Copyright (c) 2019 by Feaser http://www.feaser.com All rights reserved
|
||||||
|
*
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* L I C E N S E
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as published by the Free
|
||||||
|
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||||
|
* version.
|
||||||
|
*
|
||||||
|
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||||
|
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||||
|
* PURPOSE. See the GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||||
|
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||||
|
*
|
||||||
|
* \endinternal
|
||||||
|
****************************************************************************************/
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Include files
|
||||||
|
****************************************************************************************/
|
||||||
|
#include "boot.h" /* bootloader generic header */
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Disable global interrupts.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
void CpuIrqDisable(void)
|
||||||
|
{
|
||||||
|
__asm volatile ("cpsid i");
|
||||||
|
} /*** end of CpuIrqDisable ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Enable global interrupts.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
void CpuIrqEnable(void)
|
||||||
|
{
|
||||||
|
__asm volatile ("cpsie i");
|
||||||
|
} /*** end of CpuIrqEnable ***/
|
||||||
|
|
||||||
|
/*********************************** end of cpu_comp.c *********************************/
|
||||||
57
Boot/ARMCM0_STM32G0/IAR/cpu_comp.c
Normal file
57
Boot/ARMCM0_STM32G0/IAR/cpu_comp.c
Normal file
@@ -0,0 +1,57 @@
|
|||||||
|
/************************************************************************************//**
|
||||||
|
* \file Source/ARMCM0_STM32G0/IAR/cpu_comp.c
|
||||||
|
* \brief Bootloader cpu module source file.
|
||||||
|
* \ingroup Target_ARMCM0_STM32G0
|
||||||
|
* \internal
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* C O P Y R I G H T
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* Copyright (c) 2019 by Feaser http://www.feaser.com All rights reserved
|
||||||
|
*
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* L I C E N S E
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as published by the Free
|
||||||
|
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||||
|
* version.
|
||||||
|
*
|
||||||
|
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||||
|
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||||
|
* PURPOSE. See the GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||||
|
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||||
|
*
|
||||||
|
* \endinternal
|
||||||
|
****************************************************************************************/
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Include files
|
||||||
|
****************************************************************************************/
|
||||||
|
#include "boot.h" /* bootloader generic header */
|
||||||
|
#include <intrinsics.h> /* IAR intrinsics */
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Disable global interrupts.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
void CpuIrqDisable(void)
|
||||||
|
{
|
||||||
|
__disable_interrupt();
|
||||||
|
} /*** end of CpuIrqDisable ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Enable global interrupts.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
void CpuIrqEnable(void)
|
||||||
|
{
|
||||||
|
__enable_interrupt();
|
||||||
|
} /*** end of CpuIrqEnable ***/
|
||||||
|
|
||||||
|
/*********************************** end of cpu_comp.c *********************************/
|
||||||
56
Boot/ARMCM0_STM32G0/Keil/cpu_comp.c
Normal file
56
Boot/ARMCM0_STM32G0/Keil/cpu_comp.c
Normal file
@@ -0,0 +1,56 @@
|
|||||||
|
/************************************************************************************//**
|
||||||
|
* \file Source/ARMCM0_STM32G0/Keil/cpu_comp.c
|
||||||
|
* \brief Bootloader cpu module source file.
|
||||||
|
* \ingroup Target_ARMCM0_STM32G0
|
||||||
|
* \internal
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* C O P Y R I G H T
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* Copyright (c) 2019 by Feaser http://www.feaser.com All rights reserved
|
||||||
|
*
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* L I C E N S E
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as published by the Free
|
||||||
|
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||||
|
* version.
|
||||||
|
*
|
||||||
|
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||||
|
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||||
|
* PURPOSE. See the GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||||
|
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||||
|
*
|
||||||
|
* \endinternal
|
||||||
|
****************************************************************************************/
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Include files
|
||||||
|
****************************************************************************************/
|
||||||
|
#include "boot.h" /* bootloader generic header */
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Disable global interrupts.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
void CpuIrqDisable(void)
|
||||||
|
{
|
||||||
|
__asm volatile ("cpsid i");
|
||||||
|
} /*** end of CpuIrqDisable ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Enable global interrupts.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
void CpuIrqEnable(void)
|
||||||
|
{
|
||||||
|
__asm volatile ("cpsie i");
|
||||||
|
} /*** end of CpuIrqEnable ***/
|
||||||
|
|
||||||
|
/*********************************** end of cpu_comp.c *********************************/
|
||||||
387
Boot/ARMCM0_STM32G0/can.c
Normal file
387
Boot/ARMCM0_STM32G0/can.c
Normal file
@@ -0,0 +1,387 @@
|
|||||||
|
/************************************************************************************//**
|
||||||
|
* \file Source/ARMCM0_STM32G0/can.c
|
||||||
|
* \brief Bootloader CAN communication interface source file.
|
||||||
|
* \ingroup Target_ARMCM0_STM32G0
|
||||||
|
* \internal
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* C O P Y R I G H T
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* Copyright (c) 2021 by Feaser http://www.feaser.com All rights reserved
|
||||||
|
*
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* L I C E N S E
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as published by the Free
|
||||||
|
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||||
|
* version.
|
||||||
|
*
|
||||||
|
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||||
|
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||||
|
* PURPOSE. See the GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||||
|
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||||
|
*
|
||||||
|
* \endinternal
|
||||||
|
****************************************************************************************/
|
||||||
|
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Include files
|
||||||
|
****************************************************************************************/
|
||||||
|
#include "boot.h" /* bootloader generic header */
|
||||||
|
#if (BOOT_COM_CAN_ENABLE > 0)
|
||||||
|
#include "stm32g0xx.h" /* STM32 CPU and HAL header */
|
||||||
|
#include "stm32g0xx_ll_rcc.h" /* STM32 LL RCC header */
|
||||||
|
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Macro definitions
|
||||||
|
****************************************************************************************/
|
||||||
|
/** \brief Timeout for transmitting a CAN message in milliseconds. */
|
||||||
|
#define CAN_MSG_TX_TIMEOUT_MS (50u)
|
||||||
|
|
||||||
|
/* map the configured CAN channel index to the STM32's CAN peripheral */
|
||||||
|
#if (BOOT_COM_CAN_CHANNEL_INDEX == 0)
|
||||||
|
/** \brief Set CAN base address to CAN1. */
|
||||||
|
#define CAN_CHANNEL FDCAN1
|
||||||
|
#elif (BOOT_COM_CAN_CHANNEL_INDEX == 1)
|
||||||
|
/** \brief Set CAN base address to CAN2. */
|
||||||
|
#define CAN_CHANNEL FDCAN2
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Type definitions
|
||||||
|
****************************************************************************************/
|
||||||
|
/** \brief Structure type for grouping CAN bus timing related information. */
|
||||||
|
typedef struct t_can_bus_timing
|
||||||
|
{
|
||||||
|
blt_int8u tseg1; /**< CAN time segment 1 */
|
||||||
|
blt_int8u tseg2; /**< CAN time segment 2 */
|
||||||
|
} tCanBusTiming;
|
||||||
|
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Local constant declarations
|
||||||
|
****************************************************************************************/
|
||||||
|
/** \brief CAN bittiming table for dynamically calculating the bittiming settings.
|
||||||
|
* \details According to the CAN protocol 1 bit-time can be made up of between 8..25
|
||||||
|
* time quanta (TQ). The total TQ in a bit is SYNC + TSEG1 + TSEG2 with SYNC
|
||||||
|
* always being 1. The sample point is (SYNC + TSEG1) / (SYNC + TSEG1 + SEG2) *
|
||||||
|
* 100%. This array contains possible and valid time quanta configurations with
|
||||||
|
* a sample point between 68..78%.
|
||||||
|
*/
|
||||||
|
static const tCanBusTiming canTiming[] =
|
||||||
|
{
|
||||||
|
/* TQ | TSEG1 | TSEG2 | SP */
|
||||||
|
/* ------------------------- */
|
||||||
|
{ 5, 2 }, /* 8 | 5 | 2 | 75% */
|
||||||
|
{ 6, 2 }, /* 9 | 6 | 2 | 78% */
|
||||||
|
{ 6, 3 }, /* 10 | 6 | 3 | 70% */
|
||||||
|
{ 7, 3 }, /* 11 | 7 | 3 | 73% */
|
||||||
|
{ 8, 3 }, /* 12 | 8 | 3 | 75% */
|
||||||
|
{ 9, 3 }, /* 13 | 9 | 3 | 77% */
|
||||||
|
{ 9, 4 }, /* 14 | 9 | 4 | 71% */
|
||||||
|
{ 10, 4 }, /* 15 | 10 | 4 | 73% */
|
||||||
|
{ 11, 4 }, /* 16 | 11 | 4 | 75% */
|
||||||
|
{ 12, 4 }, /* 17 | 12 | 4 | 76% */
|
||||||
|
{ 12, 5 }, /* 18 | 12 | 5 | 72% */
|
||||||
|
{ 13, 5 }, /* 19 | 13 | 5 | 74% */
|
||||||
|
{ 14, 5 }, /* 20 | 14 | 5 | 75% */
|
||||||
|
{ 15, 5 }, /* 21 | 15 | 5 | 76% */
|
||||||
|
{ 15, 6 }, /* 22 | 15 | 6 | 73% */
|
||||||
|
{ 16, 6 }, /* 23 | 16 | 6 | 74% */
|
||||||
|
{ 16, 7 }, /* 24 | 16 | 7 | 71% */
|
||||||
|
{ 16, 8 } /* 25 | 16 | 8 | 68% */
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Local data declarations
|
||||||
|
****************************************************************************************/
|
||||||
|
/** \brief CAN handle to be used in API calls. */
|
||||||
|
static FDCAN_HandleTypeDef canHandle;
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Search algorithm to match the desired baudrate to a possible bus
|
||||||
|
** timing configuration.
|
||||||
|
** \param baud The desired baudrate in kbps. Valid values are 10..1000.
|
||||||
|
** \param prescaler Pointer to where the value for the prescaler will be stored.
|
||||||
|
** \param tseg1 Pointer to where the value for TSEG2 will be stored.
|
||||||
|
** \param tseg2 Pointer to where the value for TSEG2 will be stored.
|
||||||
|
** \return BLT_TRUE if the CAN bustiming register values were found, BLT_FALSE
|
||||||
|
** otherwise.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
static blt_bool CanGetSpeedConfig(blt_int16u baud, blt_int16u *prescaler,
|
||||||
|
blt_int8u *tseg1, blt_int8u *tseg2)
|
||||||
|
{
|
||||||
|
blt_int8u cnt;
|
||||||
|
blt_int32u canClockFreqkHz;
|
||||||
|
|
||||||
|
/* obtain the CAN peripheral clock frequency in kHz. note that it is up to the user
|
||||||
|
* to configure the desired CAN clock source. By default it is PCLK1. Alternatives
|
||||||
|
* are HSE or PLLQ. To meet the clock tolerance requirement of CAN 2.0B, an external
|
||||||
|
* crystal oscillator (HSE) is recommended.
|
||||||
|
* whichever CAN clock source is selected, make sure that it is not higher than 48 MHz.
|
||||||
|
* a multiple of 8 MHz gives the best support for most commonly used CAN baudrates, so
|
||||||
|
* that is recommended.
|
||||||
|
*/
|
||||||
|
canClockFreqkHz = LL_RCC_GetFDCANClockFreq(LL_RCC_FDCAN_CLKSOURCE) / 1000u;
|
||||||
|
/* the CAN clock source should not be higher than 48 MHz. so only continue if this is
|
||||||
|
* the case.
|
||||||
|
*/
|
||||||
|
if (canClockFreqkHz <= 48000u)
|
||||||
|
{
|
||||||
|
/* loop through all possible time quanta configurations to find a match */
|
||||||
|
for (cnt=0; cnt < sizeof(canTiming)/sizeof(canTiming[0]); cnt++)
|
||||||
|
{
|
||||||
|
if ((canClockFreqkHz % (baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1))) == 0)
|
||||||
|
{
|
||||||
|
/* compute the prescaler that goes with this TQ configuration */
|
||||||
|
*prescaler = canClockFreqkHz/(baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1));
|
||||||
|
|
||||||
|
/* make sure the prescaler is valid */
|
||||||
|
if ((*prescaler > 0) && (*prescaler <= 512))
|
||||||
|
{
|
||||||
|
/* store the bustiming configuration */
|
||||||
|
*tseg1 = canTiming[cnt].tseg1;
|
||||||
|
*tseg2 = canTiming[cnt].tseg2;
|
||||||
|
/* found a good bus timing configuration */
|
||||||
|
return BLT_TRUE;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/* could not find a good bus timing configuration */
|
||||||
|
return BLT_FALSE;
|
||||||
|
} /*** end of CanGetSpeedConfig ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Initializes the CAN controller and synchronizes it to the CAN bus.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
void CanInit(void)
|
||||||
|
{
|
||||||
|
blt_int16u prescaler = 0;
|
||||||
|
blt_int8u tseg1 = 0, tseg2 = 0;
|
||||||
|
blt_int32u rxMsgId = BOOT_COM_CAN_RX_MSG_ID;
|
||||||
|
FDCAN_FilterTypeDef filterConfig;
|
||||||
|
|
||||||
|
/* the current implementation supports CAN1, 2 and 3. throw an assertion error in case
|
||||||
|
* a different CAN channel is configured.
|
||||||
|
*/
|
||||||
|
ASSERT_CT((BOOT_COM_CAN_CHANNEL_INDEX == 0) ||
|
||||||
|
(BOOT_COM_CAN_CHANNEL_INDEX == 1));
|
||||||
|
|
||||||
|
/* obtain bittiming configuration information. */
|
||||||
|
if (CanGetSpeedConfig(BOOT_COM_CAN_BAUDRATE/1000, &prescaler, &tseg1, &tseg2) == BLT_FALSE)
|
||||||
|
{
|
||||||
|
/* Incorrect configuration. The specified baudrate is not supported for the given
|
||||||
|
* clock configuration. Verify the following settings in blt_conf.h:
|
||||||
|
* - BOOT_COM_CAN_BAUDRATE
|
||||||
|
* - BOOT_CPU_XTAL_SPEED_KHZ
|
||||||
|
* - BOOT_CPU_SYSTEM_SPEED_KHZ
|
||||||
|
*/
|
||||||
|
ASSERT_RT(BLT_FALSE);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* set the CAN controller configuration. */
|
||||||
|
canHandle.Instance = CAN_CHANNEL;
|
||||||
|
canHandle.Init.ClockDivider = FDCAN_CLOCK_DIV1;
|
||||||
|
canHandle.Init.FrameFormat = FDCAN_FRAME_CLASSIC;
|
||||||
|
canHandle.Init.Mode = FDCAN_MODE_NORMAL;
|
||||||
|
canHandle.Init.AutoRetransmission = ENABLE;
|
||||||
|
canHandle.Init.TransmitPause = DISABLE;
|
||||||
|
canHandle.Init.ProtocolException = DISABLE;
|
||||||
|
canHandle.Init.NominalPrescaler = prescaler;
|
||||||
|
canHandle.Init.NominalSyncJumpWidth = 1;
|
||||||
|
canHandle.Init.NominalTimeSeg1 = tseg1;
|
||||||
|
canHandle.Init.NominalTimeSeg2 = tseg2;
|
||||||
|
/* FD mode is not used by this driver, so the .Init.DataXxx values are don't care. */
|
||||||
|
canHandle.Init.DataPrescaler = 1;
|
||||||
|
canHandle.Init.DataSyncJumpWidth = 1;
|
||||||
|
canHandle.Init.DataTimeSeg1 = 1;
|
||||||
|
canHandle.Init.DataTimeSeg2 = 1;
|
||||||
|
/* does the message to be received have a standard 11-bit CAN identifier? */
|
||||||
|
if ((rxMsgId & 0x80000000) == 0)
|
||||||
|
{
|
||||||
|
canHandle.Init.StdFiltersNbr = 1;
|
||||||
|
canHandle.Init.ExtFiltersNbr = 0;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
canHandle.Init.StdFiltersNbr = 0;
|
||||||
|
canHandle.Init.ExtFiltersNbr = 1;
|
||||||
|
}
|
||||||
|
canHandle.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
|
||||||
|
/* initialize the CAN controller. this only fails if the CAN controller hardware is
|
||||||
|
* faulty. no need to evaluate the return value as there is nothing we can do about
|
||||||
|
* a faulty CAN controller.
|
||||||
|
*/
|
||||||
|
(void)HAL_FDCAN_Init(&canHandle);
|
||||||
|
|
||||||
|
/* configure the reception filter. note that the implementation of this function
|
||||||
|
* always returns HAL_OK as long as the CAN controller is initialized, so no need to
|
||||||
|
* evaluate the return value.
|
||||||
|
*/
|
||||||
|
if ((rxMsgId & 0x80000000) == 0)
|
||||||
|
{
|
||||||
|
filterConfig.IdType = FDCAN_STANDARD_ID;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
filterConfig.IdType = FDCAN_EXTENDED_ID;
|
||||||
|
/* negate the ID-type bit */
|
||||||
|
rxMsgId &= ~0x80000000;
|
||||||
|
}
|
||||||
|
filterConfig.FilterIndex = 0;
|
||||||
|
filterConfig.FilterType = FDCAN_FILTER_DUAL;
|
||||||
|
filterConfig.FilterConfig = FDCAN_FILTER_TO_RXFIFO0;
|
||||||
|
filterConfig.FilterID1 = rxMsgId;
|
||||||
|
filterConfig.FilterID2 = rxMsgId;
|
||||||
|
(void)HAL_FDCAN_ConfigFilter(&canHandle, &filterConfig);
|
||||||
|
|
||||||
|
/* configure global filter to reject all non-matching frames. */
|
||||||
|
HAL_FDCAN_ConfigGlobalFilter(&canHandle, FDCAN_REJECT, FDCAN_REJECT,
|
||||||
|
FDCAN_REJECT_REMOTE, FDCAN_REJECT_REMOTE);
|
||||||
|
|
||||||
|
/* start the CAN peripheral. no need to evaluate the return value as there is nothing
|
||||||
|
* we can do about a faulty CAN controller. */
|
||||||
|
(void)HAL_FDCAN_Start(&canHandle);
|
||||||
|
} /*** end of CanInit ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Transmits a packet formatted for the communication interface.
|
||||||
|
** \param data Pointer to byte array with data that it to be transmitted.
|
||||||
|
** \param len Number of bytes that are to be transmitted.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
void CanTransmitPacket(blt_int8u *data, blt_int8u len)
|
||||||
|
{
|
||||||
|
blt_int32u txMsgId = BOOT_COM_CAN_TX_MSG_ID;
|
||||||
|
FDCAN_TxHeaderTypeDef txMsgHeader;
|
||||||
|
blt_int32u timeout;
|
||||||
|
HAL_StatusTypeDef status;
|
||||||
|
blt_int32u txMsgBuffer;
|
||||||
|
|
||||||
|
/* configure the message that should be transmitted. */
|
||||||
|
if ((txMsgId & 0x80000000) == 0)
|
||||||
|
{
|
||||||
|
/* set the 11-bit CAN identifier. */
|
||||||
|
txMsgHeader.Identifier = txMsgId;
|
||||||
|
txMsgHeader.IdType = FDCAN_STANDARD_ID;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* negate the ID-type bit. */
|
||||||
|
txMsgId &= ~0x80000000;
|
||||||
|
/* set the 29-bit CAN identifier. */
|
||||||
|
txMsgHeader.Identifier = txMsgId;
|
||||||
|
txMsgHeader.IdType = FDCAN_EXTENDED_ID;
|
||||||
|
}
|
||||||
|
txMsgHeader.TxFrameType = FDCAN_DATA_FRAME;
|
||||||
|
txMsgHeader.DataLength = len << 16U;
|
||||||
|
txMsgHeader.ErrorStateIndicator = FDCAN_ESI_ACTIVE;
|
||||||
|
txMsgHeader.BitRateSwitch = FDCAN_BRS_OFF;
|
||||||
|
txMsgHeader.FDFormat = FDCAN_CLASSIC_CAN;
|
||||||
|
txMsgHeader.TxEventFifoControl = FDCAN_NO_TX_EVENTS;
|
||||||
|
txMsgHeader.MessageMarker = 0x52;
|
||||||
|
|
||||||
|
/* add the message to the transmit FIFO to request its transmission. */
|
||||||
|
status = HAL_FDCAN_AddMessageToTxFifoQ(&canHandle, &txMsgHeader, data);
|
||||||
|
/* read out which FIFO buffer was used for the last transmit request. */
|
||||||
|
txMsgBuffer = HAL_FDCAN_GetLatestTxFifoQRequestBuffer(&canHandle);
|
||||||
|
|
||||||
|
/* only continue with polling for transmit completion if the message transmit request
|
||||||
|
* could be submitted to a valid FIFO buffer.
|
||||||
|
*/
|
||||||
|
if ((status == HAL_OK) && (txMsgBuffer != 0))
|
||||||
|
{
|
||||||
|
/* determine timeout time for the transmit completion. */
|
||||||
|
timeout = TimerGet() + CAN_MSG_TX_TIMEOUT_MS;
|
||||||
|
/* poll for completion of the transmit operation. */
|
||||||
|
while (HAL_FDCAN_IsTxBufferMessagePending(&canHandle, txMsgBuffer) != 0)
|
||||||
|
{
|
||||||
|
/* service the watchdog. */
|
||||||
|
CopService();
|
||||||
|
/* break loop upon timeout. this would indicate a hardware failure or no other
|
||||||
|
* nodes connected to the bus.
|
||||||
|
*/
|
||||||
|
if (TimerGet() > timeout)
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
} /*** end of CanTransmitPacket ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Receives a communication interface packet if one is present.
|
||||||
|
** \param data Pointer to byte array where the data is to be stored.
|
||||||
|
** \param len Pointer where the length of the packet is to be stored.
|
||||||
|
** \return BLT_TRUE is a packet was received, BLT_FALSE otherwise.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
blt_bool CanReceivePacket(blt_int8u *data, blt_int8u *len)
|
||||||
|
{
|
||||||
|
blt_bool result = BLT_FALSE;
|
||||||
|
blt_int32u rxMsgId = BOOT_COM_CAN_RX_MSG_ID;
|
||||||
|
FDCAN_RxHeaderTypeDef rxMsgHeader;
|
||||||
|
HAL_StatusTypeDef rxStatus = HAL_ERROR;
|
||||||
|
|
||||||
|
/* check if the expected CAN message was received? */
|
||||||
|
if (HAL_FDCAN_GetRxFifoFillLevel(&canHandle, FDCAN_RX_FIFO0) > 0)
|
||||||
|
{
|
||||||
|
/* attempt to read the newly received CAN message from its buffer. */
|
||||||
|
rxStatus = HAL_FDCAN_GetRxMessage(&canHandle, FDCAN_RX_FIFO0, &rxMsgHeader, data);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* only continue processing the CAN message if something was received. */
|
||||||
|
if (rxStatus == HAL_OK)
|
||||||
|
{
|
||||||
|
/* check if this message has the configured CAN packet identifier. */
|
||||||
|
if ((rxMsgId & 0x80000000) == 0)
|
||||||
|
{
|
||||||
|
/* was an 11-bit CAN message received that matches? */
|
||||||
|
if ( (rxMsgHeader.Identifier == rxMsgId) &&
|
||||||
|
(rxMsgHeader.IdType == FDCAN_STANDARD_ID) )
|
||||||
|
{
|
||||||
|
/* set flag that a packet with a matching CAN identifier was received. */
|
||||||
|
result = BLT_TRUE;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* negate the ID-type bit. */
|
||||||
|
rxMsgId &= ~0x80000000;
|
||||||
|
/* was an 29-bit CAN message received that matches? */
|
||||||
|
if ( (rxMsgHeader.Identifier == rxMsgId) &&
|
||||||
|
(rxMsgHeader.IdType == FDCAN_EXTENDED_ID) )
|
||||||
|
{
|
||||||
|
/* set flag that a packet with a matching CAN identifier was received. */
|
||||||
|
result = BLT_TRUE;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/* store the data length. */
|
||||||
|
if (result == BLT_TRUE)
|
||||||
|
{
|
||||||
|
*len = (blt_int8u)(rxMsgHeader.DataLength >> 16U);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* give the result back to the caller. */
|
||||||
|
return result;
|
||||||
|
} /*** end of CanReceivePacket ***/
|
||||||
|
#endif /* BOOT_COM_CAN_ENABLE > 0 */
|
||||||
|
|
||||||
|
|
||||||
|
/*********************************** end of can.c **************************************/
|
||||||
196
Boot/ARMCM0_STM32G0/cpu.c
Normal file
196
Boot/ARMCM0_STM32G0/cpu.c
Normal file
@@ -0,0 +1,196 @@
|
|||||||
|
/************************************************************************************//**
|
||||||
|
* \file Source/ARMCM0_STM32G0/cpu.c
|
||||||
|
* \brief Bootloader cpu module source file.
|
||||||
|
* \ingroup Target_ARMCM0_STM32G0
|
||||||
|
* \internal
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* C O P Y R I G H T
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* Copyright (c) 2019 by Feaser http://www.feaser.com All rights reserved
|
||||||
|
*
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* L I C E N S E
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as published by the Free
|
||||||
|
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||||
|
* version.
|
||||||
|
*
|
||||||
|
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||||
|
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||||
|
* PURPOSE. See the GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||||
|
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||||
|
*
|
||||||
|
* \endinternal
|
||||||
|
****************************************************************************************/
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Include files
|
||||||
|
****************************************************************************************/
|
||||||
|
#include "boot.h" /* bootloader generic header */
|
||||||
|
#include "stm32g0xx.h" /* STM32 CPU and HAL header */
|
||||||
|
#include "stm32g0xx_ll_bus.h" /* STM32 LL BUS header */
|
||||||
|
#include "stm32g0xx_ll_system.h" /* STM32 LL SYSTEM header */
|
||||||
|
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Macro definitions
|
||||||
|
****************************************************************************************/
|
||||||
|
/** \brief Pointer to the user program's reset vector. */
|
||||||
|
#define CPU_USER_PROGRAM_STARTADDR_PTR ((blt_addr)(NvmGetUserProgBaseAddress() + 0x00000004))
|
||||||
|
/** \brief Pointer to the user program's vector table. */
|
||||||
|
#define CPU_USER_PROGRAM_VECTABLE_OFFSET ((blt_int32u)NvmGetUserProgBaseAddress())
|
||||||
|
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Hook functions
|
||||||
|
****************************************************************************************/
|
||||||
|
#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0)
|
||||||
|
extern blt_bool CpuUserProgramStartHook(void);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Initializes the CPU module.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
void CpuInit(void)
|
||||||
|
{
|
||||||
|
/* bootloader runs in polling mode so disable the global interrupts. this is done for
|
||||||
|
* safety reasons. if the bootloader was started from a running user program, it could
|
||||||
|
* be that the user program did not properly disable the interrupt generation of
|
||||||
|
* peripherals. */
|
||||||
|
CpuIrqDisable();
|
||||||
|
} /*** end of CpuInit ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Starts the user program, if one is present. In this case this function
|
||||||
|
** does not return.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
void CpuStartUserProgram(void)
|
||||||
|
{
|
||||||
|
void (*pProgResetHandler)(void);
|
||||||
|
|
||||||
|
/* check if a user program is present by verifying the checksum */
|
||||||
|
if (NvmVerifyChecksum() == BLT_FALSE)
|
||||||
|
{
|
||||||
|
#if (BOOT_COM_DEFERRED_INIT_ENABLE > 0) && (BOOT_COM_ENABLE > 0)
|
||||||
|
/* bootloader will stay active so perform deferred initialization to make sure
|
||||||
|
* the communication interface that were not yet initialized are now initialized.
|
||||||
|
* this is needed to make sure firmware updates via these communication interfaces
|
||||||
|
* will be possible.
|
||||||
|
*/
|
||||||
|
ComDeferredInit();
|
||||||
|
#endif
|
||||||
|
/* not a valid user program so it cannot be started */
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0)
|
||||||
|
/* invoke callback */
|
||||||
|
if (CpuUserProgramStartHook() == BLT_FALSE)
|
||||||
|
{
|
||||||
|
#if (BOOT_COM_DEFERRED_INIT_ENABLE > 0) && (BOOT_COM_ENABLE > 0)
|
||||||
|
/* bootloader will stay active so perform deferred initialization to make sure
|
||||||
|
* the communication interface that were not yet initialized are now initialized.
|
||||||
|
* this is needed to make sure firmware updates via these communication interfaces
|
||||||
|
* will be possible.
|
||||||
|
*/
|
||||||
|
ComDeferredInit();
|
||||||
|
#endif
|
||||||
|
/* callback requests the user program to not be started */
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
#if (BOOT_COM_ENABLE > 0)
|
||||||
|
/* release the communication interface */
|
||||||
|
ComFree();
|
||||||
|
#endif
|
||||||
|
/* reset the HAL */
|
||||||
|
HAL_DeInit();
|
||||||
|
/* reset the timer */
|
||||||
|
TimerReset();
|
||||||
|
/* remap user program's vector table */
|
||||||
|
SCB->VTOR = CPU_USER_PROGRAM_VECTABLE_OFFSET & (blt_int32u)0x1FFFFF80;
|
||||||
|
/* set the address where the bootloader needs to jump to. this is the address of
|
||||||
|
* the 2nd entry in the user program's vector table. this address points to the
|
||||||
|
* user program's reset handler.
|
||||||
|
*/
|
||||||
|
pProgResetHandler = (void(*)(void))(*((blt_addr *)CPU_USER_PROGRAM_STARTADDR_PTR));
|
||||||
|
/* the Cortex-M0+ core has interrupts enabled out of reset. the bootloader
|
||||||
|
* explicitly disables these for security reasons. Enable them here again, so it does
|
||||||
|
* not have to be done by the user program.
|
||||||
|
*/
|
||||||
|
CpuIrqEnable();
|
||||||
|
/* start the user program by activating its reset interrupt service routine */
|
||||||
|
pProgResetHandler();
|
||||||
|
#if (BOOT_COM_DEFERRED_INIT_ENABLE > 0) && (BOOT_COM_ENABLE > 0)
|
||||||
|
/* theoretically, the code never gets here because the user program should now be
|
||||||
|
* running and the previous function call should not return. In case it did return
|
||||||
|
* for whatever reason, make sure all communication interfaces are initialized so that
|
||||||
|
* firmware updates can be started.
|
||||||
|
*/
|
||||||
|
ComDeferredInit();
|
||||||
|
#endif
|
||||||
|
} /*** end of CpuStartUserProgram ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Copies data from the source to the destination address.
|
||||||
|
** \param dest Destination address for the data.
|
||||||
|
** \param src Source address of the data.
|
||||||
|
** \param len length of the data in bytes.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
void CpuMemCopy(blt_addr dest, blt_addr src, blt_int16u len)
|
||||||
|
{
|
||||||
|
blt_int8u *from, *to;
|
||||||
|
|
||||||
|
/* set casted pointers */
|
||||||
|
from = (blt_int8u *)src;
|
||||||
|
to = (blt_int8u *)dest;
|
||||||
|
|
||||||
|
/* copy all bytes from source address to destination address */
|
||||||
|
while (len-- > 0)
|
||||||
|
{
|
||||||
|
/* store byte value from source to destination */
|
||||||
|
*to++ = *from++;
|
||||||
|
/* keep the watchdog happy */
|
||||||
|
CopService();
|
||||||
|
}
|
||||||
|
} /*** end of CpuMemCopy ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Sets the bytes at the destination address to the specified value.
|
||||||
|
** \param dest Destination address for the data.
|
||||||
|
** \param value Value to write.
|
||||||
|
** \param len Number of bytes to write.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
void CpuMemSet(blt_addr dest, blt_int8u value, blt_int16u len)
|
||||||
|
{
|
||||||
|
blt_int8u *to;
|
||||||
|
|
||||||
|
/* set casted pointer */
|
||||||
|
to = (blt_int8u *)dest;
|
||||||
|
|
||||||
|
/* set all bytes at the destination address to the specified value */
|
||||||
|
while (len-- > 0)
|
||||||
|
{
|
||||||
|
/* set byte value */
|
||||||
|
*to++ = value;
|
||||||
|
/* keep the watchdog happy */
|
||||||
|
CopService();
|
||||||
|
}
|
||||||
|
} /*** end of CpuMemSet ***/
|
||||||
|
|
||||||
|
|
||||||
|
/*********************************** end of cpu.c **************************************/
|
||||||
1008
Boot/ARMCM0_STM32G0/flash.c
Normal file
1008
Boot/ARMCM0_STM32G0/flash.c
Normal file
File diff suppressed because it is too large
Load Diff
45
Boot/ARMCM0_STM32G0/flash.h
Normal file
45
Boot/ARMCM0_STM32G0/flash.h
Normal file
@@ -0,0 +1,45 @@
|
|||||||
|
/************************************************************************************//**
|
||||||
|
* \file Source/ARMCM0_STM32G0/flash.h
|
||||||
|
* \brief Bootloader flash driver header file.
|
||||||
|
* \ingroup Target_ARMCM0_STM32G0
|
||||||
|
* \internal
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* C O P Y R I G H T
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* Copyright (c) 2019 by Feaser http://www.feaser.com All rights reserved
|
||||||
|
*
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* L I C E N S E
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as published by the Free
|
||||||
|
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||||
|
* version.
|
||||||
|
*
|
||||||
|
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||||
|
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||||
|
* PURPOSE. See the GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||||
|
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||||
|
*
|
||||||
|
* \endinternal
|
||||||
|
****************************************************************************************/
|
||||||
|
#ifndef FLASH_H
|
||||||
|
#define FLASH_H
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Function prototypes
|
||||||
|
****************************************************************************************/
|
||||||
|
void FlashInit(void);
|
||||||
|
void FlashReinit(void);
|
||||||
|
blt_bool FlashWrite(blt_addr addr, blt_int32u len, blt_int8u *data);
|
||||||
|
blt_bool FlashErase(blt_addr addr, blt_int32u len);
|
||||||
|
blt_bool FlashWriteChecksum(void);
|
||||||
|
blt_bool FlashVerifyChecksum(void);
|
||||||
|
blt_bool FlashDone(void);
|
||||||
|
blt_addr FlashGetUserProgBaseAddress(void);
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* FLASH_H */
|
||||||
|
/*********************************** end of flash.h ************************************/
|
||||||
245
Boot/ARMCM0_STM32G0/nvm.c
Normal file
245
Boot/ARMCM0_STM32G0/nvm.c
Normal file
@@ -0,0 +1,245 @@
|
|||||||
|
/************************************************************************************//**
|
||||||
|
* \file Source/ARMCM0_STM32G0/nvm.c
|
||||||
|
* \brief Bootloader non-volatile memory driver source file.
|
||||||
|
* \ingroup Target_ARMCM0_STM32G0
|
||||||
|
* \internal
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* C O P Y R I G H T
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* Copyright (c) 2019 by Feaser http://www.feaser.com All rights reserved
|
||||||
|
*
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* L I C E N S E
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as published by the Free
|
||||||
|
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||||
|
* version.
|
||||||
|
*
|
||||||
|
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||||
|
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||||
|
* PURPOSE. See the GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||||
|
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||||
|
*
|
||||||
|
* \endinternal
|
||||||
|
****************************************************************************************/
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Include files
|
||||||
|
****************************************************************************************/
|
||||||
|
#include "boot.h" /* bootloader generic header */
|
||||||
|
#include "flash.h"
|
||||||
|
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Hook functions
|
||||||
|
****************************************************************************************/
|
||||||
|
#if (BOOT_NVM_HOOKS_ENABLE > 0)
|
||||||
|
extern void NvmInitHook(void);
|
||||||
|
extern void NvmReinitHook(void);
|
||||||
|
extern blt_int8u NvmWriteHook(blt_addr addr, blt_int32u len, blt_int8u *data);
|
||||||
|
extern blt_int8u NvmEraseHook(blt_addr addr, blt_int32u len);
|
||||||
|
extern blt_bool NvmDoneHook(void);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0)
|
||||||
|
extern blt_bool NvmWriteChecksumHook(void);
|
||||||
|
extern blt_bool NvmVerifyChecksumHook(void);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Initializes the NVM driver.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
void NvmInit(void)
|
||||||
|
{
|
||||||
|
#if (BOOT_NVM_HOOKS_ENABLE > 0)
|
||||||
|
/* give the application a chance to initialize a driver for operating on NVM
|
||||||
|
* that is not by default supported by this driver.
|
||||||
|
*/
|
||||||
|
NvmInitHook();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* init the internal driver */
|
||||||
|
FlashInit();
|
||||||
|
} /*** end of NvmInit ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Reinitializes the NVM driver. This function is called at the start of each
|
||||||
|
** firmware update as opposed to NvmInit, which is only called once during
|
||||||
|
** power on.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
void NvmReinit(void)
|
||||||
|
{
|
||||||
|
#if (BOOT_NVM_HOOKS_ENABLE > 0)
|
||||||
|
/* give the application a chance to re-initialize a driver for operating on NVM
|
||||||
|
* that is not by default supported by this driver.
|
||||||
|
*/
|
||||||
|
NvmReinitHook();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* reinitialize the internal driver */
|
||||||
|
FlashReinit();
|
||||||
|
} /*** end of NvmReinit ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Programs the non-volatile memory.
|
||||||
|
** \param addr Start address.
|
||||||
|
** \param len Length in bytes.
|
||||||
|
** \param data Pointer to the data buffer.
|
||||||
|
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
blt_bool NvmWrite(blt_addr addr, blt_int32u len, blt_int8u *data)
|
||||||
|
{
|
||||||
|
#if (BOOT_NVM_HOOKS_ENABLE > 0)
|
||||||
|
blt_int8u result = BLT_NVM_NOT_IN_RANGE;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (BOOT_NVM_HOOKS_ENABLE > 0)
|
||||||
|
/* give the application a chance to operate on memory that is not by default supported
|
||||||
|
* by this driver.
|
||||||
|
*/
|
||||||
|
result = NvmWriteHook(addr, len, data);
|
||||||
|
|
||||||
|
/* process the return code */
|
||||||
|
if (result == BLT_NVM_OKAY)
|
||||||
|
{
|
||||||
|
/* data was within range of the additionally supported memory and succesfully
|
||||||
|
* programmed, so we are all done.
|
||||||
|
*/
|
||||||
|
return BLT_TRUE;
|
||||||
|
}
|
||||||
|
else if (result == BLT_NVM_ERROR)
|
||||||
|
{
|
||||||
|
/* data was within range of the additionally supported memory and attempted to be
|
||||||
|
* programmed, but an error occurred, so we can't continue.
|
||||||
|
*/
|
||||||
|
return BLT_FALSE;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* still here so the internal driver should try and perform the program operation */
|
||||||
|
return FlashWrite(addr, len, data);
|
||||||
|
} /*** end of NvmWrite ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Erases the non-volatile memory.
|
||||||
|
** \param addr Start address.
|
||||||
|
** \param len Length in bytes.
|
||||||
|
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
blt_bool NvmErase(blt_addr addr, blt_int32u len)
|
||||||
|
{
|
||||||
|
#if (BOOT_NVM_HOOKS_ENABLE > 0)
|
||||||
|
blt_int8u result = BLT_NVM_NOT_IN_RANGE;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (BOOT_NVM_HOOKS_ENABLE > 0)
|
||||||
|
/* give the application a chance to operate on memory that is not by default supported
|
||||||
|
* by this driver.
|
||||||
|
*/
|
||||||
|
result = NvmEraseHook(addr, len);
|
||||||
|
|
||||||
|
/* process the return code */
|
||||||
|
if (result == BLT_NVM_OKAY)
|
||||||
|
{
|
||||||
|
/* address was within range of the additionally supported memory and succesfully
|
||||||
|
* erased, so we are all done.
|
||||||
|
*/
|
||||||
|
return BLT_TRUE;
|
||||||
|
}
|
||||||
|
else if (result == BLT_NVM_ERROR)
|
||||||
|
{
|
||||||
|
/* address was within range of the additionally supported memory and attempted to be
|
||||||
|
* erased, but an error occurred, so we can't continue.
|
||||||
|
*/
|
||||||
|
return BLT_FALSE;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* still here so the internal driver should try and perform the erase operation */
|
||||||
|
return FlashErase(addr, len);
|
||||||
|
} /*** end of NvmErase ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Verifies the checksum, which indicates that a valid user program is
|
||||||
|
** present and can be started.
|
||||||
|
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
blt_bool NvmVerifyChecksum(void)
|
||||||
|
{
|
||||||
|
#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0)
|
||||||
|
/* check checksum using the application specific method. */
|
||||||
|
return NvmVerifyChecksumHook();
|
||||||
|
#else
|
||||||
|
/* check checksum using the interally supported method. */
|
||||||
|
return FlashVerifyChecksum();
|
||||||
|
#endif
|
||||||
|
} /*** end of NvmVerifyChecksum ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Obtains the base address of the non-volatile memory available to the user
|
||||||
|
** program. This is typically that start of the vector table.
|
||||||
|
** \return Base address.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
blt_addr NvmGetUserProgBaseAddress(void)
|
||||||
|
{
|
||||||
|
return FlashGetUserProgBaseAddress();
|
||||||
|
} /*** end of NvmGetUserProgBaseAddress ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Once all erase and programming operations are completed, this
|
||||||
|
** function is called, so at the end of the programming session and
|
||||||
|
** right before a software reset is performed. It is used to calculate
|
||||||
|
** a checksum and program this into flash. This checksum is later used
|
||||||
|
** to determine if a valid user program is present in flash.
|
||||||
|
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
blt_bool NvmDone(void)
|
||||||
|
{
|
||||||
|
#if (BOOT_NVM_HOOKS_ENABLE > 0)
|
||||||
|
/* give the application's NVM driver a chance to finish up */
|
||||||
|
if (NvmDoneHook() == BLT_FALSE)
|
||||||
|
{
|
||||||
|
/* error so no need to continue */
|
||||||
|
return BLT_FALSE;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0)
|
||||||
|
/* compute and write checksum, using the application specific method. */
|
||||||
|
if (NvmWriteChecksumHook() == BLT_FALSE)
|
||||||
|
{
|
||||||
|
return BLT_FALSE;
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
/* compute and write checksum, which is programmed by the internal driver. */
|
||||||
|
if (FlashWriteChecksum() == BLT_FALSE)
|
||||||
|
{
|
||||||
|
return BLT_FALSE;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* finish up internal driver operations */
|
||||||
|
return FlashDone();
|
||||||
|
} /*** end of NvmDone ***/
|
||||||
|
|
||||||
|
|
||||||
|
/*********************************** end of nvm.c **************************************/
|
||||||
257
Boot/ARMCM0_STM32G0/rs232.c
Normal file
257
Boot/ARMCM0_STM32G0/rs232.c
Normal file
@@ -0,0 +1,257 @@
|
|||||||
|
/************************************************************************************//**
|
||||||
|
* \file Source/ARMCM0_STM32G0/rs232.c
|
||||||
|
* \brief Bootloader RS232 communication interface source file.
|
||||||
|
* \ingroup Target_ARMCM0_STM32G0
|
||||||
|
* \internal
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* C O P Y R I G H T
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* Copyright (c) 2019 by Feaser http://www.feaser.com All rights reserved
|
||||||
|
*
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* L I C E N S E
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as published by the Free
|
||||||
|
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||||
|
* version.
|
||||||
|
*
|
||||||
|
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||||
|
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||||
|
* PURPOSE. See the GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||||
|
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||||
|
*
|
||||||
|
* \endinternal
|
||||||
|
****************************************************************************************/
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Include files
|
||||||
|
****************************************************************************************/
|
||||||
|
#include "boot.h" /* bootloader generic header */
|
||||||
|
#if (BOOT_COM_RS232_ENABLE > 0)
|
||||||
|
#include "stm32g0xx.h" /* STM32 CPU and HAL header */
|
||||||
|
#include "stm32g0xx_ll_usart.h" /* STM32 LL USART header */
|
||||||
|
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Macro definitions
|
||||||
|
****************************************************************************************/
|
||||||
|
/** \brief Timeout time for the reception of a CTO packet. The timer is started upon
|
||||||
|
* reception of the first packet byte.
|
||||||
|
*/
|
||||||
|
#define RS232_CTO_RX_PACKET_TIMEOUT_MS (100u)
|
||||||
|
/** \brief Timeout for transmitting a byte in milliseconds. */
|
||||||
|
#define RS232_BYTE_TX_TIMEOUT_MS (10u)
|
||||||
|
|
||||||
|
/* map the configured UART channel index to the STM32's USART peripheral */
|
||||||
|
#if (BOOT_COM_RS232_CHANNEL_INDEX == 0)
|
||||||
|
/** \brief Set UART base address to USART1. */
|
||||||
|
#define USART_CHANNEL USART1
|
||||||
|
#elif (BOOT_COM_RS232_CHANNEL_INDEX == 1)
|
||||||
|
/** \brief Set UART base address to USART2. */
|
||||||
|
#define USART_CHANNEL USART2
|
||||||
|
#elif (BOOT_COM_RS232_CHANNEL_INDEX == 2)
|
||||||
|
/** \brief Set UART base address to USART3. */
|
||||||
|
#define USART_CHANNEL USART3
|
||||||
|
#elif (BOOT_COM_RS232_CHANNEL_INDEX == 3)
|
||||||
|
/** \brief Set UART base address to USART4. */
|
||||||
|
#define USART_CHANNEL USART4
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Function prototypes
|
||||||
|
****************************************************************************************/
|
||||||
|
static blt_bool Rs232ReceiveByte(blt_int8u *data);
|
||||||
|
static void Rs232TransmitByte(blt_int8u data);
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Initializes the RS232 communication interface.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
void Rs232Init(void)
|
||||||
|
{
|
||||||
|
LL_USART_InitTypeDef USART_InitStruct;
|
||||||
|
|
||||||
|
/* the current implementation supports USART1 - USART4. throw an assertion error in
|
||||||
|
* case a different UART channel is configured.
|
||||||
|
*/
|
||||||
|
ASSERT_CT((BOOT_COM_RS232_CHANNEL_INDEX == 0) ||
|
||||||
|
(BOOT_COM_RS232_CHANNEL_INDEX == 1) ||
|
||||||
|
(BOOT_COM_RS232_CHANNEL_INDEX == 2) ||
|
||||||
|
(BOOT_COM_RS232_CHANNEL_INDEX == 3));
|
||||||
|
|
||||||
|
/* disable the UART peripheral */
|
||||||
|
LL_USART_Disable(USART_CHANNEL);
|
||||||
|
/* configure UART peripheral */
|
||||||
|
USART_InitStruct.BaudRate = BOOT_COM_RS232_BAUDRATE;
|
||||||
|
USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B;
|
||||||
|
USART_InitStruct.StopBits = LL_USART_STOPBITS_1;
|
||||||
|
USART_InitStruct.Parity = LL_USART_PARITY_NONE;
|
||||||
|
USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX;
|
||||||
|
USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE;
|
||||||
|
USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16;
|
||||||
|
USART_InitStruct.PrescalerValue = LL_USART_PRESCALER_DIV1;
|
||||||
|
|
||||||
|
/* initialize the UART peripheral */
|
||||||
|
LL_USART_Init(USART_CHANNEL, &USART_InitStruct);
|
||||||
|
LL_USART_Enable(USART_CHANNEL);
|
||||||
|
} /*** end of Rs232Init ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Transmits a packet formatted for the communication interface.
|
||||||
|
** \param data Pointer to byte array with data that it to be transmitted.
|
||||||
|
** \param len Number of bytes that are to be transmitted.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
void Rs232TransmitPacket(blt_int8u *data, blt_int8u len)
|
||||||
|
{
|
||||||
|
blt_int16u data_index;
|
||||||
|
|
||||||
|
/* verify validity of the len-paramenter */
|
||||||
|
ASSERT_RT(len <= BOOT_COM_RS232_TX_MAX_DATA);
|
||||||
|
|
||||||
|
/* first transmit the length of the packet */
|
||||||
|
Rs232TransmitByte(len);
|
||||||
|
|
||||||
|
/* transmit all the packet bytes one-by-one */
|
||||||
|
for (data_index = 0; data_index < len; data_index++)
|
||||||
|
{
|
||||||
|
/* keep the watchdog happy */
|
||||||
|
CopService();
|
||||||
|
/* write byte */
|
||||||
|
Rs232TransmitByte(data[data_index]);
|
||||||
|
}
|
||||||
|
} /*** end of Rs232TransmitPacket ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Receives a communication interface packet if one is present.
|
||||||
|
** \param data Pointer to byte array where the data is to be stored.
|
||||||
|
** \param len Pointer where the length of the packet is to be stored.
|
||||||
|
** \return BLT_TRUE if a packet was received, BLT_FALSE otherwise.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
blt_bool Rs232ReceivePacket(blt_int8u *data, blt_int8u *len)
|
||||||
|
{
|
||||||
|
static blt_int8u xcpCtoReqPacket[BOOT_COM_RS232_RX_MAX_DATA+1]; /* one extra for length */
|
||||||
|
static blt_int8u xcpCtoRxLength;
|
||||||
|
static blt_bool xcpCtoRxInProgress = BLT_FALSE;
|
||||||
|
static blt_int32u xcpCtoRxStartTime = 0;
|
||||||
|
|
||||||
|
/* start of cto packet received? */
|
||||||
|
if (xcpCtoRxInProgress == BLT_FALSE)
|
||||||
|
{
|
||||||
|
/* store the message length when received */
|
||||||
|
if (Rs232ReceiveByte(&xcpCtoReqPacket[0]) == BLT_TRUE)
|
||||||
|
{
|
||||||
|
if ( (xcpCtoReqPacket[0] > 0) &&
|
||||||
|
(xcpCtoReqPacket[0] <= BOOT_COM_RS232_RX_MAX_DATA) )
|
||||||
|
{
|
||||||
|
/* store the start time */
|
||||||
|
xcpCtoRxStartTime = TimerGet();
|
||||||
|
/* reset packet data count */
|
||||||
|
xcpCtoRxLength = 0;
|
||||||
|
/* indicate that a cto packet is being received */
|
||||||
|
xcpCtoRxInProgress = BLT_TRUE;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* store the next packet byte */
|
||||||
|
if (Rs232ReceiveByte(&xcpCtoReqPacket[xcpCtoRxLength+1]) == BLT_TRUE)
|
||||||
|
{
|
||||||
|
/* increment the packet data count */
|
||||||
|
xcpCtoRxLength++;
|
||||||
|
|
||||||
|
/* check to see if the entire packet was received */
|
||||||
|
if (xcpCtoRxLength == xcpCtoReqPacket[0])
|
||||||
|
{
|
||||||
|
/* copy the packet data */
|
||||||
|
CpuMemCopy((blt_int32u)data, (blt_int32u)&xcpCtoReqPacket[1], xcpCtoRxLength);
|
||||||
|
/* done with cto packet reception */
|
||||||
|
xcpCtoRxInProgress = BLT_FALSE;
|
||||||
|
/* set the packet length */
|
||||||
|
*len = xcpCtoRxLength;
|
||||||
|
/* packet reception complete */
|
||||||
|
return BLT_TRUE;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* check packet reception timeout */
|
||||||
|
if (TimerGet() > (xcpCtoRxStartTime + RS232_CTO_RX_PACKET_TIMEOUT_MS))
|
||||||
|
{
|
||||||
|
/* cancel cto packet reception due to timeout. note that that automaticaly
|
||||||
|
* discards the already received packet bytes, allowing the host to retry.
|
||||||
|
*/
|
||||||
|
xcpCtoRxInProgress = BLT_FALSE;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/* packet reception not yet complete */
|
||||||
|
return BLT_FALSE;
|
||||||
|
} /*** end of Rs232ReceivePacket ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Receives a communication interface byte if one is present.
|
||||||
|
** \param data Pointer to byte where the data is to be stored.
|
||||||
|
** \return BLT_TRUE if a byte was received, BLT_FALSE otherwise.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
static blt_bool Rs232ReceiveByte(blt_int8u *data)
|
||||||
|
{
|
||||||
|
blt_bool result = BLT_FALSE;
|
||||||
|
|
||||||
|
/* check flag to see if a byte was received */
|
||||||
|
if (LL_USART_IsActiveFlag_RXNE(USART_CHANNEL) != 0)
|
||||||
|
{
|
||||||
|
/* retrieve and store the newly received byte */
|
||||||
|
*data = LL_USART_ReceiveData8(USART_CHANNEL);
|
||||||
|
/* update the result for success */
|
||||||
|
result = BLT_TRUE;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* give the result back to the caller */
|
||||||
|
return result;
|
||||||
|
} /*** end of Rs232ReceiveByte ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Transmits a communication interface byte.
|
||||||
|
** \param data Value of byte that is to be transmitted.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
static void Rs232TransmitByte(blt_int8u data)
|
||||||
|
{
|
||||||
|
blt_int32u timeout;
|
||||||
|
|
||||||
|
/* write byte to transmit holding register */
|
||||||
|
LL_USART_TransmitData8(USART_CHANNEL, data);
|
||||||
|
/* set timeout time to wait for transmit completion. */
|
||||||
|
timeout = TimerGet() + RS232_BYTE_TX_TIMEOUT_MS;
|
||||||
|
/* wait for tx holding register to be empty */
|
||||||
|
while (LL_USART_IsActiveFlag_TXE(USART_CHANNEL) == 0)
|
||||||
|
{
|
||||||
|
/* keep the watchdog happy */
|
||||||
|
CopService();
|
||||||
|
/* break loop upon timeout. this would indicate a hardware failure. */
|
||||||
|
if (TimerGet() > timeout)
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
} /*** end of Rs232TransmitByte ***/
|
||||||
|
#endif /* BOOT_COM_RS232_ENABLE > 0 */
|
||||||
|
|
||||||
|
|
||||||
|
/*********************************** end of rs232.c ************************************/
|
||||||
9
Boot/ARMCM0_STM32G0/target.dox
Normal file
9
Boot/ARMCM0_STM32G0/target.dox
Normal file
@@ -0,0 +1,9 @@
|
|||||||
|
/**
|
||||||
|
\defgroup Target_ARMCM0_STM32G0 Target ARMCM0 STM32G0
|
||||||
|
\ingroup Ports
|
||||||
|
\brief Target dependent code for the ARMCM0 STM32G0 microcontroller family.
|
||||||
|
\details This module implements the bootloader's target dependent part for the
|
||||||
|
ARMCM0 STM32G0 microcontroller family.
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
128
Boot/ARMCM0_STM32G0/timer.c
Normal file
128
Boot/ARMCM0_STM32G0/timer.c
Normal file
@@ -0,0 +1,128 @@
|
|||||||
|
/************************************************************************************//**
|
||||||
|
* \file Source/ARMCM0_STM32G0/timer.c
|
||||||
|
* \brief Bootloader timer driver source file.
|
||||||
|
* \ingroup Target_ARMCM0_STM32G0
|
||||||
|
* \internal
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* C O P Y R I G H T
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* Copyright (c) 2019 by Feaser http://www.feaser.com All rights reserved
|
||||||
|
*
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* L I C E N S E
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as published by the Free
|
||||||
|
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||||
|
* version.
|
||||||
|
*
|
||||||
|
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||||
|
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||||
|
* PURPOSE. See the GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||||
|
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||||
|
*
|
||||||
|
* \endinternal
|
||||||
|
****************************************************************************************/
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Include files
|
||||||
|
****************************************************************************************/
|
||||||
|
#include "boot.h" /* bootloader generic header */
|
||||||
|
#include "stm32g0xx.h" /* STM32 CPU and HAL header */
|
||||||
|
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Local data declarations
|
||||||
|
****************************************************************************************/
|
||||||
|
/** \brief Local variable for storing the number of milliseconds that have elapsed since
|
||||||
|
* startup.
|
||||||
|
*/
|
||||||
|
static blt_int32u millisecond_counter;
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Initializes the polling based millisecond timer driver.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
void TimerInit(void)
|
||||||
|
{
|
||||||
|
/* Reset the timer configuration. */
|
||||||
|
TimerReset();
|
||||||
|
/* configure the systick frequency as a 1 ms event generator */
|
||||||
|
SysTick->LOAD = BOOT_CPU_SYSTEM_SPEED_KHZ - 1;
|
||||||
|
/* reset the current counter value */
|
||||||
|
SysTick->VAL = 0;
|
||||||
|
/* select core clock as source and enable the timer */
|
||||||
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
|
||||||
|
/* reset the millisecond counter value */
|
||||||
|
millisecond_counter = 0;
|
||||||
|
} /*** end of TimerInit ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Reset the timer by placing the timer back into it's default reset
|
||||||
|
** configuration.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
void TimerReset(void)
|
||||||
|
{
|
||||||
|
/* set the systick's registers back into the default reset value. */
|
||||||
|
SysTick->CTRL = 0;
|
||||||
|
SysTick->LOAD = 0;
|
||||||
|
SysTick->VAL = 0;
|
||||||
|
} /* end of TimerReset */
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Updates the millisecond timer.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
void TimerUpdate(void)
|
||||||
|
{
|
||||||
|
/* check if the millisecond event occurred */
|
||||||
|
if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0)
|
||||||
|
{
|
||||||
|
/* Increment the millisecond counter. */
|
||||||
|
millisecond_counter++;
|
||||||
|
}
|
||||||
|
} /*** end of TimerUpdate ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Obtains the counter value of the millisecond timer.
|
||||||
|
** \return Current value of the millisecond timer.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
blt_int32u TimerGet(void)
|
||||||
|
{
|
||||||
|
/* Updating timer here allows this function to be called in a loop with timeout
|
||||||
|
* detection.
|
||||||
|
*/
|
||||||
|
TimerUpdate();
|
||||||
|
/* Read and return the amount of milliseconds that passed since initialization. */
|
||||||
|
return millisecond_counter;
|
||||||
|
} /*** end of TimerGet ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Override for the HAL driver's GetTick() functionality. This is needed
|
||||||
|
** because the bootloader doesn't use interrupts, but the HAL's tick
|
||||||
|
** functionality assumes that it does. This will cause the HAL_Delay()
|
||||||
|
** function to not work properly. As a result of this override, the HAL's
|
||||||
|
** tick functionality works in polling mode.
|
||||||
|
** \return Current value of the millisecond timer.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
uint32_t HAL_GetTick(void)
|
||||||
|
{
|
||||||
|
/* Link to the bootloader's 1ms timer. */
|
||||||
|
return TimerGet();
|
||||||
|
} /*** end of HAL_GetTick ***/
|
||||||
|
|
||||||
|
|
||||||
|
/*********************************** end of timer.c ************************************/
|
||||||
59
Boot/ARMCM0_STM32G0/types.h
Normal file
59
Boot/ARMCM0_STM32G0/types.h
Normal file
@@ -0,0 +1,59 @@
|
|||||||
|
/************************************************************************************//**
|
||||||
|
* \file Source/ARMCM0_STM32G0/types.h
|
||||||
|
* \brief Bootloader types header file.
|
||||||
|
* \ingroup Target_ARMCM0_STM32G0
|
||||||
|
* \internal
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* C O P Y R I G H T
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* Copyright (c) 2019 by Feaser http://www.feaser.com All rights reserved
|
||||||
|
*
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* L I C E N S E
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as published by the Free
|
||||||
|
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||||
|
* version.
|
||||||
|
*
|
||||||
|
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||||
|
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||||
|
* PURPOSE. See the GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||||
|
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||||
|
*
|
||||||
|
* \endinternal
|
||||||
|
****************************************************************************************/
|
||||||
|
#ifndef TYPES_H
|
||||||
|
#define TYPES_H
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Macro definitions
|
||||||
|
****************************************************************************************/
|
||||||
|
/** \brief Boolean true value. */
|
||||||
|
#define BLT_TRUE (1)
|
||||||
|
/** \brief Boolean false value. */
|
||||||
|
#define BLT_FALSE (0)
|
||||||
|
/** \brief NULL pointer value. */
|
||||||
|
#define BLT_NULL ((void *)0)
|
||||||
|
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Type definitions
|
||||||
|
****************************************************************************************/
|
||||||
|
typedef unsigned char blt_bool; /**< boolean type */
|
||||||
|
typedef char blt_char; /**< character type */
|
||||||
|
typedef unsigned long blt_addr; /**< memory address type */
|
||||||
|
typedef unsigned char blt_int8u; /**< 8-bit unsigned integer */
|
||||||
|
typedef signed char blt_int8s; /**< 8-bit signed integer */
|
||||||
|
typedef unsigned short blt_int16u; /**< 16-bit unsigned integer */
|
||||||
|
typedef signed short blt_int16s; /**< 16-bit signed integer */
|
||||||
|
typedef unsigned int blt_int32u; /**< 32-bit unsigned integer */
|
||||||
|
typedef signed int blt_int32s; /**< 32-bit signed integer */
|
||||||
|
typedef unsigned long long blt_int64u; /**< 64-bit unsigned integer */
|
||||||
|
typedef signed long long blt_int64s; /**< 64-bit signed integer */
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* TYPES_H */
|
||||||
|
/*********************************** end of types.h ************************************/
|
||||||
61
Boot/App/app.c
Normal file
61
Boot/App/app.c
Normal file
@@ -0,0 +1,61 @@
|
|||||||
|
/************************************************************************************//**
|
||||||
|
* \file Demo/ARMCM0_STM32G0_Nucleo_G071RB_CubeIDE/Boot/App/app.c
|
||||||
|
* \brief Bootloader application source file.
|
||||||
|
* \ingroup Boot_ARMCM0_STM32G0_Nucleo_G071RB_CubeIDE
|
||||||
|
* \internal
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* C O P Y R I G H T
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
|
||||||
|
*
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* L I C E N S E
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as published by the Free
|
||||||
|
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||||
|
* version.
|
||||||
|
*
|
||||||
|
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||||
|
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||||
|
* PURPOSE. See the GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||||
|
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||||
|
*
|
||||||
|
* \endinternal
|
||||||
|
****************************************************************************************/
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Include files
|
||||||
|
****************************************************************************************/
|
||||||
|
#include "boot.h" /* bootloader generic header */
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Initializes the bootloader application. Should be called once during
|
||||||
|
** software program initialization.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
void AppInit(void)
|
||||||
|
{
|
||||||
|
/* initialize the bootloader */
|
||||||
|
BootInit();
|
||||||
|
} /*** end of AppInit ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Task function of the bootloader application. Should be called continuously
|
||||||
|
** in the program loop.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
void AppTask(void)
|
||||||
|
{
|
||||||
|
/* Run the bootloader task. */
|
||||||
|
BootTask();
|
||||||
|
} /*** end of AppTask ***/
|
||||||
|
|
||||||
|
|
||||||
|
/*********************************** end of app.c **************************************/
|
||||||
39
Boot/App/app.h
Normal file
39
Boot/App/app.h
Normal file
@@ -0,0 +1,39 @@
|
|||||||
|
/************************************************************************************//**
|
||||||
|
* \file Demo/ARMCM0_STM32G0_Nucleo_G071RB_CubeIDE/Boot/App/app.h
|
||||||
|
* \brief Bootloader application header file.
|
||||||
|
* \ingroup Boot_ARMCM0_STM32G0_Nucleo_G071RB_CubeIDE
|
||||||
|
* \internal
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* C O P Y R I G H T
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
|
||||||
|
*
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* L I C E N S E
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as published by the Free
|
||||||
|
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||||
|
* version.
|
||||||
|
*
|
||||||
|
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||||
|
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||||
|
* PURPOSE. See the GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||||
|
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||||
|
*
|
||||||
|
* \endinternal
|
||||||
|
****************************************************************************************/
|
||||||
|
#ifndef APP_H
|
||||||
|
#define APP_H
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Function prototypes
|
||||||
|
****************************************************************************************/
|
||||||
|
void AppInit(void);
|
||||||
|
void AppTask(void);
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* APP_H */
|
||||||
|
/*********************************** end of app.h **************************************/
|
||||||
148
Boot/App/blt_conf.h
Normal file
148
Boot/App/blt_conf.h
Normal file
@@ -0,0 +1,148 @@
|
|||||||
|
/************************************************************************************//**
|
||||||
|
* \file Demo/ARMCM0_STM32G0_Nucleo_G071RB_CubeIDE/Boot/App/blt_conf.h
|
||||||
|
* \brief Bootloader configuration header file.
|
||||||
|
* \ingroup Boot_ARMCM0_STM32G0_Nucleo_G071RB_CubeIDE
|
||||||
|
* \internal
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* C O P Y R I G H T
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
|
||||||
|
*
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* L I C E N S E
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as published by the Free
|
||||||
|
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||||
|
* version.
|
||||||
|
*
|
||||||
|
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||||
|
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||||
|
* PURPOSE. See the GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||||
|
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||||
|
*
|
||||||
|
* \endinternal
|
||||||
|
****************************************************************************************/
|
||||||
|
#ifndef BLT_CONF_H
|
||||||
|
#define BLT_CONF_H
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* C P U D R I V E R C O N F I G U R A T I O N
|
||||||
|
****************************************************************************************/
|
||||||
|
/* To properly initialize the baudrate clocks of the communication interface, typically
|
||||||
|
* the speed of the crystal oscillator and/or the speed at which the system runs is
|
||||||
|
* needed. Set these through configurables BOOT_CPU_XTAL_SPEED_KHZ and
|
||||||
|
* BOOT_CPU_SYSTEM_SPEED_KHZ, respectively. To enable data exchange with the host that is
|
||||||
|
* not dependent on the targets architecture, the byte ordering needs to be known.
|
||||||
|
* Setting BOOT_CPU_BYTE_ORDER_MOTOROLA to 1 selects big endian mode and 0 selects
|
||||||
|
* little endian mode.
|
||||||
|
*
|
||||||
|
* Set BOOT_CPU_USER_PROGRAM_START_HOOK to 1 if you would like a hook function to be
|
||||||
|
* called the moment the user program is about to be started. This could be used to
|
||||||
|
* de-initialize application specific parts, for example to stop blinking an LED, etc.
|
||||||
|
*/
|
||||||
|
/** \brief Frequency of the external crystal oscillator. */
|
||||||
|
#define BOOT_CPU_XTAL_SPEED_KHZ (16000)
|
||||||
|
/** \brief Desired system speed. */
|
||||||
|
#define BOOT_CPU_SYSTEM_SPEED_KHZ (64000)
|
||||||
|
/** \brief Motorola or Intel style byte ordering. */
|
||||||
|
#define BOOT_CPU_BYTE_ORDER_MOTOROLA (0)
|
||||||
|
/** \brief Enable/disable hook function call right before user program start. */
|
||||||
|
#define BOOT_CPU_USER_PROGRAM_START_HOOK (1)
|
||||||
|
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* C O M M U N I C A T I O N I N T E R F A C E C O N F I G U R A T I O N
|
||||||
|
****************************************************************************************/
|
||||||
|
/* The RS232 communication interface is selected by setting the BOOT_COM_RS232_ENABLE
|
||||||
|
* configurable to 1. Configurable BOOT_COM_RS232_BAUDRATE selects the communication speed
|
||||||
|
* in bits/second. The maximum amount of data bytes in a message for data transmission
|
||||||
|
* and reception is set through BOOT_COM_RS232_TX_MAX_DATA and BOOT_COM_RS232_RX_MAX_DATA,
|
||||||
|
* respectively. It is common for a microcontroller to have more than 1 UART interface
|
||||||
|
* on board. The zero-based BOOT_COM_RS232_CHANNEL_INDEX selects the UART interface.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
/** \brief Enable/disable UART transport layer. */
|
||||||
|
#define BOOT_COM_RS232_ENABLE (1)
|
||||||
|
/** \brief Configure the desired communication speed. */
|
||||||
|
#define BOOT_COM_RS232_BAUDRATE (57600)
|
||||||
|
/** \brief Configure number of bytes in the target->host data packet. */
|
||||||
|
#define BOOT_COM_RS232_TX_MAX_DATA (129)
|
||||||
|
/** \brief Configure number of bytes in the host->target data packet. */
|
||||||
|
#define BOOT_COM_RS232_RX_MAX_DATA (129)
|
||||||
|
/** \brief Select the desired UART peripheral as a zero based index. */
|
||||||
|
#define BOOT_COM_RS232_CHANNEL_INDEX (1)
|
||||||
|
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* B A C K D O O R E N T R Y C O N F I G U R A T I O N
|
||||||
|
****************************************************************************************/
|
||||||
|
/* It is possible to implement an application specific method to force the bootloader to
|
||||||
|
* stay active after a reset. Such a backdoor entry into the bootloader is desired in
|
||||||
|
* situations where the user program does not run properly and therefore cannot
|
||||||
|
* reactivate the bootloader. By enabling these hook functions, the application can
|
||||||
|
* implement the backdoor, which overrides the default backdoor entry that is programmed
|
||||||
|
* into the bootloader. When desired for security purposes, these hook functions can
|
||||||
|
* also be implemented in a way that disables the backdoor entry altogether.
|
||||||
|
*/
|
||||||
|
/** \brief Enable/disable the backdoor override hook functions. */
|
||||||
|
#define BOOT_BACKDOOR_HOOKS_ENABLE (0)
|
||||||
|
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* N O N - V O L A T I L E M E M O R Y D R I V E R C O N F I G U R A T I O N
|
||||||
|
****************************************************************************************/
|
||||||
|
/* The NVM driver typically supports erase and program operations of the internal memory
|
||||||
|
* present on the microcontroller. Through these hook functions the NVM driver can be
|
||||||
|
* extended to support additional memory types such as external flash memory and serial
|
||||||
|
* eeproms. The size of the internal memory in kilobytes is specified with configurable
|
||||||
|
* BOOT_NVM_SIZE_KB. If desired the internal checksum writing and verification method can
|
||||||
|
* be overridden with a application specific method by enabling configuration switch
|
||||||
|
* BOOT_NVM_CHECKSUM_HOOKS_ENABLE.
|
||||||
|
*/
|
||||||
|
/** \brief Enable/disable the NVM hook function for supporting additional memory devices. */
|
||||||
|
#define BOOT_NVM_HOOKS_ENABLE (0)
|
||||||
|
/** \brief Configure the size of the default memory device (typically flash EEPROM). */
|
||||||
|
#define BOOT_NVM_SIZE_KB (128)
|
||||||
|
/** \brief Enable/disable hooks functions to override the user program checksum handling. */
|
||||||
|
#define BOOT_NVM_CHECKSUM_HOOKS_ENABLE (0)
|
||||||
|
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* W A T C H D O G D R I V E R C O N F I G U R A T I O N
|
||||||
|
****************************************************************************************/
|
||||||
|
/* The COP driver cannot be configured internally in the bootloader, because its use
|
||||||
|
* and configuration is application specific. The bootloader does need to service the
|
||||||
|
* watchdog in case it is used. When the application requires the use of a watchdog,
|
||||||
|
* set BOOT_COP_HOOKS_ENABLE to be able to initialize and service the watchdog through
|
||||||
|
* hook functions.
|
||||||
|
*/
|
||||||
|
/** \brief Enable/disable the hook functions for controlling the watchdog. */
|
||||||
|
#define BOOT_COP_HOOKS_ENABLE (1)
|
||||||
|
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* S E E D / K E Y S E C U R I T Y C O N F I G U R A T I O N
|
||||||
|
****************************************************************************************/
|
||||||
|
/* A security mechanism can be enabled in the bootloader's XCP module by setting configu-
|
||||||
|
* rable BOOT_XCP_SEED_KEY_ENABLE to 1. Before any memory erase or programming
|
||||||
|
* operations can be performed, access to this resource need to be unlocked.
|
||||||
|
* In the Microboot settings on tab "XCP Protection" you need to specify a DLL that
|
||||||
|
* implements the unlocking algorithm. The demo programs are configured for the (simple)
|
||||||
|
* algorithm in "libseednkey.dll". The source code for this DLL is available so it can be
|
||||||
|
* customized to your needs.
|
||||||
|
* During the unlock sequence, Microboot requests a seed from the bootloader, which is in
|
||||||
|
* the format of a byte array. Using this seed the unlock algorithm in the DLL computes
|
||||||
|
* a key, which is also a byte array, and sends this back to the bootloader. The
|
||||||
|
* bootloader then verifies this key to determine if programming and erase operations are
|
||||||
|
* permitted.
|
||||||
|
* After enabling this feature the hook functions XcpGetSeedHook() and XcpVerifyKeyHook()
|
||||||
|
* are called by the bootloader to obtain the seed and to verify the key, respectively.
|
||||||
|
*/
|
||||||
|
#define BOOT_XCP_SEED_KEY_ENABLE (0)
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* BLT_CONF_H */
|
||||||
|
/*********************************** end of blt_conf.h *********************************/
|
||||||
307
Boot/App/hooks.c
Normal file
307
Boot/App/hooks.c
Normal file
@@ -0,0 +1,307 @@
|
|||||||
|
/************************************************************************************//**
|
||||||
|
* \file Demo/ARMCM0_STM32G0_Nucleo_G071RB_CubeIDE/Boot/App/hooks.c
|
||||||
|
* \brief Bootloader callback source file.
|
||||||
|
* \ingroup Boot_ARMCM0_STM32G0_Nucleo_G071RB_CubeIDE
|
||||||
|
* \internal
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* C O P Y R I G H T
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
|
||||||
|
*
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* L I C E N S E
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as published by the Free
|
||||||
|
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||||
|
* version.
|
||||||
|
*
|
||||||
|
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||||
|
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||||
|
* PURPOSE. See the GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||||
|
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||||
|
*
|
||||||
|
* \endinternal
|
||||||
|
****************************************************************************************/
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Include files
|
||||||
|
****************************************************************************************/
|
||||||
|
#include "boot.h" /* bootloader generic header */
|
||||||
|
#include "led.h" /* LED driver header */
|
||||||
|
#include "stm32g0xx.h" /* STM32 CPU and HAL header */
|
||||||
|
#include "stm32g0xx_ll_gpio.h" /* STM32 LL GPIO header */
|
||||||
|
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* B A C K D O O R E N T R Y H O O K F U N C T I O N S
|
||||||
|
****************************************************************************************/
|
||||||
|
|
||||||
|
#if (BOOT_BACKDOOR_HOOKS_ENABLE > 0)
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Initializes the backdoor entry option.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
void BackDoorInitHook(void)
|
||||||
|
{
|
||||||
|
} /*** end of BackDoorInitHook ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Checks if a backdoor entry is requested.
|
||||||
|
** \return BLT_TRUE if the backdoor entry is requested, BLT_FALSE otherwise.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
blt_bool BackDoorEntryHook(void)
|
||||||
|
{
|
||||||
|
/* default implementation always activates the bootloader after a reset */
|
||||||
|
return BLT_TRUE;
|
||||||
|
} /*** end of BackDoorEntryHook ***/
|
||||||
|
#endif /* BOOT_BACKDOOR_HOOKS_ENABLE > 0 */
|
||||||
|
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* C P U D R I V E R H O O K F U N C T I O N S
|
||||||
|
****************************************************************************************/
|
||||||
|
|
||||||
|
#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0)
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Callback that gets called when the bootloader is about to exit and
|
||||||
|
** hand over control to the user program. This is the last moment that
|
||||||
|
** some final checking can be performed and if necessary prevent the
|
||||||
|
** bootloader from activiting the user program.
|
||||||
|
** \return BLT_TRUE if it is okay to start the user program, BLT_FALSE to keep
|
||||||
|
** keep the bootloader active.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
blt_bool CpuUserProgramStartHook(void)
|
||||||
|
{
|
||||||
|
/* additional and optional backdoor entry through the pushbutton on the board. to
|
||||||
|
* force the bootloader to stay active after reset, keep it pressed during reset.
|
||||||
|
*/
|
||||||
|
if (LL_GPIO_IsInputPinSet(GPIOC, LL_GPIO_PIN_13) == 0)
|
||||||
|
{
|
||||||
|
/* pushbutton pressed, so do not start the user program and keep the
|
||||||
|
* bootloader active instead.
|
||||||
|
*/
|
||||||
|
return BLT_FALSE;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* clean up the LED driver */
|
||||||
|
LedBlinkExit();
|
||||||
|
/* okay to start the user program */
|
||||||
|
return BLT_TRUE;
|
||||||
|
} /*** end of CpuUserProgramStartHook ***/
|
||||||
|
#endif /* BOOT_CPU_USER_PROGRAM_START_HOOK > 0 */
|
||||||
|
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* W A T C H D O G D R I V E R H O O K F U N C T I O N S
|
||||||
|
****************************************************************************************/
|
||||||
|
|
||||||
|
#if (BOOT_COP_HOOKS_ENABLE > 0)
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Callback that gets called at the end of the internal COP driver
|
||||||
|
** initialization routine. It can be used to configure and enable the
|
||||||
|
** watchdog.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
void CopInitHook(void)
|
||||||
|
{
|
||||||
|
/* this function is called upon initialization. might as well use it to initialize
|
||||||
|
* the LED driver. It is kind of a visual watchdog anyways.
|
||||||
|
*/
|
||||||
|
LedBlinkInit(100);
|
||||||
|
} /*** end of CopInitHook ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Callback that gets called at the end of the internal COP driver
|
||||||
|
** service routine. This gets called upon initialization and during
|
||||||
|
** potential long lasting loops and routine. It can be used to service
|
||||||
|
** the watchdog to prevent a watchdog reset.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
void CopServiceHook(void)
|
||||||
|
{
|
||||||
|
/* run the LED blink task. this is a better place to do it than in the main() program
|
||||||
|
* loop. certain operations such as flash erase can take a long time, which would cause
|
||||||
|
* a blink interval to be skipped. this function is also called during such operations,
|
||||||
|
* so no blink intervals will be skipped when calling the LED blink task here.
|
||||||
|
*/
|
||||||
|
LedBlinkTask();
|
||||||
|
} /*** end of CopServiceHook ***/
|
||||||
|
#endif /* BOOT_COP_HOOKS_ENABLE > 0 */
|
||||||
|
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* N O N - V O L A T I L E M E M O R Y D R I V E R H O O K F U N C T I O N S
|
||||||
|
****************************************************************************************/
|
||||||
|
|
||||||
|
#if (BOOT_NVM_HOOKS_ENABLE > 0)
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Callback that gets called at the start of the internal NVM driver
|
||||||
|
** initialization routine.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
void NvmInitHook(void)
|
||||||
|
{
|
||||||
|
} /*** end of NvmInitHook ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Callback that gets called at the start of a firmware update to reinitialize
|
||||||
|
** the NVM driver.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
void NvmReinitHook(void)
|
||||||
|
{
|
||||||
|
} /*** end of NvmReinitHook ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Callback that gets called at the start of the NVM driver write
|
||||||
|
** routine. It allows additional memory to be operated on. If the address
|
||||||
|
** is not within the range of the additional memory, then
|
||||||
|
** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the data hasn't
|
||||||
|
** been written yet.
|
||||||
|
** \param addr Start address.
|
||||||
|
** \param len Length in bytes.
|
||||||
|
** \param data Pointer to the data buffer.
|
||||||
|
** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is
|
||||||
|
** not within the supported memory range, or BLT_NVM_ERROR is the write
|
||||||
|
** operation failed.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
blt_int8u NvmWriteHook(blt_addr addr, blt_int32u len, blt_int8u *data)
|
||||||
|
{
|
||||||
|
return BLT_NVM_NOT_IN_RANGE;
|
||||||
|
} /*** end of NvmWriteHook ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Callback that gets called at the start of the NVM driver erase
|
||||||
|
** routine. It allows additional memory to be operated on. If the address
|
||||||
|
** is not within the range of the additional memory, then
|
||||||
|
** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the memory
|
||||||
|
** hasn't been erased yet.
|
||||||
|
** \param addr Start address.
|
||||||
|
** \param len Length in bytes.
|
||||||
|
** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is
|
||||||
|
** not within the supported memory range, or BLT_NVM_ERROR is the erase
|
||||||
|
** operation failed.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
blt_int8u NvmEraseHook(blt_addr addr, blt_int32u len)
|
||||||
|
{
|
||||||
|
return BLT_NVM_NOT_IN_RANGE;
|
||||||
|
} /*** end of NvmEraseHook ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Callback that gets called at the end of the NVM programming session.
|
||||||
|
** \return BLT_TRUE is successful, BLT_FALSE otherwise.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
blt_bool NvmDoneHook(void)
|
||||||
|
{
|
||||||
|
return BLT_TRUE;
|
||||||
|
} /*** end of NvmDoneHook ***/
|
||||||
|
#endif /* BOOT_NVM_HOOKS_ENABLE > 0 */
|
||||||
|
|
||||||
|
|
||||||
|
#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0)
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Verifies the checksum, which indicates that a valid user program is
|
||||||
|
** present and can be started.
|
||||||
|
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
blt_bool NvmVerifyChecksumHook(void)
|
||||||
|
{
|
||||||
|
return BLT_TRUE;
|
||||||
|
} /*** end of NvmVerifyChecksum ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Writes a checksum of the user program to non-volatile memory. This is
|
||||||
|
** performed once the entire user program has been programmed. Through
|
||||||
|
** the checksum, the bootloader can check if a valid user programming is
|
||||||
|
** present and can be started.
|
||||||
|
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
blt_bool NvmWriteChecksumHook(void)
|
||||||
|
{
|
||||||
|
return BLT_TRUE;
|
||||||
|
}
|
||||||
|
#endif /* BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0 */
|
||||||
|
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* S E E D / K E Y S E C U R I T Y H O O K F U N C T I O N S
|
||||||
|
****************************************************************************************/
|
||||||
|
|
||||||
|
#if (BOOT_XCP_SEED_KEY_ENABLE > 0)
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Provides a seed to the XCP master that will be used for the key
|
||||||
|
** generation when the master attempts to unlock the specified resource.
|
||||||
|
** Called by the GET_SEED command.
|
||||||
|
** \param resource Resource that the seed if requested for (XCP_RES_XXX).
|
||||||
|
** \param seed Pointer to byte buffer wher the seed will be stored.
|
||||||
|
** \return Length of the seed in bytes.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
blt_int8u XcpGetSeedHook(blt_int8u resource, blt_int8u *seed)
|
||||||
|
{
|
||||||
|
/* request seed for unlocking ProGraMming resource */
|
||||||
|
if ((resource & XCP_RES_PGM) != 0)
|
||||||
|
{
|
||||||
|
seed[0] = 0x55;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* return seed length */
|
||||||
|
return 1;
|
||||||
|
} /*** end of XcpGetSeedHook ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Called by the UNLOCK command and checks if the key to unlock the
|
||||||
|
** specified resource was correct. If so, then the resource protection
|
||||||
|
** will be removed.
|
||||||
|
** \param resource resource to unlock (XCP_RES_XXX).
|
||||||
|
** \param key pointer to the byte buffer holding the key.
|
||||||
|
** \param len length of the key in bytes.
|
||||||
|
** \return 1 if the key was correct, 0 otherwise.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
blt_int8u XcpVerifyKeyHook(blt_int8u resource, blt_int8u *key, blt_int8u len)
|
||||||
|
{
|
||||||
|
/* suppress compiler warning for unused parameter */
|
||||||
|
len = len;
|
||||||
|
|
||||||
|
/* the example key algorithm in "libseednkey.dll" works as follows:
|
||||||
|
* - PGM will be unlocked if key = seed - 1
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* check key for unlocking ProGraMming resource */
|
||||||
|
if ((resource == XCP_RES_PGM) && (key[0] == (0x55-1)))
|
||||||
|
{
|
||||||
|
/* correct key received for unlocking PGM resource */
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* still here so key incorrect */
|
||||||
|
return 0;
|
||||||
|
} /*** end of XcpVerifyKeyHook ***/
|
||||||
|
#endif /* BOOT_XCP_SEED_KEY_ENABLE > 0 */
|
||||||
|
|
||||||
|
|
||||||
|
/*********************************** end of hooks.c ************************************/
|
||||||
101
Boot/App/led.c
Normal file
101
Boot/App/led.c
Normal file
@@ -0,0 +1,101 @@
|
|||||||
|
/************************************************************************************//**
|
||||||
|
* \file Demo/ARMCM0_STM32G0_Nucleo_G071RB_CubeIDE/Boot/App/led.c
|
||||||
|
* \brief LED driver source file.
|
||||||
|
* \ingroup Boot_ARMCM0_STM32G0_Nucleo_G071RB_CubeIDE
|
||||||
|
* \internal
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* C O P Y R I G H T
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
|
||||||
|
*
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* L I C E N S E
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as published by the Free
|
||||||
|
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||||
|
* version.
|
||||||
|
*
|
||||||
|
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||||
|
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||||
|
* PURPOSE. See the GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||||
|
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||||
|
*
|
||||||
|
* \endinternal
|
||||||
|
****************************************************************************************/
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Include files
|
||||||
|
****************************************************************************************/
|
||||||
|
#include "boot.h" /* bootloader generic header */
|
||||||
|
#include "led.h" /* module header */
|
||||||
|
#include "stm32g0xx.h" /* STM32 CPU and HAL header */
|
||||||
|
#include "stm32g0xx_ll_gpio.h" /* STM32 LL GPIO header */
|
||||||
|
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Local data declarations
|
||||||
|
****************************************************************************************/
|
||||||
|
/** \brief Holds the desired LED blink interval time. */
|
||||||
|
static blt_int16u ledBlinkIntervalMs;
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Initializes the LED blink driver.
|
||||||
|
** \param interval_ms Specifies the desired LED blink interval time in milliseconds.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
void LedBlinkInit(blt_int16u interval_ms)
|
||||||
|
{
|
||||||
|
/* store the interval time between LED toggles */
|
||||||
|
ledBlinkIntervalMs = interval_ms;
|
||||||
|
} /*** end of LedBlinkInit ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Task function for blinking the LED as a fixed timer interval.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
void LedBlinkTask(void)
|
||||||
|
{
|
||||||
|
static blt_bool ledOn = BLT_FALSE;
|
||||||
|
static blt_int32u nextBlinkEvent = 0;
|
||||||
|
|
||||||
|
/* check for blink event */
|
||||||
|
if (TimerGet() >= nextBlinkEvent)
|
||||||
|
{
|
||||||
|
/* toggle the LED state */
|
||||||
|
if (ledOn == BLT_FALSE)
|
||||||
|
{
|
||||||
|
ledOn = BLT_TRUE;
|
||||||
|
LL_GPIO_SetOutputPin(GPIOA, LL_GPIO_PIN_5);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
ledOn = BLT_FALSE;
|
||||||
|
LL_GPIO_ResetOutputPin(GPIOA, LL_GPIO_PIN_5);
|
||||||
|
}
|
||||||
|
/* schedule the next blink event */
|
||||||
|
nextBlinkEvent = TimerGet() + ledBlinkIntervalMs;
|
||||||
|
}
|
||||||
|
} /*** end of LedBlinkTask ***/
|
||||||
|
|
||||||
|
|
||||||
|
/************************************************************************************//**
|
||||||
|
** \brief Cleans up the LED blink driver. This is intended to be used upon program
|
||||||
|
** exit.
|
||||||
|
** \return none.
|
||||||
|
**
|
||||||
|
****************************************************************************************/
|
||||||
|
void LedBlinkExit(void)
|
||||||
|
{
|
||||||
|
/* turn the LED off */
|
||||||
|
LL_GPIO_ResetOutputPin(GPIOA, LL_GPIO_PIN_5);
|
||||||
|
} /*** end of LedBlinkExit ***/
|
||||||
|
|
||||||
|
|
||||||
|
/*********************************** end of led.c **************************************/
|
||||||
40
Boot/App/led.h
Normal file
40
Boot/App/led.h
Normal file
@@ -0,0 +1,40 @@
|
|||||||
|
/************************************************************************************//**
|
||||||
|
* \file Demo/ARMCM0_STM32G0_Nucleo_G071RB_CubeIDE/Boot/App/led.h
|
||||||
|
* \brief LED driver header file.
|
||||||
|
* \ingroup Boot_ARMCM0_STM32G0_Nucleo_G071RB_CubeIDE
|
||||||
|
* \internal
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* C O P Y R I G H T
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
|
||||||
|
*
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* L I C E N S E
|
||||||
|
*----------------------------------------------------------------------------------------
|
||||||
|
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as published by the Free
|
||||||
|
* Software Foundation, either version 3 of the License, or (at your option) any later
|
||||||
|
* version.
|
||||||
|
*
|
||||||
|
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
|
||||||
|
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||||
|
* PURPOSE. See the GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You have received a copy of the GNU General Public License along with OpenBLT. It
|
||||||
|
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
|
||||||
|
*
|
||||||
|
* \endinternal
|
||||||
|
****************************************************************************************/
|
||||||
|
#ifndef LED_H
|
||||||
|
#define LED_H
|
||||||
|
|
||||||
|
/****************************************************************************************
|
||||||
|
* Function prototypes
|
||||||
|
****************************************************************************************/
|
||||||
|
void LedBlinkInit(blt_int16u interval_ms);
|
||||||
|
void LedBlinkTask(void);
|
||||||
|
void LedBlinkExit(void);
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* LED_H */
|
||||||
|
/*********************************** end of led.h **************************************/
|
||||||
73
Boot/Boot Debug.launch
Normal file
73
Boot/Boot Debug.launch
Normal file
@@ -0,0 +1,73 @@
|
|||||||
|
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||||
|
<launchConfiguration type="com.st.stm32cube.ide.mcu.debug.launch.launchConfigurationType">
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.access_port_id" value="0"/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.enable_live_expr" value="true"/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.enable_swv" value="false"/>
|
||||||
|
<intAttribute key="com.st.stm32cube.ide.mcu.debug.launch.formatVersion" value="2"/>
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.ip_address_local" value="localhost"/>
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.loadList" value="{"fItems":[{"fIsFromMainTab":true,"fPath":"Debug/openblt_stm32g071.elf","fProjectName":"Boot","fPerformBuild":true,"fDownload":true,"fLoadSymbols":true}]}"/>
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.override_start_address_mode" value="default"/>
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.remoteCommand" value="target remote"/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.startServer" value="true"/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.startuptab.exception.divby0" value="true"/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.startuptab.exception.unaligned" value="false"/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.startuptab.haltonexception" value="true"/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.swd_mode" value="true"/>
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.swv_port" value="61235"/>
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.swv_trace_div" value="8"/>
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.swv_trace_hclk" value="16000000"/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.useRemoteTarget" value="true"/>
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.vector_table" value=""/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.verify_flash_download" value="true"/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.cti_allow_halt" value="false"/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.cti_signal_halt" value="false"/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.enable_external_loader" value="false"/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.enable_logging" value="false"/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.enable_max_halt_delay" value="false"/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.enable_shared_stlink" value="false"/>
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.external_loader" value=""/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.external_loader_init" value="false"/>
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.frequency" value="0"/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.halt_all_on_reset" value="false"/>
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.log_file" value="C:\Work\software\OpenBLT\Target\Demo\ARMCM0_STM32G0_Nucleo_G071RB_CubeIDE\Boot\Debug\st-link_gdbserver_log.txt"/>
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.low_power_debug" value="enable"/>
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.max_halt_delay" value="2"/>
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.reset_strategy" value="connect_under_reset"/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.stlink_check_serial_number" value="false"/>
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.stlink_txt_serial_number" value=""/>
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.watchdog_config" value="none"/>
|
||||||
|
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlinkrestart_configurations" value="{"fItems":[{"fDisplayName":"Reset","fIsSuppressible":false,"fResetAttribute":"Software system reset","fResetStrategies":[{"fDisplayName":"Software system reset","fLaunchAttribute":"system_reset","fGdbCommands":["monitor reset\r\n"],"fCmdOptions":["-g"]},{"fDisplayName":"Hardware reset","fLaunchAttribute":"hardware_reset","fGdbCommands":["monitor reset hardware\r\n"],"fCmdOptions":["-g"]},{"fDisplayName":"Core reset","fLaunchAttribute":"core_reset","fGdbCommands":["monitor reset core\r\n"],"fCmdOptions":["-g"]},{"fDisplayName":"None","fLaunchAttribute":"no_reset","fGdbCommands":[],"fCmdOptions":["-g"]}],"fGdbCommandGroup":{"name":"Additional commands","commands":[]}}]}"/>
|
||||||
|
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.swv.swv_wait_for_sync" value="true"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="false"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="false"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value=""/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="ST-LINK (ST-LINK GDB server)"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
|
||||||
|
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="61234"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="true"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.NON_STOP" value="true"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
|
||||||
|
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="remote"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN_SYMBOL" value="main"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/openblt_stm32g071.elf"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="Boot"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1190274931"/>
|
||||||
|
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
|
||||||
|
<listEntry value="/Boot"/>
|
||||||
|
</listAttribute>
|
||||||
|
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
|
||||||
|
<listEntry value="4"/>
|
||||||
|
</listAttribute>
|
||||||
|
<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?><memoryBlockExpressionList context="reserved-for-future-use"/>"/>
|
||||||
|
<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
|
||||||
|
</launchConfiguration>
|
||||||
114
Boot/Boot.ioc
Normal file
114
Boot/Boot.ioc
Normal file
@@ -0,0 +1,114 @@
|
|||||||
|
#MicroXplorer Configuration settings - do not modify
|
||||||
|
File.Version=6
|
||||||
|
KeepUserPlacement=false
|
||||||
|
Mcu.Family=STM32G0
|
||||||
|
Mcu.IP0=NVIC
|
||||||
|
Mcu.IP1=RCC
|
||||||
|
Mcu.IP2=SYS
|
||||||
|
Mcu.IP3=USART2
|
||||||
|
Mcu.IPNb=4
|
||||||
|
Mcu.Name=STM32G071R(6-8-B)Tx
|
||||||
|
Mcu.Package=LQFP64
|
||||||
|
Mcu.Pin0=PC13
|
||||||
|
Mcu.Pin1=PA2
|
||||||
|
Mcu.Pin2=PA3
|
||||||
|
Mcu.Pin3=PA5
|
||||||
|
Mcu.Pin4=VP_SYS_VS_Systick
|
||||||
|
Mcu.Pin5=VP_SYS_VS_DBSignals
|
||||||
|
Mcu.PinsNb=6
|
||||||
|
Mcu.ThirdPartyNb=0
|
||||||
|
Mcu.UserConstants=
|
||||||
|
Mcu.UserName=STM32G071RBTx
|
||||||
|
MxCube.Version=6.3.0
|
||||||
|
MxDb.Version=DB.6.0.30
|
||||||
|
NVIC.ForceEnableDMAVector=true
|
||||||
|
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
|
||||||
|
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
|
||||||
|
NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
|
||||||
|
NVIC.SVC_IRQn=true\:0\:0\:false\:false\:true\:false\:false
|
||||||
|
NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
|
||||||
|
PA2.Locked=true
|
||||||
|
PA2.Mode=Asynchronous
|
||||||
|
PA2.Signal=USART2_TX
|
||||||
|
PA3.Locked=true
|
||||||
|
PA3.Mode=Asynchronous
|
||||||
|
PA3.Signal=USART2_RX
|
||||||
|
PA5.Locked=true
|
||||||
|
PA5.Signal=GPIO_Output
|
||||||
|
PC13.Locked=true
|
||||||
|
PC13.Signal=GPIO_Input
|
||||||
|
PinOutPanel.RotationAngle=0
|
||||||
|
ProjectManager.AskForMigrate=true
|
||||||
|
ProjectManager.BackupPrevious=false
|
||||||
|
ProjectManager.CompilerOptimize=6
|
||||||
|
ProjectManager.ComputerToolchain=false
|
||||||
|
ProjectManager.CoupleFile=false
|
||||||
|
ProjectManager.CustomerFirmwarePackage=
|
||||||
|
ProjectManager.DefaultFWLocation=true
|
||||||
|
ProjectManager.DeletePrevious=true
|
||||||
|
ProjectManager.DeviceId=STM32G071RBTx
|
||||||
|
ProjectManager.FirmwarePackage=STM32Cube FW_G0 V1.5.0
|
||||||
|
ProjectManager.FreePins=false
|
||||||
|
ProjectManager.HalAssertFull=false
|
||||||
|
ProjectManager.HeapSize=0x200
|
||||||
|
ProjectManager.KeepUserCode=true
|
||||||
|
ProjectManager.LastFirmware=true
|
||||||
|
ProjectManager.LibraryCopy=1
|
||||||
|
ProjectManager.MainLocation=Core/Src
|
||||||
|
ProjectManager.NoMain=false
|
||||||
|
ProjectManager.PreviousToolchain=
|
||||||
|
ProjectManager.ProjectBuild=false
|
||||||
|
ProjectManager.ProjectFileName=Boot.ioc
|
||||||
|
ProjectManager.ProjectName=Boot
|
||||||
|
ProjectManager.RegisterCallBack=
|
||||||
|
ProjectManager.StackSize=0x400
|
||||||
|
ProjectManager.TargetToolchain=STM32CubeIDE
|
||||||
|
ProjectManager.ToolChainLocation=
|
||||||
|
ProjectManager.UnderRoot=true
|
||||||
|
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-LL-false,3-MX_USART2_UART_Init-USART2-false-LL-true
|
||||||
|
RCC.ADCFreq_Value=64000000
|
||||||
|
RCC.AHBFreq_Value=64000000
|
||||||
|
RCC.APBFreq_Value=64000000
|
||||||
|
RCC.APBTimFreq_Value=64000000
|
||||||
|
RCC.CECFreq_Value=32786.88524590164
|
||||||
|
RCC.CortexFreq_Value=64000000
|
||||||
|
RCC.EXTERNAL_CLOCK_VALUE=12288000
|
||||||
|
RCC.FCLKCortexFreq_Value=64000000
|
||||||
|
RCC.FamilyName=M
|
||||||
|
RCC.HCLKFreq_Value=64000000
|
||||||
|
RCC.HSE_VALUE=8000000
|
||||||
|
RCC.HSI_VALUE=16000000
|
||||||
|
RCC.I2C1Freq_Value=64000000
|
||||||
|
RCC.I2S1Freq_Value=64000000
|
||||||
|
RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APBFreq_Value,APBTimFreq_Value,CECFreq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2S1Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLM,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLR,PLLRCLKFreq_Value,PWRFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,TIM15Freq_Value,TIM1Freq_Value,USART1Freq_Value,USART2Freq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
|
||||||
|
RCC.LPTIM1Freq_Value=64000000
|
||||||
|
RCC.LPTIM2Freq_Value=64000000
|
||||||
|
RCC.LPUART1Freq_Value=64000000
|
||||||
|
RCC.LSCOPinFreq_Value=32000
|
||||||
|
RCC.LSE_VALUE=32768
|
||||||
|
RCC.LSI_VALUE=32000
|
||||||
|
RCC.MCO1PinFreq_Value=64000000
|
||||||
|
RCC.PLLM=RCC_PLLM_DIV4
|
||||||
|
RCC.PLLN=64
|
||||||
|
RCC.PLLPoutputFreq_Value=128000000
|
||||||
|
RCC.PLLQoutputFreq_Value=128000000
|
||||||
|
RCC.PLLR=RCC_PLLR_DIV4
|
||||||
|
RCC.PLLRCLKFreq_Value=64000000
|
||||||
|
RCC.PWRFreq_Value=64000000
|
||||||
|
RCC.SYSCLKFreq_VALUE=64000000
|
||||||
|
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
|
||||||
|
RCC.TIM15Freq_Value=64000000
|
||||||
|
RCC.TIM1Freq_Value=64000000
|
||||||
|
RCC.USART1Freq_Value=64000000
|
||||||
|
RCC.USART2Freq_Value=64000000
|
||||||
|
RCC.VCOInputFreq_Value=4000000
|
||||||
|
RCC.VCOOutputFreq_Value=256000000
|
||||||
|
USART2.IPParameters=VirtualMode-Asynchronous
|
||||||
|
USART2.VirtualMode-Asynchronous=VM_ASYNC
|
||||||
|
VP_SYS_VS_DBSignals.Mode=DisableDeadBatterySignals
|
||||||
|
VP_SYS_VS_DBSignals.Signal=SYS_VS_DBSignals
|
||||||
|
VP_SYS_VS_Systick.Mode=SysTick
|
||||||
|
VP_SYS_VS_Systick.Signal=SYS_VS_Systick
|
||||||
|
board=NUCLEO-G071RB
|
||||||
|
boardIOC=true
|
||||||
|
isbadioc=false
|
||||||
75
Boot/CMakeLists.txt
Normal file
75
Boot/CMakeLists.txt
Normal file
@@ -0,0 +1,75 @@
|
|||||||
|
#THIS FILE IS AUTO GENERATED FROM THE TEMPLATE! DO NOT CHANGE!
|
||||||
|
set(CMAKE_SYSTEM_NAME Generic)
|
||||||
|
set(CMAKE_SYSTEM_VERSION 1)
|
||||||
|
cmake_minimum_required(VERSION 3.23)
|
||||||
|
|
||||||
|
# specify cross-compilers and tools
|
||||||
|
set(CMAKE_C_COMPILER arm-none-eabi-gcc)
|
||||||
|
set(CMAKE_CXX_COMPILER arm-none-eabi-g++)
|
||||||
|
set(CMAKE_ASM_COMPILER arm-none-eabi-gcc)
|
||||||
|
set(CMAKE_AR arm-none-eabi-ar)
|
||||||
|
set(CMAKE_OBJCOPY arm-none-eabi-objcopy)
|
||||||
|
set(CMAKE_OBJDUMP arm-none-eabi-objdump)
|
||||||
|
set(SIZE arm-none-eabi-size)
|
||||||
|
set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY)
|
||||||
|
|
||||||
|
# project settings
|
||||||
|
project(gm60 C CXX ASM)
|
||||||
|
set(CMAKE_CXX_STANDARD 17)
|
||||||
|
set(CMAKE_C_STANDARD 11)
|
||||||
|
|
||||||
|
#Uncomment for hardware floating point
|
||||||
|
#add_compile_definitions(ARM_MATH_CM4;ARM_MATH_MATRIX_CHECK;ARM_MATH_ROUNDING)
|
||||||
|
#add_compile_options(-mfloat-abi=hard -mfpu=fpv4-sp-d16)
|
||||||
|
#add_link_options(-mfloat-abi=hard -mfpu=fpv4-sp-d16)
|
||||||
|
|
||||||
|
#Uncomment for software floating point
|
||||||
|
#add_compile_options(-mfloat-abi=soft)
|
||||||
|
|
||||||
|
add_compile_options(-mcpu=cortex-m0 -mthumb -mthumb-interwork)
|
||||||
|
add_compile_options(-ffunction-sections -fdata-sections -fno-common -fmessage-length=0)
|
||||||
|
|
||||||
|
# uncomment to mitigate c++17 absolute addresses warnings
|
||||||
|
#set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wno-register")
|
||||||
|
|
||||||
|
# Enable assembler files preprocessing
|
||||||
|
add_compile_options($<$<COMPILE_LANGUAGE:ASM>:-x$<SEMICOLON>assembler-with-cpp>)
|
||||||
|
|
||||||
|
if ("${CMAKE_BUILD_TYPE}" STREQUAL "Release")
|
||||||
|
message(STATUS "Maximum optimization for speed")
|
||||||
|
add_compile_options(-Ofast)
|
||||||
|
elseif ("${CMAKE_BUILD_TYPE}" STREQUAL "RelWithDebInfo")
|
||||||
|
message(STATUS "Maximum optimization for speed, debug info included")
|
||||||
|
add_compile_options(-Ofast -g)
|
||||||
|
elseif ("${CMAKE_BUILD_TYPE}" STREQUAL "MinSizeRel")
|
||||||
|
message(STATUS "Maximum optimization for size")
|
||||||
|
add_compile_options(-Os)
|
||||||
|
else ()
|
||||||
|
message(STATUS "Minimal optimization, debug info included")
|
||||||
|
add_compile_options(-Og -g)
|
||||||
|
endif ()
|
||||||
|
|
||||||
|
include_directories(Core/Inc Drivers/STM32G0xx_HAL_Driver/Inc Drivers/STM32G0xx_HAL_Driver/Inc/Legacy Drivers/CMSIS/Device/ST/STM32G0xx/Include Drivers/CMSIS/Include Core/Interfaces Core/Interfaces/Templates App)
|
||||||
|
include_directories(loader)
|
||||||
|
include_directories(ARMCM0_STM32G0)
|
||||||
|
add_definitions(-DDEBUG -DUSE_FULL_LL_DRIVER -DUSE_HAL_DRIVER -DSTM32G070xx)
|
||||||
|
|
||||||
|
file(GLOB_RECURSE SOURCES "Core/*.*" "Drivers/*.*" "App/*.*" "loader/*.*" "ARMCM0_STM32G0/*.*")
|
||||||
|
list(FILTER SOURCES EXCLUDE REGEX "IAR\\/.*.[c|h]$")
|
||||||
|
list(FILTER SOURCES EXCLUDE REGEX "Keil\\/.*.[c|h]$")
|
||||||
|
set(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/STM32G070CBTX_FLASH.ld)
|
||||||
|
|
||||||
|
add_link_options(-Wl,-gc-sections,--print-memory-usage,-Map=${PROJECT_BINARY_DIR}/${PROJECT_NAME}.map)
|
||||||
|
add_link_options(-mcpu=cortex-m0 -mthumb -mthumb-interwork)
|
||||||
|
add_link_options(-T ${LINKER_SCRIPT})
|
||||||
|
|
||||||
|
add_executable(${PROJECT_NAME}.elf ${SOURCES} ${LINKER_SCRIPT})
|
||||||
|
|
||||||
|
set(HEX_FILE ${PROJECT_BINARY_DIR}/${PROJECT_NAME}.hex)
|
||||||
|
set(BIN_FILE ${PROJECT_BINARY_DIR}/${PROJECT_NAME}.bin)
|
||||||
|
|
||||||
|
add_custom_command(TARGET ${PROJECT_NAME}.elf POST_BUILD
|
||||||
|
COMMAND ${CMAKE_OBJCOPY} -Oihex $<TARGET_FILE:${PROJECT_NAME}.elf> ${HEX_FILE}
|
||||||
|
COMMAND ${CMAKE_OBJCOPY} -Obinary $<TARGET_FILE:${PROJECT_NAME}.elf> ${BIN_FILE}
|
||||||
|
COMMENT "Building ${HEX_FILE}
|
||||||
|
Building ${BIN_FILE}")
|
||||||
49
Boot/Core/Inc/gpio.h
Normal file
49
Boot/Core/Inc/gpio.h
Normal file
@@ -0,0 +1,49 @@
|
|||||||
|
/* USER CODE BEGIN Header */
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file gpio.h
|
||||||
|
* @brief This file contains all the function prototypes for
|
||||||
|
* the gpio.c file
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* Copyright (c) 2023 STMicroelectronics.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* This software is licensed under terms that can be found in the LICENSE file
|
||||||
|
* in the root directory of this software component.
|
||||||
|
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
/* USER CODE END Header */
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __GPIO_H__
|
||||||
|
#define __GPIO_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "main.h"
|
||||||
|
|
||||||
|
/* USER CODE BEGIN Includes */
|
||||||
|
|
||||||
|
/* USER CODE END Includes */
|
||||||
|
|
||||||
|
/* USER CODE BEGIN Private defines */
|
||||||
|
|
||||||
|
/* USER CODE END Private defines */
|
||||||
|
|
||||||
|
void MX_GPIO_Init(void);
|
||||||
|
|
||||||
|
/* USER CODE BEGIN Prototypes */
|
||||||
|
|
||||||
|
/* USER CODE END Prototypes */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
#endif /*__ GPIO_H__ */
|
||||||
|
|
||||||
52
Boot/Core/Inc/i2c.h
Normal file
52
Boot/Core/Inc/i2c.h
Normal file
@@ -0,0 +1,52 @@
|
|||||||
|
/* USER CODE BEGIN Header */
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file i2c.h
|
||||||
|
* @brief This file contains all the function prototypes for
|
||||||
|
* the i2c.c file
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* Copyright (c) 2023 STMicroelectronics.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* This software is licensed under terms that can be found in the LICENSE file
|
||||||
|
* in the root directory of this software component.
|
||||||
|
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
/* USER CODE END Header */
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __I2C_H__
|
||||||
|
#define __I2C_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "main.h"
|
||||||
|
|
||||||
|
/* USER CODE BEGIN Includes */
|
||||||
|
|
||||||
|
/* USER CODE END Includes */
|
||||||
|
|
||||||
|
extern I2C_HandleTypeDef hi2c2;
|
||||||
|
|
||||||
|
/* USER CODE BEGIN Private defines */
|
||||||
|
|
||||||
|
/* USER CODE END Private defines */
|
||||||
|
|
||||||
|
void MX_I2C2_Init(void);
|
||||||
|
|
||||||
|
/* USER CODE BEGIN Prototypes */
|
||||||
|
|
||||||
|
/* USER CODE END Prototypes */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __I2C_H__ */
|
||||||
|
|
||||||
86
Boot/Core/Inc/main.h
Normal file
86
Boot/Core/Inc/main.h
Normal file
@@ -0,0 +1,86 @@
|
|||||||
|
/* USER CODE BEGIN Header */
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file : main.h
|
||||||
|
* @brief : Header for main.c file.
|
||||||
|
* This file contains the common defines of the application.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
|
*
|
||||||
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
|
* the "License"; You may not use this file except in compliance with the
|
||||||
|
* License. You may obtain a copy of the License at:
|
||||||
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
/* USER CODE END Header */
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __MAIN_H
|
||||||
|
#define __MAIN_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32g0xx_hal.h"
|
||||||
|
|
||||||
|
#include "stm32g0xx_ll_usart.h"
|
||||||
|
#include "stm32g0xx_ll_rcc.h"
|
||||||
|
#include "stm32g0xx_ll_bus.h"
|
||||||
|
#include "stm32g0xx_ll_cortex.h"
|
||||||
|
#include "stm32g0xx_ll_system.h"
|
||||||
|
#include "stm32g0xx_ll_utils.h"
|
||||||
|
#include "stm32g0xx_ll_pwr.h"
|
||||||
|
#include "stm32g0xx_ll_gpio.h"
|
||||||
|
#include "stm32g0xx_ll_dma.h"
|
||||||
|
|
||||||
|
#include "stm32g0xx_ll_exti.h"
|
||||||
|
|
||||||
|
/* Private includes ----------------------------------------------------------*/
|
||||||
|
/* USER CODE BEGIN Includes */
|
||||||
|
|
||||||
|
/* USER CODE END Includes */
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
/* USER CODE BEGIN ET */
|
||||||
|
|
||||||
|
/* USER CODE END ET */
|
||||||
|
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/* USER CODE BEGIN EC */
|
||||||
|
|
||||||
|
/* USER CODE END EC */
|
||||||
|
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
/* USER CODE BEGIN EM */
|
||||||
|
|
||||||
|
/* USER CODE END EM */
|
||||||
|
|
||||||
|
/* Exported functions prototypes ---------------------------------------------*/
|
||||||
|
void Error_Handler(void);
|
||||||
|
|
||||||
|
/* USER CODE BEGIN EFP */
|
||||||
|
|
||||||
|
/* USER CODE END EFP */
|
||||||
|
|
||||||
|
/* Private defines -----------------------------------------------------------*/
|
||||||
|
#define READER_EN_Pin GPIO_PIN_5
|
||||||
|
#define READER_EN_GPIO_Port GPIOA
|
||||||
|
#define ZUMMER_PINOUT_Pin GPIO_PIN_5
|
||||||
|
#define ZUMMER_PINOUT_GPIO_Port GPIOB
|
||||||
|
|
||||||
|
/* USER CODE BEGIN Private defines */
|
||||||
|
|
||||||
|
/* USER CODE END Private defines */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __MAIN_H */
|
||||||
53
Boot/Core/Inc/stm32_assert.h
Normal file
53
Boot/Core/Inc/stm32_assert.h
Normal file
@@ -0,0 +1,53 @@
|
|||||||
|
/* USER CODE BEGIN Header */
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32_assert.h
|
||||||
|
* @brief STM32 assert file.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* Copyright (c) 2018 STMicroelectronics.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* This software is licensed under terms that can be found in the LICENSE file
|
||||||
|
* in the root directory of this software component.
|
||||||
|
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
/* USER CODE END Header */
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32_ASSERT_H
|
||||||
|
#define __STM32_ASSERT_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
#ifdef USE_FULL_ASSERT
|
||||||
|
/**
|
||||||
|
* @brief The assert_param macro is used for function's parameters check.
|
||||||
|
* @param expr: If expr is false, it calls assert_failed function
|
||||||
|
* which reports the name of the source file and the source
|
||||||
|
* line number of the call that failed.
|
||||||
|
* If expr is true, it returns no value.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||||
|
/* Exported functions ------------------------------------------------------- */
|
||||||
|
void assert_failed(uint8_t* file, uint32_t line);
|
||||||
|
#else
|
||||||
|
#define assert_param(expr) ((void)0U)
|
||||||
|
#endif /* USE_FULL_ASSERT */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32_ASSERT_H */
|
||||||
|
|
||||||
351
Boot/Core/Inc/stm32g0xx_hal_conf.h
Normal file
351
Boot/Core/Inc/stm32g0xx_hal_conf.h
Normal file
@@ -0,0 +1,351 @@
|
|||||||
|
/* USER CODE BEGIN Header */
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32g0xx_hal_conf.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @brief HAL configuration file.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* Copyright (c) 2018 STMicroelectronics.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* This software is licensed under terms that can be found in the LICENSE file
|
||||||
|
* in the root directory of this software component.
|
||||||
|
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
/* USER CODE END Header */
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef STM32G0xx_HAL_CONF_H
|
||||||
|
#define STM32G0xx_HAL_CONF_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* ########################## Module Selection ############################## */
|
||||||
|
/**
|
||||||
|
* @brief This is the list of modules to be used in the HAL driver
|
||||||
|
*/
|
||||||
|
#define HAL_MODULE_ENABLED
|
||||||
|
/* #define HAL_ADC_MODULE_ENABLED */
|
||||||
|
/* #define HAL_CEC_MODULE_ENABLED */
|
||||||
|
/* #define HAL_COMP_MODULE_ENABLED */
|
||||||
|
/* #define HAL_CRC_MODULE_ENABLED */
|
||||||
|
/* #define HAL_CRYP_MODULE_ENABLED */
|
||||||
|
/* #define HAL_DAC_MODULE_ENABLED */
|
||||||
|
/* #define HAL_EXTI_MODULE_ENABLED */
|
||||||
|
/* #define HAL_FDCAN_MODULE_ENABLED */
|
||||||
|
/* #define HAL_HCD_MODULE_ENABLED */
|
||||||
|
#define HAL_I2C_MODULE_ENABLED
|
||||||
|
/* #define HAL_I2S_MODULE_ENABLED */
|
||||||
|
/* #define HAL_IWDG_MODULE_ENABLED */
|
||||||
|
/* #define HAL_IRDA_MODULE_ENABLED */
|
||||||
|
/* #define HAL_LPTIM_MODULE_ENABLED */
|
||||||
|
/* #define HAL_PCD_MODULE_ENABLED */
|
||||||
|
/* #define HAL_RNG_MODULE_ENABLED */
|
||||||
|
/* #define HAL_RTC_MODULE_ENABLED */
|
||||||
|
/* #define HAL_SMARTCARD_MODULE_ENABLED */
|
||||||
|
/* #define HAL_SMBUS_MODULE_ENABLED */
|
||||||
|
/* #define HAL_SPI_MODULE_ENABLED */
|
||||||
|
#define HAL_TIM_MODULE_ENABLED
|
||||||
|
/* #define HAL_UART_MODULE_ENABLED */
|
||||||
|
/* #define HAL_USART_MODULE_ENABLED */
|
||||||
|
/* #define HAL_WWDG_MODULE_ENABLED */
|
||||||
|
#define HAL_GPIO_MODULE_ENABLED
|
||||||
|
#define HAL_EXTI_MODULE_ENABLED
|
||||||
|
#define HAL_DMA_MODULE_ENABLED
|
||||||
|
#define HAL_RCC_MODULE_ENABLED
|
||||||
|
#define HAL_FLASH_MODULE_ENABLED
|
||||||
|
#define HAL_PWR_MODULE_ENABLED
|
||||||
|
#define HAL_CORTEX_MODULE_ENABLED
|
||||||
|
|
||||||
|
/* ########################## Register Callbacks selection ############################## */
|
||||||
|
/**
|
||||||
|
* @brief This is the list of modules where register callback can be used
|
||||||
|
*/
|
||||||
|
#define USE_HAL_ADC_REGISTER_CALLBACKS 0u
|
||||||
|
#define USE_HAL_CEC_REGISTER_CALLBACKS 0u
|
||||||
|
#define USE_HAL_COMP_REGISTER_CALLBACKS 0u
|
||||||
|
#define USE_HAL_CRYP_REGISTER_CALLBACKS 0u
|
||||||
|
#define USE_HAL_DAC_REGISTER_CALLBACKS 0u
|
||||||
|
#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0u
|
||||||
|
#define USE_HAL_HCD_REGISTER_CALLBACKS 0u
|
||||||
|
#define USE_HAL_I2C_REGISTER_CALLBACKS 0u
|
||||||
|
#define USE_HAL_I2S_REGISTER_CALLBACKS 0u
|
||||||
|
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0u
|
||||||
|
#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0u
|
||||||
|
#define USE_HAL_PCD_REGISTER_CALLBACKS 0u
|
||||||
|
#define USE_HAL_RNG_REGISTER_CALLBACKS 0u
|
||||||
|
#define USE_HAL_RTC_REGISTER_CALLBACKS 0u
|
||||||
|
#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0u
|
||||||
|
#define USE_HAL_SPI_REGISTER_CALLBACKS 0u
|
||||||
|
#define USE_HAL_TIM_REGISTER_CALLBACKS 0u
|
||||||
|
#define USE_HAL_UART_REGISTER_CALLBACKS 0u
|
||||||
|
#define USE_HAL_USART_REGISTER_CALLBACKS 0u
|
||||||
|
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0u
|
||||||
|
|
||||||
|
/* ########################## Oscillator Values adaptation ####################*/
|
||||||
|
/**
|
||||||
|
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
|
||||||
|
* This value is used by the RCC HAL module to compute the system frequency
|
||||||
|
* (when HSE is used as system clock source, directly or through the PLL).
|
||||||
|
*/
|
||||||
|
#if !defined (HSE_VALUE)
|
||||||
|
#define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */
|
||||||
|
#endif /* HSE_VALUE */
|
||||||
|
|
||||||
|
#if !defined (HSE_STARTUP_TIMEOUT)
|
||||||
|
#define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */
|
||||||
|
#endif /* HSE_STARTUP_TIMEOUT */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Internal High Speed oscillator (HSI) value.
|
||||||
|
* This value is used by the RCC HAL module to compute the system frequency
|
||||||
|
* (when HSI is used as system clock source, directly or through the PLL).
|
||||||
|
*/
|
||||||
|
#if !defined (HSI_VALUE)
|
||||||
|
#define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/
|
||||||
|
#endif /* HSI_VALUE */
|
||||||
|
|
||||||
|
#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
|
||||||
|
/**
|
||||||
|
* @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG.
|
||||||
|
* This internal oscillator is mainly dedicated to provide a high precision clock to
|
||||||
|
* the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
|
||||||
|
* When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
|
||||||
|
* which is subject to manufacturing process variations.
|
||||||
|
*/
|
||||||
|
#if !defined (HSI48_VALUE)
|
||||||
|
#define HSI48_VALUE 48000000U /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
|
||||||
|
The real value my vary depending on manufacturing process variations.*/
|
||||||
|
#endif /* HSI48_VALUE */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Internal Low Speed oscillator (LSI) value.
|
||||||
|
*/
|
||||||
|
#if !defined (LSI_VALUE)
|
||||||
|
#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/
|
||||||
|
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
|
||||||
|
The real value may vary depending on the variations
|
||||||
|
in voltage and temperature.*/
|
||||||
|
/**
|
||||||
|
* @brief External Low Speed oscillator (LSE) value.
|
||||||
|
* This value is used by the UART, RTC HAL module to compute the system frequency
|
||||||
|
*/
|
||||||
|
#if !defined (LSE_VALUE)
|
||||||
|
#define LSE_VALUE (32768UL) /*!< Value of the External oscillator in Hz*/
|
||||||
|
#endif /* LSE_VALUE */
|
||||||
|
|
||||||
|
#if !defined (LSE_STARTUP_TIMEOUT)
|
||||||
|
#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */
|
||||||
|
#endif /* LSE_STARTUP_TIMEOUT */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief External clock source for I2S1 peripheral
|
||||||
|
* This value is used by the RCC HAL module to compute the I2S1 clock source
|
||||||
|
* frequency.
|
||||||
|
*/
|
||||||
|
#if !defined (EXTERNAL_I2S1_CLOCK_VALUE)
|
||||||
|
#define EXTERNAL_I2S1_CLOCK_VALUE (48000UL) /*!< Value of the I2S1 External clock source in Hz*/
|
||||||
|
#endif /* EXTERNAL_I2S1_CLOCK_VALUE */
|
||||||
|
|
||||||
|
#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
|
||||||
|
/**
|
||||||
|
* @brief External clock source for I2S2 peripheral
|
||||||
|
* This value is used by the RCC HAL module to compute the I2S2 clock source
|
||||||
|
* frequency.
|
||||||
|
*/
|
||||||
|
#if !defined (EXTERNAL_I2S2_CLOCK_VALUE)
|
||||||
|
#define EXTERNAL_I2S2_CLOCK_VALUE 48000U /*!< Value of the I2S2 External clock source in Hz*/
|
||||||
|
#endif /* EXTERNAL_I2S2_CLOCK_VALUE */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Tip: To avoid modifying this file each time you need to use different HSE,
|
||||||
|
=== you can define the HSE value in your toolchain compiler preprocessor. */
|
||||||
|
|
||||||
|
/* ########################### System Configuration ######################### */
|
||||||
|
/**
|
||||||
|
* @brief This is the HAL system configuration section
|
||||||
|
*/
|
||||||
|
#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */
|
||||||
|
#define TICK_INT_PRIORITY 3U /*!< tick interrupt priority */
|
||||||
|
#define USE_RTOS 0U
|
||||||
|
#define PREFETCH_ENABLE 1U
|
||||||
|
#define INSTRUCTION_CACHE_ENABLE 1U
|
||||||
|
|
||||||
|
/* ################## SPI peripheral configuration ########################## */
|
||||||
|
|
||||||
|
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
|
||||||
|
* Activated: CRC code is present inside driver
|
||||||
|
* Deactivated: CRC code cleaned from driver
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define USE_SPI_CRC 0U
|
||||||
|
|
||||||
|
/* ################## CRYP peripheral configuration ########################## */
|
||||||
|
|
||||||
|
#define USE_HAL_CRYP_SUSPEND_RESUME 1U
|
||||||
|
|
||||||
|
/* ########################## Assert Selection ############################## */
|
||||||
|
/**
|
||||||
|
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
||||||
|
* HAL drivers code
|
||||||
|
*/
|
||||||
|
/* #define USE_FULL_ASSERT 1U */
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
/**
|
||||||
|
* @brief Include modules header file
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef HAL_RCC_MODULE_ENABLED
|
||||||
|
#include "stm32g0xx_hal_rcc.h"
|
||||||
|
#endif /* HAL_RCC_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||||
|
#include "stm32g0xx_hal_gpio.h"
|
||||||
|
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_DMA_MODULE_ENABLED
|
||||||
|
#include "stm32g0xx_hal_dma.h"
|
||||||
|
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||||
|
#include "stm32g0xx_hal_cortex.h"
|
||||||
|
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_ADC_MODULE_ENABLED
|
||||||
|
#include "stm32g0xx_hal_adc.h"
|
||||||
|
#include "stm32g0xx_hal_adc_ex.h"
|
||||||
|
#endif /* HAL_ADC_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_CEC_MODULE_ENABLED
|
||||||
|
#include "stm32g0xx_hal_cec.h"
|
||||||
|
#endif /* HAL_CEC_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_COMP_MODULE_ENABLED
|
||||||
|
#include "stm32g0xx_hal_comp.h"
|
||||||
|
#endif /* HAL_COMP_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_CRC_MODULE_ENABLED
|
||||||
|
#include "stm32g0xx_hal_crc.h"
|
||||||
|
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_CRYP_MODULE_ENABLED
|
||||||
|
#include "stm32g0xx_hal_cryp.h"
|
||||||
|
#endif /* HAL_CRYP_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_DAC_MODULE_ENABLED
|
||||||
|
#include "stm32g0xx_hal_dac.h"
|
||||||
|
#endif /* HAL_DAC_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_EXTI_MODULE_ENABLED
|
||||||
|
#include "stm32g0xx_hal_exti.h"
|
||||||
|
#endif /* HAL_EXTI_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||||
|
#include "stm32g0xx_hal_flash.h"
|
||||||
|
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_FDCAN_MODULE_ENABLED
|
||||||
|
#include "stm32g0xx_hal_fdcan.h"
|
||||||
|
#endif /* HAL_FDCAN_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_HCD_MODULE_ENABLED
|
||||||
|
#include "stm32g0xx_hal_hcd.h"
|
||||||
|
#endif /* HAL_HCD_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_I2C_MODULE_ENABLED
|
||||||
|
#include "stm32g0xx_hal_i2c.h"
|
||||||
|
#endif /* HAL_I2C_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_I2S_MODULE_ENABLED
|
||||||
|
#include "stm32g0xx_hal_i2s.h"
|
||||||
|
#endif /* HAL_I2S_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_IRDA_MODULE_ENABLED
|
||||||
|
#include "stm32g0xx_hal_irda.h"
|
||||||
|
#endif /* HAL_IRDA_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_IWDG_MODULE_ENABLED
|
||||||
|
#include "stm32g0xx_hal_iwdg.h"
|
||||||
|
#endif /* HAL_IWDG_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_LPTIM_MODULE_ENABLED
|
||||||
|
#include "stm32g0xx_hal_lptim.h"
|
||||||
|
#endif /* HAL_LPTIM_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_PCD_MODULE_ENABLED
|
||||||
|
#include "stm32g0xx_hal_pcd.h"
|
||||||
|
#endif /* HAL_PCD_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_PWR_MODULE_ENABLED
|
||||||
|
#include "stm32g0xx_hal_pwr.h"
|
||||||
|
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_RNG_MODULE_ENABLED
|
||||||
|
#include "stm32g0xx_hal_rng.h"
|
||||||
|
#endif /* HAL_RNG_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_RTC_MODULE_ENABLED
|
||||||
|
#include "stm32g0xx_hal_rtc.h"
|
||||||
|
#endif /* HAL_RTC_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_SMARTCARD_MODULE_ENABLED
|
||||||
|
#include "stm32g0xx_hal_smartcard.h"
|
||||||
|
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_SMBUS_MODULE_ENABLED
|
||||||
|
#include "stm32g0xx_hal_smbus.h"
|
||||||
|
#endif /* HAL_SMBUS_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_SPI_MODULE_ENABLED
|
||||||
|
#include "stm32g0xx_hal_spi.h"
|
||||||
|
#endif /* HAL_SPI_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_TIM_MODULE_ENABLED
|
||||||
|
#include "stm32g0xx_hal_tim.h"
|
||||||
|
#endif /* HAL_TIM_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_UART_MODULE_ENABLED
|
||||||
|
#include "stm32g0xx_hal_uart.h"
|
||||||
|
#endif /* HAL_UART_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_USART_MODULE_ENABLED
|
||||||
|
#include "stm32g0xx_hal_usart.h"
|
||||||
|
#endif /* HAL_USART_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_WWDG_MODULE_ENABLED
|
||||||
|
#include "stm32g0xx_hal_wwdg.h"
|
||||||
|
#endif /* HAL_WWDG_MODULE_ENABLED */
|
||||||
|
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
#ifdef USE_FULL_ASSERT
|
||||||
|
/**
|
||||||
|
* @brief The assert_param macro is used for functions parameters check.
|
||||||
|
* @param expr If expr is false, it calls assert_failed function
|
||||||
|
* which reports the name of the source file and the source
|
||||||
|
* line number of the call that failed.
|
||||||
|
* If expr is true, it returns no value.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||||
|
/* Exported functions ------------------------------------------------------- */
|
||||||
|
void assert_failed(uint8_t *file, uint32_t line);
|
||||||
|
#else
|
||||||
|
#define assert_param(expr) ((void)0U)
|
||||||
|
#endif /* USE_FULL_ASSERT */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* STM32G0xx_HAL_CONF_H */
|
||||||
65
Boot/Core/Inc/stm32g0xx_it.h
Normal file
65
Boot/Core/Inc/stm32g0xx_it.h
Normal file
@@ -0,0 +1,65 @@
|
|||||||
|
/* USER CODE BEGIN Header */
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32g0xx_it.h
|
||||||
|
* @brief This file contains the headers of the interrupt handlers.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
|
*
|
||||||
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
|
* the "License"; You may not use this file except in compliance with the
|
||||||
|
* License. You may obtain a copy of the License at:
|
||||||
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
/* USER CODE END Header */
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __STM32G0xx_IT_H
|
||||||
|
#define __STM32G0xx_IT_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Private includes ----------------------------------------------------------*/
|
||||||
|
/* USER CODE BEGIN Includes */
|
||||||
|
|
||||||
|
/* USER CODE END Includes */
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
/* USER CODE BEGIN ET */
|
||||||
|
|
||||||
|
/* USER CODE END ET */
|
||||||
|
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/* USER CODE BEGIN EC */
|
||||||
|
|
||||||
|
/* USER CODE END EC */
|
||||||
|
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
/* USER CODE BEGIN EM */
|
||||||
|
|
||||||
|
/* USER CODE END EM */
|
||||||
|
|
||||||
|
/* Exported functions prototypes ---------------------------------------------*/
|
||||||
|
void NMI_Handler(void);
|
||||||
|
void HardFault_Handler(void);
|
||||||
|
void SVC_Handler(void);
|
||||||
|
void PendSV_Handler(void);
|
||||||
|
void SysTick_Handler(void);
|
||||||
|
void USART1_IRQHandler(void);
|
||||||
|
void USART2_IRQHandler(void);
|
||||||
|
/* USER CODE BEGIN EFP */
|
||||||
|
|
||||||
|
/* USER CODE END EFP */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __STM32G0xx_IT_H */
|
||||||
52
Boot/Core/Inc/tim.h
Normal file
52
Boot/Core/Inc/tim.h
Normal file
@@ -0,0 +1,52 @@
|
|||||||
|
/* USER CODE BEGIN Header */
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file tim.h
|
||||||
|
* @brief This file contains all the function prototypes for
|
||||||
|
* the tim.c file
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* Copyright (c) 2023 STMicroelectronics.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* This software is licensed under terms that can be found in the LICENSE file
|
||||||
|
* in the root directory of this software component.
|
||||||
|
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
/* USER CODE END Header */
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __TIM_H__
|
||||||
|
#define __TIM_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "main.h"
|
||||||
|
|
||||||
|
/* USER CODE BEGIN Includes */
|
||||||
|
|
||||||
|
/* USER CODE END Includes */
|
||||||
|
|
||||||
|
extern TIM_HandleTypeDef htim3;
|
||||||
|
|
||||||
|
/* USER CODE BEGIN Private defines */
|
||||||
|
|
||||||
|
/* USER CODE END Private defines */
|
||||||
|
|
||||||
|
void MX_TIM3_Init(void);
|
||||||
|
|
||||||
|
/* USER CODE BEGIN Prototypes */
|
||||||
|
|
||||||
|
/* USER CODE END Prototypes */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __TIM_H__ */
|
||||||
|
|
||||||
51
Boot/Core/Inc/usart.h
Normal file
51
Boot/Core/Inc/usart.h
Normal file
@@ -0,0 +1,51 @@
|
|||||||
|
/* USER CODE BEGIN Header */
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file usart.h
|
||||||
|
* @brief This file contains all the function prototypes for
|
||||||
|
* the usart.c file
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* Copyright (c) 2023 STMicroelectronics.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* This software is licensed under terms that can be found in the LICENSE file
|
||||||
|
* in the root directory of this software component.
|
||||||
|
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
/* USER CODE END Header */
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef __USART_H__
|
||||||
|
#define __USART_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "main.h"
|
||||||
|
|
||||||
|
/* USER CODE BEGIN Includes */
|
||||||
|
|
||||||
|
/* USER CODE END Includes */
|
||||||
|
|
||||||
|
/* USER CODE BEGIN Private defines */
|
||||||
|
|
||||||
|
/* USER CODE END Private defines */
|
||||||
|
|
||||||
|
void MX_USART1_UART_Init(void);
|
||||||
|
void MX_USART2_UART_Init(void);
|
||||||
|
|
||||||
|
/* USER CODE BEGIN Prototypes */
|
||||||
|
|
||||||
|
/* USER CODE END Prototypes */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __USART_H__ */
|
||||||
|
|
||||||
82
Boot/Core/Src/gpio.c
Normal file
82
Boot/Core/Src/gpio.c
Normal file
@@ -0,0 +1,82 @@
|
|||||||
|
/* USER CODE BEGIN Header */
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file gpio.c
|
||||||
|
* @brief This file provides code for the configuration
|
||||||
|
* of all used GPIO pins.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* Copyright (c) 2023 STMicroelectronics.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* This software is licensed under terms that can be found in the LICENSE file
|
||||||
|
* in the root directory of this software component.
|
||||||
|
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
/* USER CODE END Header */
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "gpio.h"
|
||||||
|
|
||||||
|
/* USER CODE BEGIN 0 */
|
||||||
|
|
||||||
|
/* USER CODE END 0 */
|
||||||
|
|
||||||
|
/*----------------------------------------------------------------------------*/
|
||||||
|
/* Configure GPIO */
|
||||||
|
/*----------------------------------------------------------------------------*/
|
||||||
|
/* USER CODE BEGIN 1 */
|
||||||
|
|
||||||
|
/* USER CODE END 1 */
|
||||||
|
|
||||||
|
/** Configure pins as
|
||||||
|
* Analog
|
||||||
|
* Input
|
||||||
|
* Output
|
||||||
|
* EVENT_OUT
|
||||||
|
* EXTI
|
||||||
|
*/
|
||||||
|
void MX_GPIO_Init(void)
|
||||||
|
{
|
||||||
|
|
||||||
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
||||||
|
|
||||||
|
/* GPIO Ports Clock Enable */
|
||||||
|
__HAL_RCC_GPIOF_CLK_ENABLE();
|
||||||
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||||||
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||||
|
|
||||||
|
/*Configure GPIO pin Output Level */
|
||||||
|
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_4|READER_EN_Pin, GPIO_PIN_RESET);
|
||||||
|
|
||||||
|
/*Configure GPIO pin Output Level */
|
||||||
|
HAL_GPIO_WritePin(ZUMMER_PINOUT_GPIO_Port, ZUMMER_PINOUT_Pin, GPIO_PIN_RESET);
|
||||||
|
|
||||||
|
/*Configure GPIO pins : PA0 PA1 */
|
||||||
|
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
|
||||||
|
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
|
||||||
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||||
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||||
|
|
||||||
|
/*Configure GPIO pins : PA4 PAPin */
|
||||||
|
GPIO_InitStruct.Pin = GPIO_PIN_4|READER_EN_Pin;
|
||||||
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
||||||
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||||
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||||||
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||||
|
|
||||||
|
/*Configure GPIO pin : PtPin */
|
||||||
|
GPIO_InitStruct.Pin = ZUMMER_PINOUT_Pin;
|
||||||
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
||||||
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||||
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||||||
|
HAL_GPIO_Init(ZUMMER_PINOUT_GPIO_Port, &GPIO_InitStruct);
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/* USER CODE BEGIN 2 */
|
||||||
|
|
||||||
|
/* USER CODE END 2 */
|
||||||
130
Boot/Core/Src/i2c.c
Normal file
130
Boot/Core/Src/i2c.c
Normal file
@@ -0,0 +1,130 @@
|
|||||||
|
/* USER CODE BEGIN Header */
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file i2c.c
|
||||||
|
* @brief This file provides code for the configuration
|
||||||
|
* of the I2C instances.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* Copyright (c) 2023 STMicroelectronics.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* This software is licensed under terms that can be found in the LICENSE file
|
||||||
|
* in the root directory of this software component.
|
||||||
|
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
/* USER CODE END Header */
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "i2c.h"
|
||||||
|
|
||||||
|
/* USER CODE BEGIN 0 */
|
||||||
|
|
||||||
|
/* USER CODE END 0 */
|
||||||
|
|
||||||
|
I2C_HandleTypeDef hi2c2;
|
||||||
|
|
||||||
|
/* I2C2 init function */
|
||||||
|
void MX_I2C2_Init(void)
|
||||||
|
{
|
||||||
|
|
||||||
|
/* USER CODE BEGIN I2C2_Init 0 */
|
||||||
|
|
||||||
|
/* USER CODE END I2C2_Init 0 */
|
||||||
|
|
||||||
|
/* USER CODE BEGIN I2C2_Init 1 */
|
||||||
|
|
||||||
|
/* USER CODE END I2C2_Init 1 */
|
||||||
|
hi2c2.Instance = I2C2;
|
||||||
|
hi2c2.Init.Timing = 0x00303D5B;
|
||||||
|
hi2c2.Init.OwnAddress1 = 0;
|
||||||
|
hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
|
||||||
|
hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
|
||||||
|
hi2c2.Init.OwnAddress2 = 0;
|
||||||
|
hi2c2.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
|
||||||
|
hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
|
||||||
|
hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
|
||||||
|
if (HAL_I2C_Init(&hi2c2) != HAL_OK)
|
||||||
|
{
|
||||||
|
Error_Handler();
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Configure Analogue filter
|
||||||
|
*/
|
||||||
|
if (HAL_I2CEx_ConfigAnalogFilter(&hi2c2, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
|
||||||
|
{
|
||||||
|
Error_Handler();
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Configure Digital filter
|
||||||
|
*/
|
||||||
|
if (HAL_I2CEx_ConfigDigitalFilter(&hi2c2, 0) != HAL_OK)
|
||||||
|
{
|
||||||
|
Error_Handler();
|
||||||
|
}
|
||||||
|
/* USER CODE BEGIN I2C2_Init 2 */
|
||||||
|
|
||||||
|
/* USER CODE END I2C2_Init 2 */
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle)
|
||||||
|
{
|
||||||
|
|
||||||
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
||||||
|
if(i2cHandle->Instance==I2C2)
|
||||||
|
{
|
||||||
|
/* USER CODE BEGIN I2C2_MspInit 0 */
|
||||||
|
|
||||||
|
/* USER CODE END I2C2_MspInit 0 */
|
||||||
|
|
||||||
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||||||
|
/**I2C2 GPIO Configuration
|
||||||
|
PA11 [PA9] ------> I2C2_SCL
|
||||||
|
PA12 [PA10] ------> I2C2_SDA
|
||||||
|
*/
|
||||||
|
GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
|
||||||
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
|
||||||
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||||
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||||||
|
GPIO_InitStruct.Alternate = GPIO_AF6_I2C2;
|
||||||
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||||
|
|
||||||
|
/* I2C2 clock enable */
|
||||||
|
__HAL_RCC_I2C2_CLK_ENABLE();
|
||||||
|
/* USER CODE BEGIN I2C2_MspInit 1 */
|
||||||
|
|
||||||
|
/* USER CODE END I2C2_MspInit 1 */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void HAL_I2C_MspDeInit(I2C_HandleTypeDef* i2cHandle)
|
||||||
|
{
|
||||||
|
|
||||||
|
if(i2cHandle->Instance==I2C2)
|
||||||
|
{
|
||||||
|
/* USER CODE BEGIN I2C2_MspDeInit 0 */
|
||||||
|
|
||||||
|
/* USER CODE END I2C2_MspDeInit 0 */
|
||||||
|
/* Peripheral clock disable */
|
||||||
|
__HAL_RCC_I2C2_CLK_DISABLE();
|
||||||
|
|
||||||
|
/**I2C2 GPIO Configuration
|
||||||
|
PA11 [PA9] ------> I2C2_SCL
|
||||||
|
PA12 [PA10] ------> I2C2_SDA
|
||||||
|
*/
|
||||||
|
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11);
|
||||||
|
|
||||||
|
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_12);
|
||||||
|
|
||||||
|
/* USER CODE BEGIN I2C2_MspDeInit 1 */
|
||||||
|
|
||||||
|
/* USER CODE END I2C2_MspDeInit 1 */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* USER CODE BEGIN 1 */
|
||||||
|
|
||||||
|
/* USER CODE END 1 */
|
||||||
184
Boot/Core/Src/main.c
Normal file
184
Boot/Core/Src/main.c
Normal file
@@ -0,0 +1,184 @@
|
|||||||
|
/* USER CODE BEGIN Header */
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file : main.c
|
||||||
|
* @brief : Main program body
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
|
*
|
||||||
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
|
* the "License"; You may not use this file except in compliance with the
|
||||||
|
* License. You may obtain a copy of the License at:
|
||||||
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
/* USER CODE END Header */
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "main.h"
|
||||||
|
#include "i2c.h"
|
||||||
|
#include "tim.h"
|
||||||
|
#include "usart.h"
|
||||||
|
#include "gpio.h"
|
||||||
|
|
||||||
|
/* Private includes ----------------------------------------------------------*/
|
||||||
|
/* USER CODE BEGIN Includes */
|
||||||
|
#include "app.h"
|
||||||
|
/* USER CODE END Includes */
|
||||||
|
|
||||||
|
/* Private typedef -----------------------------------------------------------*/
|
||||||
|
/* USER CODE BEGIN PTD */
|
||||||
|
|
||||||
|
/* USER CODE END PTD */
|
||||||
|
|
||||||
|
/* Private define ------------------------------------------------------------*/
|
||||||
|
/* USER CODE BEGIN PD */
|
||||||
|
/* USER CODE END PD */
|
||||||
|
|
||||||
|
/* Private macro -------------------------------------------------------------*/
|
||||||
|
/* USER CODE BEGIN PM */
|
||||||
|
|
||||||
|
/* USER CODE END PM */
|
||||||
|
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* USER CODE BEGIN PV */
|
||||||
|
|
||||||
|
/* USER CODE END PV */
|
||||||
|
|
||||||
|
/* Private function prototypes -----------------------------------------------*/
|
||||||
|
void SystemClock_Config(void);
|
||||||
|
/* USER CODE BEGIN PFP */
|
||||||
|
|
||||||
|
/* USER CODE END PFP */
|
||||||
|
|
||||||
|
/* Private user code ---------------------------------------------------------*/
|
||||||
|
/* USER CODE BEGIN 0 */
|
||||||
|
|
||||||
|
/* USER CODE END 0 */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief The application entry point.
|
||||||
|
* @retval int
|
||||||
|
*/
|
||||||
|
int main(void)
|
||||||
|
{
|
||||||
|
/* USER CODE BEGIN 1 */
|
||||||
|
|
||||||
|
/* USER CODE END 1 */
|
||||||
|
|
||||||
|
/* MCU Configuration--------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
|
||||||
|
HAL_Init();
|
||||||
|
|
||||||
|
/* USER CODE BEGIN Init */
|
||||||
|
|
||||||
|
/* USER CODE END Init */
|
||||||
|
|
||||||
|
/* Configure the system clock */
|
||||||
|
SystemClock_Config();
|
||||||
|
|
||||||
|
/* USER CODE BEGIN SysInit */
|
||||||
|
|
||||||
|
/* USER CODE END SysInit */
|
||||||
|
|
||||||
|
/* Initialize all configured peripherals */
|
||||||
|
MX_GPIO_Init();
|
||||||
|
MX_I2C2_Init();
|
||||||
|
MX_TIM3_Init();
|
||||||
|
MX_USART1_UART_Init();
|
||||||
|
MX_USART2_UART_Init();
|
||||||
|
/* USER CODE BEGIN 2 */
|
||||||
|
/* Initialize the bootloader application. */
|
||||||
|
AppInit();
|
||||||
|
/* USER CODE END 2 */
|
||||||
|
|
||||||
|
/* Infinite loop */
|
||||||
|
/* USER CODE BEGIN WHILE */
|
||||||
|
while (1)
|
||||||
|
{
|
||||||
|
/* Run the bootloader application. */
|
||||||
|
AppTask();
|
||||||
|
/* USER CODE END WHILE */
|
||||||
|
|
||||||
|
/* USER CODE BEGIN 3 */
|
||||||
|
}
|
||||||
|
/* USER CODE END 3 */
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief System Clock Configuration
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SystemClock_Config(void)
|
||||||
|
{
|
||||||
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||||
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||||
|
|
||||||
|
/** Configure the main internal regulator output voltage
|
||||||
|
*/
|
||||||
|
HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
|
||||||
|
|
||||||
|
/** Initializes the RCC Oscillators according to the specified parameters
|
||||||
|
* in the RCC_OscInitTypeDef structure.
|
||||||
|
*/
|
||||||
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
|
||||||
|
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
||||||
|
RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
|
||||||
|
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
|
||||||
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
|
||||||
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
||||||
|
{
|
||||||
|
Error_Handler();
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Initializes the CPU, AHB and APB buses clocks
|
||||||
|
*/
|
||||||
|
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|
||||||
|
|RCC_CLOCKTYPE_PCLK1;
|
||||||
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
|
||||||
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
||||||
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
|
||||||
|
|
||||||
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
|
||||||
|
{
|
||||||
|
Error_Handler();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* USER CODE BEGIN 4 */
|
||||||
|
|
||||||
|
/* USER CODE END 4 */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function is executed in case of error occurrence.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void Error_Handler(void)
|
||||||
|
{
|
||||||
|
/* USER CODE BEGIN Error_Handler_Debug */
|
||||||
|
/* User can add his own implementation to report the HAL error return state */
|
||||||
|
|
||||||
|
/* USER CODE END Error_Handler_Debug */
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef USE_FULL_ASSERT
|
||||||
|
/**
|
||||||
|
* @brief Reports the name of the source file and the source line number
|
||||||
|
* where the assert_param error has occurred.
|
||||||
|
* @param file: pointer to the source file name
|
||||||
|
* @param line: assert_param error line source number
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void assert_failed(uint8_t *file, uint32_t line)
|
||||||
|
{
|
||||||
|
/* USER CODE BEGIN 6 */
|
||||||
|
/* User can add his own implementation to report the file name and line number,
|
||||||
|
tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
|
||||||
|
/* USER CODE END 6 */
|
||||||
|
}
|
||||||
|
#endif /* USE_FULL_ASSERT */
|
||||||
111
Boot/Core/Src/stm32g0xx_hal_msp.c
Normal file
111
Boot/Core/Src/stm32g0xx_hal_msp.c
Normal file
@@ -0,0 +1,111 @@
|
|||||||
|
/* USER CODE BEGIN Header */
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* File Name : stm32g0xx_hal_msp.c
|
||||||
|
* Description : This file provides code for the MSP Initialization
|
||||||
|
* and de-Initialization codes.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
|
*
|
||||||
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
|
* the "License"; You may not use this file except in compliance with the
|
||||||
|
* License. You may obtain a copy of the License at:
|
||||||
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
/* USER CODE END Header */
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "main.h"
|
||||||
|
/* USER CODE BEGIN Includes */
|
||||||
|
|
||||||
|
/* USER CODE END Includes */
|
||||||
|
|
||||||
|
/* Private typedef -----------------------------------------------------------*/
|
||||||
|
/* USER CODE BEGIN TD */
|
||||||
|
|
||||||
|
/* USER CODE END TD */
|
||||||
|
|
||||||
|
/* Private define ------------------------------------------------------------*/
|
||||||
|
/* USER CODE BEGIN Define */
|
||||||
|
|
||||||
|
/* USER CODE END Define */
|
||||||
|
|
||||||
|
/* Private macro -------------------------------------------------------------*/
|
||||||
|
/* USER CODE BEGIN Macro */
|
||||||
|
|
||||||
|
/* USER CODE END Macro */
|
||||||
|
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* USER CODE BEGIN PV */
|
||||||
|
|
||||||
|
/* USER CODE END PV */
|
||||||
|
|
||||||
|
/* Private function prototypes -----------------------------------------------*/
|
||||||
|
/* USER CODE BEGIN PFP */
|
||||||
|
|
||||||
|
/* USER CODE END PFP */
|
||||||
|
|
||||||
|
/* External functions --------------------------------------------------------*/
|
||||||
|
/* USER CODE BEGIN ExternalFunctions */
|
||||||
|
|
||||||
|
/* USER CODE END ExternalFunctions */
|
||||||
|
|
||||||
|
/* USER CODE BEGIN 0 */
|
||||||
|
|
||||||
|
/* USER CODE END 0 */
|
||||||
|
/**
|
||||||
|
* Initializes the Global MSP.
|
||||||
|
*/
|
||||||
|
void HAL_MspInit(void)
|
||||||
|
{
|
||||||
|
/* USER CODE BEGIN MspInit 0 */
|
||||||
|
|
||||||
|
/* USER CODE END MspInit 0 */
|
||||||
|
|
||||||
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||||||
|
__HAL_RCC_PWR_CLK_ENABLE();
|
||||||
|
|
||||||
|
/* System interrupt init*/
|
||||||
|
|
||||||
|
/** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral
|
||||||
|
*/
|
||||||
|
HAL_SYSCFG_StrobeDBattpinsConfig(SYSCFG_CFGR1_UCPD1_STROBE | SYSCFG_CFGR1_UCPD2_STROBE);
|
||||||
|
|
||||||
|
/* USER CODE BEGIN MspInit 1 */
|
||||||
|
|
||||||
|
/* USER CODE END MspInit 1 */
|
||||||
|
}
|
||||||
|
|
||||||
|
/* USER CODE BEGIN 1 */
|
||||||
|
/**
|
||||||
|
* De-Initializes the Global MSP.
|
||||||
|
*/
|
||||||
|
void HAL_MspDeInit(void)
|
||||||
|
{
|
||||||
|
/* Reset the RCC clock configuration to the default reset state. */
|
||||||
|
HAL_RCC_DeInit();
|
||||||
|
|
||||||
|
/* Reset GPIO pin for the LED to turn it off. */
|
||||||
|
LL_GPIO_ResetOutputPin(GPIOA, LL_GPIO_PIN_5);
|
||||||
|
|
||||||
|
/* Deinit used GPIOs. */
|
||||||
|
LL_GPIO_DeInit(GPIOC);
|
||||||
|
LL_GPIO_DeInit(GPIOA);
|
||||||
|
|
||||||
|
/* UART clock disable. */
|
||||||
|
LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_USART2);
|
||||||
|
|
||||||
|
/* GPIO ports clock disable. */
|
||||||
|
LL_IOP_GRP1_DisableClock(LL_IOP_GRP1_PERIPH_GPIOC);
|
||||||
|
LL_IOP_GRP1_DisableClock(LL_IOP_GRP1_PERIPH_GPIOA);
|
||||||
|
|
||||||
|
/* SYSCFG and PWR clock disable. */
|
||||||
|
LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_PWR);
|
||||||
|
LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SYSCFG);
|
||||||
|
}
|
||||||
|
/* USER CODE END 1 */
|
||||||
170
Boot/Core/Src/stm32g0xx_it.c
Normal file
170
Boot/Core/Src/stm32g0xx_it.c
Normal file
@@ -0,0 +1,170 @@
|
|||||||
|
/* USER CODE BEGIN Header */
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32g0xx_it.c
|
||||||
|
* @brief Interrupt Service Routines.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
|
*
|
||||||
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
|
* the "License"; You may not use this file except in compliance with the
|
||||||
|
* License. You may obtain a copy of the License at:
|
||||||
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
/* USER CODE END Header */
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "main.h"
|
||||||
|
#include "stm32g0xx_it.h"
|
||||||
|
/* Private includes ----------------------------------------------------------*/
|
||||||
|
/* USER CODE BEGIN Includes */
|
||||||
|
/* USER CODE END Includes */
|
||||||
|
|
||||||
|
/* Private typedef -----------------------------------------------------------*/
|
||||||
|
/* USER CODE BEGIN TD */
|
||||||
|
|
||||||
|
/* USER CODE END TD */
|
||||||
|
|
||||||
|
/* Private define ------------------------------------------------------------*/
|
||||||
|
/* USER CODE BEGIN PD */
|
||||||
|
|
||||||
|
/* USER CODE END PD */
|
||||||
|
|
||||||
|
/* Private macro -------------------------------------------------------------*/
|
||||||
|
/* USER CODE BEGIN PM */
|
||||||
|
|
||||||
|
/* USER CODE END PM */
|
||||||
|
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* USER CODE BEGIN PV */
|
||||||
|
|
||||||
|
/* USER CODE END PV */
|
||||||
|
|
||||||
|
/* Private function prototypes -----------------------------------------------*/
|
||||||
|
/* USER CODE BEGIN PFP */
|
||||||
|
|
||||||
|
/* USER CODE END PFP */
|
||||||
|
|
||||||
|
/* Private user code ---------------------------------------------------------*/
|
||||||
|
/* USER CODE BEGIN 0 */
|
||||||
|
|
||||||
|
/* USER CODE END 0 */
|
||||||
|
|
||||||
|
/* External variables --------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* USER CODE BEGIN EV */
|
||||||
|
|
||||||
|
/* USER CODE END EV */
|
||||||
|
|
||||||
|
/******************************************************************************/
|
||||||
|
/* Cortex-M0+ Processor Interruption and Exception Handlers */
|
||||||
|
/******************************************************************************/
|
||||||
|
/**
|
||||||
|
* @brief This function handles Non maskable interrupt.
|
||||||
|
*/
|
||||||
|
void NMI_Handler(void)
|
||||||
|
{
|
||||||
|
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
|
||||||
|
|
||||||
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
||||||
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
||||||
|
|
||||||
|
/* USER CODE END NonMaskableInt_IRQn 1 */
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function handles Hard fault interrupt.
|
||||||
|
*/
|
||||||
|
void HardFault_Handler(void)
|
||||||
|
{
|
||||||
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
||||||
|
|
||||||
|
/* USER CODE END HardFault_IRQn 0 */
|
||||||
|
while (1)
|
||||||
|
{
|
||||||
|
/* USER CODE BEGIN W1_HardFault_IRQn 0 */
|
||||||
|
/* USER CODE END W1_HardFault_IRQn 0 */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function handles System service call via SWI instruction.
|
||||||
|
*/
|
||||||
|
void SVC_Handler(void)
|
||||||
|
{
|
||||||
|
/* USER CODE BEGIN SVC_IRQn 0 */
|
||||||
|
|
||||||
|
/* USER CODE END SVC_IRQn 0 */
|
||||||
|
/* USER CODE BEGIN SVC_IRQn 1 */
|
||||||
|
|
||||||
|
/* USER CODE END SVC_IRQn 1 */
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function handles Pendable request for system service.
|
||||||
|
*/
|
||||||
|
void PendSV_Handler(void)
|
||||||
|
{
|
||||||
|
/* USER CODE BEGIN PendSV_IRQn 0 */
|
||||||
|
|
||||||
|
/* USER CODE END PendSV_IRQn 0 */
|
||||||
|
/* USER CODE BEGIN PendSV_IRQn 1 */
|
||||||
|
|
||||||
|
/* USER CODE END PendSV_IRQn 1 */
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function handles System tick timer.
|
||||||
|
*/
|
||||||
|
void SysTick_Handler(void)
|
||||||
|
{
|
||||||
|
/* USER CODE BEGIN SysTick_IRQn 0 */
|
||||||
|
|
||||||
|
/* USER CODE END SysTick_IRQn 0 */
|
||||||
|
HAL_IncTick();
|
||||||
|
/* USER CODE BEGIN SysTick_IRQn 1 */
|
||||||
|
|
||||||
|
/* USER CODE END SysTick_IRQn 1 */
|
||||||
|
}
|
||||||
|
|
||||||
|
/******************************************************************************/
|
||||||
|
/* STM32G0xx Peripheral Interrupt Handlers */
|
||||||
|
/* Add here the Interrupt Handlers for the used peripherals. */
|
||||||
|
/* For the available peripheral interrupt handler names, */
|
||||||
|
/* please refer to the startup file (startup_stm32g0xx.s). */
|
||||||
|
/******************************************************************************/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function handles USART1 global interrupt / USART1 wake-up interrupt through EXTI line 25.
|
||||||
|
*/
|
||||||
|
void USART1_IRQHandler(void)
|
||||||
|
{
|
||||||
|
/* USER CODE BEGIN USART1_IRQn 0 */
|
||||||
|
|
||||||
|
/* USER CODE END USART1_IRQn 0 */
|
||||||
|
/* USER CODE BEGIN USART1_IRQn 1 */
|
||||||
|
|
||||||
|
/* USER CODE END USART1_IRQn 1 */
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function handles USART2 global interrupt / USART2 wake-up interrupt through EXTI line 26.
|
||||||
|
*/
|
||||||
|
void USART2_IRQHandler(void)
|
||||||
|
{
|
||||||
|
/* USER CODE BEGIN USART2_IRQn 0 */
|
||||||
|
|
||||||
|
/* USER CODE END USART2_IRQn 0 */
|
||||||
|
/* USER CODE BEGIN USART2_IRQn 1 */
|
||||||
|
|
||||||
|
/* USER CODE END USART2_IRQn 1 */
|
||||||
|
}
|
||||||
|
|
||||||
|
/* USER CODE BEGIN 1 */
|
||||||
|
|
||||||
|
/* USER CODE END 1 */
|
||||||
159
Boot/Core/Src/syscalls.c
Normal file
159
Boot/Core/Src/syscalls.c
Normal file
@@ -0,0 +1,159 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file syscalls.c
|
||||||
|
* @author Auto-generated by STM32CubeIDE
|
||||||
|
* @brief STM32CubeIDE Minimal System calls file
|
||||||
|
*
|
||||||
|
* For more information about which c-functions
|
||||||
|
* need which of these lowlevel functions
|
||||||
|
* please consult the Newlib libc-manual
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
|
*
|
||||||
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
|
* the "License"; You may not use this file except in compliance with the
|
||||||
|
* License. You may obtain a copy of the License at:
|
||||||
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Includes */
|
||||||
|
#include <sys/stat.h>
|
||||||
|
#include <stdlib.h>
|
||||||
|
#include <errno.h>
|
||||||
|
#include <stdio.h>
|
||||||
|
#include <signal.h>
|
||||||
|
#include <time.h>
|
||||||
|
#include <sys/time.h>
|
||||||
|
#include <sys/times.h>
|
||||||
|
|
||||||
|
|
||||||
|
/* Variables */
|
||||||
|
//#undef errno
|
||||||
|
extern int errno;
|
||||||
|
extern int __io_putchar(int ch) __attribute__((weak));
|
||||||
|
extern int __io_getchar(void) __attribute__((weak));
|
||||||
|
|
||||||
|
register char * stack_ptr asm("sp");
|
||||||
|
|
||||||
|
char *__env[1] = { 0 };
|
||||||
|
char **environ = __env;
|
||||||
|
|
||||||
|
|
||||||
|
/* Functions */
|
||||||
|
void initialise_monitor_handles()
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
int _getpid(void)
|
||||||
|
{
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
int _kill(int pid, int sig)
|
||||||
|
{
|
||||||
|
errno = EINVAL;
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
void _exit (int status)
|
||||||
|
{
|
||||||
|
_kill(status, -1);
|
||||||
|
while (1) {} /* Make sure we hang here */
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__((weak)) int _read(int file, char *ptr, int len)
|
||||||
|
{
|
||||||
|
int DataIdx;
|
||||||
|
|
||||||
|
for (DataIdx = 0; DataIdx < len; DataIdx++)
|
||||||
|
{
|
||||||
|
*ptr++ = __io_getchar();
|
||||||
|
}
|
||||||
|
|
||||||
|
return len;
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__((weak)) int _write(int file, char *ptr, int len)
|
||||||
|
{
|
||||||
|
int DataIdx;
|
||||||
|
|
||||||
|
for (DataIdx = 0; DataIdx < len; DataIdx++)
|
||||||
|
{
|
||||||
|
__io_putchar(*ptr++);
|
||||||
|
}
|
||||||
|
return len;
|
||||||
|
}
|
||||||
|
|
||||||
|
int _close(int file)
|
||||||
|
{
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
int _fstat(int file, struct stat *st)
|
||||||
|
{
|
||||||
|
st->st_mode = S_IFCHR;
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int _isatty(int file)
|
||||||
|
{
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
int _lseek(int file, int ptr, int dir)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int _open(char *path, int flags, ...)
|
||||||
|
{
|
||||||
|
/* Pretend like we always fail */
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
int _wait(int *status)
|
||||||
|
{
|
||||||
|
errno = ECHILD;
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
int _unlink(char *name)
|
||||||
|
{
|
||||||
|
errno = ENOENT;
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
int _times(struct tms *buf)
|
||||||
|
{
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
int _stat(char *file, struct stat *st)
|
||||||
|
{
|
||||||
|
st->st_mode = S_IFCHR;
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int _link(char *old, char *new)
|
||||||
|
{
|
||||||
|
errno = EMLINK;
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
int _fork(void)
|
||||||
|
{
|
||||||
|
errno = EAGAIN;
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
int _execve(char *name, char **argv, char **env)
|
||||||
|
{
|
||||||
|
errno = ENOMEM;
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
80
Boot/Core/Src/sysmem.c
Normal file
80
Boot/Core/Src/sysmem.c
Normal file
@@ -0,0 +1,80 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file sysmem.c
|
||||||
|
* @author Generated by STM32CubeIDE
|
||||||
|
* @brief STM32CubeIDE System Memory calls file
|
||||||
|
*
|
||||||
|
* For more information about which C functions
|
||||||
|
* need which of these lowlevel functions
|
||||||
|
* please consult the newlib libc manual
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
|
*
|
||||||
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
|
* the "License"; You may not use this file except in compliance with the
|
||||||
|
* License. You may obtain a copy of the License at:
|
||||||
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Includes */
|
||||||
|
#include <errno.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Pointer to the current high watermark of the heap usage
|
||||||
|
*/
|
||||||
|
static uint8_t *__sbrk_heap_end = NULL;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief _sbrk() allocates memory to the newlib heap and is used by malloc
|
||||||
|
* and others from the C library
|
||||||
|
*
|
||||||
|
* @verbatim
|
||||||
|
* ############################################################################
|
||||||
|
* # .data # .bss # newlib heap # MSP stack #
|
||||||
|
* # # # # Reserved by _Min_Stack_Size #
|
||||||
|
* ############################################################################
|
||||||
|
* ^-- RAM start ^-- _end _estack, RAM end --^
|
||||||
|
* @endverbatim
|
||||||
|
*
|
||||||
|
* This implementation starts allocating at the '_end' linker symbol
|
||||||
|
* The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack
|
||||||
|
* The implementation considers '_estack' linker symbol to be RAM end
|
||||||
|
* NOTE: If the MSP stack, at any point during execution, grows larger than the
|
||||||
|
* reserved size, please increase the '_Min_Stack_Size'.
|
||||||
|
*
|
||||||
|
* @param incr Memory size
|
||||||
|
* @return Pointer to allocated memory
|
||||||
|
*/
|
||||||
|
void *_sbrk(ptrdiff_t incr)
|
||||||
|
{
|
||||||
|
extern uint8_t _end; /* Symbol defined in the linker script */
|
||||||
|
extern uint8_t _estack; /* Symbol defined in the linker script */
|
||||||
|
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
|
||||||
|
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
|
||||||
|
const uint8_t *max_heap = (uint8_t *)stack_limit;
|
||||||
|
uint8_t *prev_heap_end;
|
||||||
|
|
||||||
|
/* Initalize heap end at first call */
|
||||||
|
if (NULL == __sbrk_heap_end)
|
||||||
|
{
|
||||||
|
__sbrk_heap_end = &_end;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Protect heap from growing into the reserved MSP stack */
|
||||||
|
if (__sbrk_heap_end + incr > max_heap)
|
||||||
|
{
|
||||||
|
errno = ENOMEM;
|
||||||
|
return (void *)-1;
|
||||||
|
}
|
||||||
|
|
||||||
|
prev_heap_end = __sbrk_heap_end;
|
||||||
|
__sbrk_heap_end += incr;
|
||||||
|
|
||||||
|
return (void *)prev_heap_end;
|
||||||
|
}
|
||||||
304
Boot/Core/Src/system_stm32g0xx.c
Normal file
304
Boot/Core/Src/system_stm32g0xx.c
Normal file
@@ -0,0 +1,304 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file system_stm32g0xx.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File
|
||||||
|
*
|
||||||
|
* This file provides two functions and one global variable to be called from
|
||||||
|
* user application:
|
||||||
|
* - SystemInit(): This function is called at startup just after reset and
|
||||||
|
* before branch to main program. This call is made inside
|
||||||
|
* the "startup_stm32g0xx.s" file.
|
||||||
|
*
|
||||||
|
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
|
||||||
|
* by the user application to setup the SysTick
|
||||||
|
* timer or configure other parameters.
|
||||||
|
*
|
||||||
|
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
||||||
|
* be called whenever the core clock is changed
|
||||||
|
* during program execution.
|
||||||
|
*
|
||||||
|
* After each device reset the HSI (8 MHz then 16 MHz) is used as system clock source.
|
||||||
|
* Then SystemInit() function is called, in "startup_stm32g0xx.s" file, to
|
||||||
|
* configure the system clock before to branch to main program.
|
||||||
|
*
|
||||||
|
* This file configures the system clock as follows:
|
||||||
|
*=============================================================================
|
||||||
|
*-----------------------------------------------------------------------------
|
||||||
|
* System Clock source | HSI
|
||||||
|
*-----------------------------------------------------------------------------
|
||||||
|
* SYSCLK(Hz) | 16000000
|
||||||
|
*-----------------------------------------------------------------------------
|
||||||
|
* HCLK(Hz) | 16000000
|
||||||
|
*-----------------------------------------------------------------------------
|
||||||
|
* AHB Prescaler | 1
|
||||||
|
*-----------------------------------------------------------------------------
|
||||||
|
* APB Prescaler | 1
|
||||||
|
*-----------------------------------------------------------------------------
|
||||||
|
* HSI Division factor | 1
|
||||||
|
*-----------------------------------------------------------------------------
|
||||||
|
* PLL_M | 1
|
||||||
|
*-----------------------------------------------------------------------------
|
||||||
|
* PLL_N | 8
|
||||||
|
*-----------------------------------------------------------------------------
|
||||||
|
* PLL_P | 7
|
||||||
|
*-----------------------------------------------------------------------------
|
||||||
|
* PLL_Q | 2
|
||||||
|
*-----------------------------------------------------------------------------
|
||||||
|
* PLL_R | 2
|
||||||
|
*-----------------------------------------------------------------------------
|
||||||
|
* Require 48MHz for RNG | Disabled
|
||||||
|
*-----------------------------------------------------------------------------
|
||||||
|
*=============================================================================
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* Copyright (c) 2018-2021 STMicroelectronics.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* This software is licensed under terms that can be found in the LICENSE file
|
||||||
|
* in the root directory of this software component.
|
||||||
|
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
/** @addtogroup CMSIS
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup stm32g0xx_system
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup STM32G0xx_System_Private_Includes
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "stm32g0xx.h"
|
||||||
|
|
||||||
|
#if !defined (HSE_VALUE)
|
||||||
|
#define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */
|
||||||
|
#endif /* HSE_VALUE */
|
||||||
|
|
||||||
|
#if !defined (HSI_VALUE)
|
||||||
|
#define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/
|
||||||
|
#endif /* HSI_VALUE */
|
||||||
|
|
||||||
|
#if !defined (LSI_VALUE)
|
||||||
|
#define LSI_VALUE (32000UL) /*!< Value of LSI in Hz*/
|
||||||
|
#endif /* LSI_VALUE */
|
||||||
|
|
||||||
|
#if !defined (LSE_VALUE)
|
||||||
|
#define LSE_VALUE (32768UL) /*!< Value of LSE in Hz*/
|
||||||
|
#endif /* LSE_VALUE */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup STM32G0xx_System_Private_TypesDefinitions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup STM32G0xx_System_Private_Defines
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/************************* Miscellaneous Configuration ************************/
|
||||||
|
/* Note: Following vector table addresses must be defined in line with linker
|
||||||
|
configuration. */
|
||||||
|
/*!< Uncomment the following line if you need to relocate the vector table
|
||||||
|
anywhere in Flash or Sram, else the vector table is kept at the automatic
|
||||||
|
remap of boot address selected */
|
||||||
|
/* #define USER_VECT_TAB_ADDRESS */
|
||||||
|
|
||||||
|
#if defined(USER_VECT_TAB_ADDRESS)
|
||||||
|
/*!< Uncomment the following line if you need to relocate your vector Table
|
||||||
|
in Sram else user remap will be done in Flash. */
|
||||||
|
/* #define VECT_TAB_SRAM */
|
||||||
|
#if defined(VECT_TAB_SRAM)
|
||||||
|
#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
|
||||||
|
This value must be a multiple of 0x200. */
|
||||||
|
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||||
|
This value must be a multiple of 0x200. */
|
||||||
|
#else
|
||||||
|
#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
|
||||||
|
This value must be a multiple of 0x200. */
|
||||||
|
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||||
|
This value must be a multiple of 0x200. */
|
||||||
|
#endif /* VECT_TAB_SRAM */
|
||||||
|
#endif /* USER_VECT_TAB_ADDRESS */
|
||||||
|
/******************************************************************************/
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup STM32G0xx_System_Private_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup STM32G0xx_System_Private_Variables
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* The SystemCoreClock variable is updated in three ways:
|
||||||
|
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||||
|
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
|
||||||
|
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||||
|
Note: If you use this function to configure the system clock; then there
|
||||||
|
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||||
|
variable is updated automatically.
|
||||||
|
*/
|
||||||
|
uint32_t SystemCoreClock = 16000000UL;
|
||||||
|
|
||||||
|
const uint32_t AHBPrescTable[16UL] = {0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL, 6UL, 7UL, 8UL, 9UL};
|
||||||
|
const uint32_t APBPrescTable[8UL] = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup STM32G0xx_System_Private_FunctionPrototypes
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup STM32G0xx_System_Private_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Setup the microcontroller system.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SystemInit(void)
|
||||||
|
{
|
||||||
|
/* Configure the Vector Table location -------------------------------------*/
|
||||||
|
#if defined(USER_VECT_TAB_ADDRESS)
|
||||||
|
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation */
|
||||||
|
#endif /* USER_VECT_TAB_ADDRESS */
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||||
|
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||||
|
* be used by the user application to setup the SysTick timer or configure
|
||||||
|
* other parameters.
|
||||||
|
*
|
||||||
|
* @note Each time the core clock (HCLK) changes, this function must be called
|
||||||
|
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||||||
|
* based on this variable will be incorrect.
|
||||||
|
*
|
||||||
|
* @note - The system frequency computed by this function is not the real
|
||||||
|
* frequency in the chip. It is calculated based on the predefined
|
||||||
|
* constant and the selected clock source:
|
||||||
|
*
|
||||||
|
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) / HSI division factor
|
||||||
|
*
|
||||||
|
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
|
||||||
|
*
|
||||||
|
* - If SYSCLK source is LSI, SystemCoreClock will contain the LSI_VALUE
|
||||||
|
*
|
||||||
|
* - If SYSCLK source is LSE, SystemCoreClock will contain the LSE_VALUE
|
||||||
|
*
|
||||||
|
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
|
||||||
|
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
|
||||||
|
*
|
||||||
|
* (**) HSI_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value
|
||||||
|
* 16 MHz) but the real value may vary depending on the variations
|
||||||
|
* in voltage and temperature.
|
||||||
|
*
|
||||||
|
* (***) HSE_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value
|
||||||
|
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
|
||||||
|
* frequency of the crystal used. Otherwise, this function may
|
||||||
|
* have wrong result.
|
||||||
|
*
|
||||||
|
* - The result of this function could be not correct when using fractional
|
||||||
|
* value for HSE crystal.
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
void SystemCoreClockUpdate(void)
|
||||||
|
{
|
||||||
|
uint32_t tmp;
|
||||||
|
uint32_t pllvco;
|
||||||
|
uint32_t pllr;
|
||||||
|
uint32_t pllsource;
|
||||||
|
uint32_t pllm;
|
||||||
|
uint32_t hsidiv;
|
||||||
|
|
||||||
|
/* Get SYSCLK source -------------------------------------------------------*/
|
||||||
|
switch (RCC->CFGR & RCC_CFGR_SWS)
|
||||||
|
{
|
||||||
|
case RCC_CFGR_SWS_0: /* HSE used as system clock */
|
||||||
|
SystemCoreClock = HSE_VALUE;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0): /* LSI used as system clock */
|
||||||
|
SystemCoreClock = LSI_VALUE;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case RCC_CFGR_SWS_2: /* LSE used as system clock */
|
||||||
|
SystemCoreClock = LSE_VALUE;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case RCC_CFGR_SWS_1: /* PLL used as system clock */
|
||||||
|
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
|
||||||
|
SYSCLK = PLL_VCO / PLLR
|
||||||
|
*/
|
||||||
|
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
|
||||||
|
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL;
|
||||||
|
|
||||||
|
if(pllsource == 0x03UL) /* HSE used as PLL clock source */
|
||||||
|
{
|
||||||
|
pllvco = (HSE_VALUE / pllm);
|
||||||
|
}
|
||||||
|
else /* HSI used as PLL clock source */
|
||||||
|
{
|
||||||
|
pllvco = (HSI_VALUE / pllm);
|
||||||
|
}
|
||||||
|
pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
|
||||||
|
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
|
||||||
|
|
||||||
|
SystemCoreClock = pllvco/pllr;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 0x00000000U: /* HSI used as system clock */
|
||||||
|
default: /* HSI used as system clock */
|
||||||
|
hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV))>> RCC_CR_HSIDIV_Pos));
|
||||||
|
SystemCoreClock = (HSI_VALUE/hsidiv);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
/* Compute HCLK clock frequency --------------------------------------------*/
|
||||||
|
/* Get HCLK prescaler */
|
||||||
|
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
|
||||||
|
/* HCLK clock frequency */
|
||||||
|
SystemCoreClock >>= tmp;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
126
Boot/Core/Src/tim.c
Normal file
126
Boot/Core/Src/tim.c
Normal file
@@ -0,0 +1,126 @@
|
|||||||
|
/* USER CODE BEGIN Header */
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file tim.c
|
||||||
|
* @brief This file provides code for the configuration
|
||||||
|
* of the TIM instances.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* Copyright (c) 2023 STMicroelectronics.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* This software is licensed under terms that can be found in the LICENSE file
|
||||||
|
* in the root directory of this software component.
|
||||||
|
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
/* USER CODE END Header */
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "tim.h"
|
||||||
|
|
||||||
|
/* USER CODE BEGIN 0 */
|
||||||
|
|
||||||
|
/* USER CODE END 0 */
|
||||||
|
|
||||||
|
TIM_HandleTypeDef htim3;
|
||||||
|
|
||||||
|
/* TIM3 init function */
|
||||||
|
void MX_TIM3_Init(void)
|
||||||
|
{
|
||||||
|
|
||||||
|
/* USER CODE BEGIN TIM3_Init 0 */
|
||||||
|
|
||||||
|
/* USER CODE END TIM3_Init 0 */
|
||||||
|
|
||||||
|
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
||||||
|
TIM_IC_InitTypeDef sConfigIC = {0};
|
||||||
|
|
||||||
|
/* USER CODE BEGIN TIM3_Init 1 */
|
||||||
|
|
||||||
|
/* USER CODE END TIM3_Init 1 */
|
||||||
|
htim3.Instance = TIM3;
|
||||||
|
htim3.Init.Prescaler = 0;
|
||||||
|
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
|
||||||
|
htim3.Init.Period = 65535;
|
||||||
|
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
||||||
|
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
||||||
|
if (HAL_TIM_IC_Init(&htim3) != HAL_OK)
|
||||||
|
{
|
||||||
|
Error_Handler();
|
||||||
|
}
|
||||||
|
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
||||||
|
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
||||||
|
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
|
||||||
|
{
|
||||||
|
Error_Handler();
|
||||||
|
}
|
||||||
|
sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_RISING;
|
||||||
|
sConfigIC.ICSelection = TIM_ICSELECTION_DIRECTTI;
|
||||||
|
sConfigIC.ICPrescaler = TIM_ICPSC_DIV1;
|
||||||
|
sConfigIC.ICFilter = 0;
|
||||||
|
if (HAL_TIM_IC_ConfigChannel(&htim3, &sConfigIC, TIM_CHANNEL_1) != HAL_OK)
|
||||||
|
{
|
||||||
|
Error_Handler();
|
||||||
|
}
|
||||||
|
/* USER CODE BEGIN TIM3_Init 2 */
|
||||||
|
|
||||||
|
/* USER CODE END TIM3_Init 2 */
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
void HAL_TIM_IC_MspInit(TIM_HandleTypeDef* tim_icHandle)
|
||||||
|
{
|
||||||
|
|
||||||
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
||||||
|
if(tim_icHandle->Instance==TIM3)
|
||||||
|
{
|
||||||
|
/* USER CODE BEGIN TIM3_MspInit 0 */
|
||||||
|
|
||||||
|
/* USER CODE END TIM3_MspInit 0 */
|
||||||
|
/* TIM3 clock enable */
|
||||||
|
__HAL_RCC_TIM3_CLK_ENABLE();
|
||||||
|
|
||||||
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||||
|
/**TIM3 GPIO Configuration
|
||||||
|
PB4 ------> TIM3_CH1
|
||||||
|
*/
|
||||||
|
GPIO_InitStruct.Pin = GPIO_PIN_4;
|
||||||
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||||
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||||
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||||||
|
GPIO_InitStruct.Alternate = GPIO_AF1_TIM3;
|
||||||
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
||||||
|
|
||||||
|
/* USER CODE BEGIN TIM3_MspInit 1 */
|
||||||
|
|
||||||
|
/* USER CODE END TIM3_MspInit 1 */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef* tim_icHandle)
|
||||||
|
{
|
||||||
|
|
||||||
|
if(tim_icHandle->Instance==TIM3)
|
||||||
|
{
|
||||||
|
/* USER CODE BEGIN TIM3_MspDeInit 0 */
|
||||||
|
|
||||||
|
/* USER CODE END TIM3_MspDeInit 0 */
|
||||||
|
/* Peripheral clock disable */
|
||||||
|
__HAL_RCC_TIM3_CLK_DISABLE();
|
||||||
|
|
||||||
|
/**TIM3 GPIO Configuration
|
||||||
|
PB4 ------> TIM3_CH1
|
||||||
|
*/
|
||||||
|
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_4);
|
||||||
|
|
||||||
|
/* USER CODE BEGIN TIM3_MspDeInit 1 */
|
||||||
|
|
||||||
|
/* USER CODE END TIM3_MspDeInit 1 */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* USER CODE BEGIN 1 */
|
||||||
|
|
||||||
|
/* USER CODE END 1 */
|
||||||
197
Boot/Core/Src/usart.c
Normal file
197
Boot/Core/Src/usart.c
Normal file
@@ -0,0 +1,197 @@
|
|||||||
|
/* USER CODE BEGIN Header */
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file usart.c
|
||||||
|
* @brief This file provides code for the configuration
|
||||||
|
* of the USART instances.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* Copyright (c) 2023 STMicroelectronics.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* This software is licensed under terms that can be found in the LICENSE file
|
||||||
|
* in the root directory of this software component.
|
||||||
|
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
/* USER CODE END Header */
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "usart.h"
|
||||||
|
|
||||||
|
/* USER CODE BEGIN 0 */
|
||||||
|
|
||||||
|
/* USER CODE END 0 */
|
||||||
|
|
||||||
|
/* USART1 init function */
|
||||||
|
|
||||||
|
void MX_USART1_UART_Init(void)
|
||||||
|
{
|
||||||
|
|
||||||
|
/* USER CODE BEGIN USART1_Init 0 */
|
||||||
|
|
||||||
|
/* USER CODE END USART1_Init 0 */
|
||||||
|
|
||||||
|
LL_USART_InitTypeDef USART_InitStruct = {0};
|
||||||
|
|
||||||
|
LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
|
||||||
|
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
|
||||||
|
|
||||||
|
/** Initializes the peripherals clocks
|
||||||
|
*/
|
||||||
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;
|
||||||
|
PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK1;
|
||||||
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
||||||
|
{
|
||||||
|
Error_Handler();
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Peripheral clock enable */
|
||||||
|
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1);
|
||||||
|
|
||||||
|
LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOB);
|
||||||
|
/**USART1 GPIO Configuration
|
||||||
|
PB6 ------> USART1_TX
|
||||||
|
PB7 ------> USART1_RX
|
||||||
|
*/
|
||||||
|
GPIO_InitStruct.Pin = LL_GPIO_PIN_6;
|
||||||
|
GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
|
||||||
|
GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
|
||||||
|
GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
|
||||||
|
GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
|
||||||
|
GPIO_InitStruct.Alternate = LL_GPIO_AF_0;
|
||||||
|
LL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
||||||
|
|
||||||
|
GPIO_InitStruct.Pin = LL_GPIO_PIN_7;
|
||||||
|
GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
|
||||||
|
GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
|
||||||
|
GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
|
||||||
|
GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
|
||||||
|
GPIO_InitStruct.Alternate = LL_GPIO_AF_0;
|
||||||
|
LL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
||||||
|
|
||||||
|
/* USART1 interrupt Init */
|
||||||
|
NVIC_SetPriority(USART1_IRQn, 0);
|
||||||
|
NVIC_EnableIRQ(USART1_IRQn);
|
||||||
|
|
||||||
|
/* USER CODE BEGIN USART1_Init 1 */
|
||||||
|
|
||||||
|
/* USER CODE END USART1_Init 1 */
|
||||||
|
USART_InitStruct.PrescalerValue = LL_USART_PRESCALER_DIV1;
|
||||||
|
USART_InitStruct.BaudRate = 9600;
|
||||||
|
USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B;
|
||||||
|
USART_InitStruct.StopBits = LL_USART_STOPBITS_1;
|
||||||
|
USART_InitStruct.Parity = LL_USART_PARITY_NONE;
|
||||||
|
USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX;
|
||||||
|
USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE;
|
||||||
|
USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16;
|
||||||
|
LL_USART_Init(USART1, &USART_InitStruct);
|
||||||
|
LL_USART_SetTXFIFOThreshold(USART1, LL_USART_FIFOTHRESHOLD_1_8);
|
||||||
|
LL_USART_SetRXFIFOThreshold(USART1, LL_USART_FIFOTHRESHOLD_1_8);
|
||||||
|
LL_USART_DisableFIFO(USART1);
|
||||||
|
LL_USART_SetTXRXSwap(USART1, LL_USART_TXRX_SWAPPED);
|
||||||
|
LL_USART_ConfigAsyncMode(USART1);
|
||||||
|
|
||||||
|
/* USER CODE BEGIN WKUPType USART1 */
|
||||||
|
|
||||||
|
/* USER CODE END WKUPType USART1 */
|
||||||
|
|
||||||
|
LL_USART_Enable(USART1);
|
||||||
|
|
||||||
|
/* Polling USART1 initialisation */
|
||||||
|
while((!(LL_USART_IsActiveFlag_TEACK(USART1))) || (!(LL_USART_IsActiveFlag_REACK(USART1))))
|
||||||
|
{
|
||||||
|
}
|
||||||
|
/* USER CODE BEGIN USART1_Init 2 */
|
||||||
|
|
||||||
|
/* USER CODE END USART1_Init 2 */
|
||||||
|
|
||||||
|
}
|
||||||
|
/* USART2 init function */
|
||||||
|
|
||||||
|
void MX_USART2_UART_Init(void)
|
||||||
|
{
|
||||||
|
|
||||||
|
/* USER CODE BEGIN USART2_Init 0 */
|
||||||
|
|
||||||
|
/* USER CODE END USART2_Init 0 */
|
||||||
|
|
||||||
|
LL_USART_InitTypeDef USART_InitStruct = {0};
|
||||||
|
|
||||||
|
LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
|
||||||
|
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
|
||||||
|
|
||||||
|
/** Initializes the peripherals clocks
|
||||||
|
*/
|
||||||
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2;
|
||||||
|
PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
|
||||||
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
||||||
|
{
|
||||||
|
Error_Handler();
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Peripheral clock enable */
|
||||||
|
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USART2);
|
||||||
|
|
||||||
|
LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA);
|
||||||
|
/**USART2 GPIO Configuration
|
||||||
|
PA2 ------> USART2_TX
|
||||||
|
PA3 ------> USART2_RX
|
||||||
|
*/
|
||||||
|
GPIO_InitStruct.Pin = LL_GPIO_PIN_2;
|
||||||
|
GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
|
||||||
|
GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
|
||||||
|
GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
|
||||||
|
GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
|
||||||
|
GPIO_InitStruct.Alternate = LL_GPIO_AF_1;
|
||||||
|
LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||||
|
|
||||||
|
GPIO_InitStruct.Pin = LL_GPIO_PIN_3;
|
||||||
|
GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
|
||||||
|
GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
|
||||||
|
GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
|
||||||
|
GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
|
||||||
|
GPIO_InitStruct.Alternate = LL_GPIO_AF_1;
|
||||||
|
LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||||
|
|
||||||
|
/* USART2 interrupt Init */
|
||||||
|
NVIC_SetPriority(USART2_IRQn, 0);
|
||||||
|
NVIC_EnableIRQ(USART2_IRQn);
|
||||||
|
|
||||||
|
/* USER CODE BEGIN USART2_Init 1 */
|
||||||
|
|
||||||
|
/* USER CODE END USART2_Init 1 */
|
||||||
|
USART_InitStruct.PrescalerValue = LL_USART_PRESCALER_DIV1;
|
||||||
|
USART_InitStruct.BaudRate = 9600;
|
||||||
|
USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B;
|
||||||
|
USART_InitStruct.StopBits = LL_USART_STOPBITS_1;
|
||||||
|
USART_InitStruct.Parity = LL_USART_PARITY_NONE;
|
||||||
|
USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX;
|
||||||
|
USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE;
|
||||||
|
USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16;
|
||||||
|
LL_USART_Init(USART2, &USART_InitStruct);
|
||||||
|
LL_USART_SetTXFIFOThreshold(USART2, LL_USART_FIFOTHRESHOLD_1_8);
|
||||||
|
LL_USART_SetRXFIFOThreshold(USART2, LL_USART_FIFOTHRESHOLD_1_8);
|
||||||
|
LL_USART_DisableFIFO(USART2);
|
||||||
|
LL_USART_ConfigAsyncMode(USART2);
|
||||||
|
|
||||||
|
/* USER CODE BEGIN WKUPType USART2 */
|
||||||
|
|
||||||
|
/* USER CODE END WKUPType USART2 */
|
||||||
|
|
||||||
|
LL_USART_Enable(USART2);
|
||||||
|
|
||||||
|
/* Polling USART2 initialisation */
|
||||||
|
while((!(LL_USART_IsActiveFlag_TEACK(USART2))) || (!(LL_USART_IsActiveFlag_REACK(USART2))))
|
||||||
|
{
|
||||||
|
}
|
||||||
|
/* USER CODE BEGIN USART2_Init 2 */
|
||||||
|
|
||||||
|
/* USER CODE END USART2_Init 2 */
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/* USER CODE BEGIN 1 */
|
||||||
|
|
||||||
|
/* USER CODE END 1 */
|
||||||
288
Boot/Core/Startup/startup_stm32g071rbtx.s
Normal file
288
Boot/Core/Startup/startup_stm32g071rbtx.s
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file startup_stm32g071xx.s
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @brief STM32G071xx devices vector table for SW4STM32 toolchain.
|
||||||
|
* This module performs:
|
||||||
|
* - Set the initial SP
|
||||||
|
* - Set the initial PC == Reset_Handler,
|
||||||
|
* - Set the vector table entries with the exceptions ISR address
|
||||||
|
* - Branches to main in the C library (which eventually
|
||||||
|
* calls main()).
|
||||||
|
* After Reset the Cortex-M0+ processor is in Thread mode,
|
||||||
|
* priority is Privileged, and the Stack is set to Main.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* Copyright (c) 2018 STMicroelectronics. All rights reserved.
|
||||||
|
*
|
||||||
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
|
* the "License"; You may not use this file except in compliance with the
|
||||||
|
* License. You may obtain a copy of the License at:
|
||||||
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
.syntax unified
|
||||||
|
.cpu cortex-m0
|
||||||
|
.fpu softvfp
|
||||||
|
.thumb
|
||||||
|
|
||||||
|
.global g_pfnVectors
|
||||||
|
.global Default_Handler
|
||||||
|
|
||||||
|
/* start address for the initialization values of the .data section.
|
||||||
|
defined in linker script */
|
||||||
|
.word _sidata
|
||||||
|
/* start address for the .data section. defined in linker script */
|
||||||
|
.word _sdata
|
||||||
|
/* end address for the .data section. defined in linker script */
|
||||||
|
.word _edata
|
||||||
|
/* start address for the .bss section. defined in linker script */
|
||||||
|
.word _sbss
|
||||||
|
/* end address for the .bss section. defined in linker script */
|
||||||
|
.word _ebss
|
||||||
|
|
||||||
|
.section .text.Reset_Handler
|
||||||
|
.weak Reset_Handler
|
||||||
|
.type Reset_Handler, %function
|
||||||
|
Reset_Handler:
|
||||||
|
ldr r0, =_estack
|
||||||
|
mov sp, r0 /* set stack pointer */
|
||||||
|
|
||||||
|
/* Copy the data segment initializers from flash to SRAM */
|
||||||
|
movs r1, #0
|
||||||
|
b LoopCopyDataInit
|
||||||
|
|
||||||
|
CopyDataInit:
|
||||||
|
ldr r3, =_sidata
|
||||||
|
ldr r3, [r3, r1]
|
||||||
|
str r3, [r0, r1]
|
||||||
|
adds r1, r1, #4
|
||||||
|
|
||||||
|
LoopCopyDataInit:
|
||||||
|
ldr r0, =_sdata
|
||||||
|
ldr r3, =_edata
|
||||||
|
adds r2, r0, r1
|
||||||
|
cmp r2, r3
|
||||||
|
bcc CopyDataInit
|
||||||
|
ldr r2, =_sbss
|
||||||
|
b LoopFillZerobss
|
||||||
|
/* Zero fill the bss segment. */
|
||||||
|
FillZerobss:
|
||||||
|
movs r3, #0
|
||||||
|
str r3, [r2]
|
||||||
|
adds r2, r2, #4
|
||||||
|
|
||||||
|
|
||||||
|
LoopFillZerobss:
|
||||||
|
ldr r3, = _ebss
|
||||||
|
cmp r2, r3
|
||||||
|
bcc FillZerobss
|
||||||
|
|
||||||
|
/* Call the clock system intitialization function.*/
|
||||||
|
bl SystemInit
|
||||||
|
/* Call static constructors */
|
||||||
|
bl __libc_init_array
|
||||||
|
/* Call the application's entry point.*/
|
||||||
|
bl main
|
||||||
|
|
||||||
|
LoopForever:
|
||||||
|
b LoopForever
|
||||||
|
|
||||||
|
|
||||||
|
.size Reset_Handler, .-Reset_Handler
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor receives an
|
||||||
|
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||||
|
* the system state for examination by a debugger.
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
.section .text.Default_Handler,"ax",%progbits
|
||||||
|
Default_Handler:
|
||||||
|
Infinite_Loop:
|
||||||
|
b Infinite_Loop
|
||||||
|
.size Default_Handler, .-Default_Handler
|
||||||
|
/******************************************************************************
|
||||||
|
*
|
||||||
|
* The minimal vector table for a Cortex M0. Note that the proper constructs
|
||||||
|
* must be placed on this to ensure that it ends up at physical address
|
||||||
|
* 0x0000.0000.
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
.section .isr_vector,"a",%progbits
|
||||||
|
.type g_pfnVectors, %object
|
||||||
|
.size g_pfnVectors, .-g_pfnVectors
|
||||||
|
|
||||||
|
|
||||||
|
g_pfnVectors:
|
||||||
|
.word _estack
|
||||||
|
.word Reset_Handler
|
||||||
|
.word NMI_Handler
|
||||||
|
.word HardFault_Handler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word SVC_Handler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word PendSV_Handler
|
||||||
|
.word SysTick_Handler
|
||||||
|
.word WWDG_IRQHandler /* Window WatchDog */
|
||||||
|
.word PVD_IRQHandler /* PVD through EXTI Line detect */
|
||||||
|
.word RTC_TAMP_IRQHandler /* RTC through the EXTI line */
|
||||||
|
.word FLASH_IRQHandler /* FLASH */
|
||||||
|
.word RCC_IRQHandler /* RCC */
|
||||||
|
.word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */
|
||||||
|
.word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */
|
||||||
|
.word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */
|
||||||
|
.word UCPD1_2_IRQHandler /* UCPD1, UCPD2 */
|
||||||
|
.word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
|
||||||
|
.word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */
|
||||||
|
.word DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler /* DMA1 Channel 4 to Channel 7, DMAMUX1 overrun */
|
||||||
|
.word ADC1_COMP_IRQHandler /* ADC1, COMP1 and COMP2 */
|
||||||
|
.word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */
|
||||||
|
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||||
|
.word TIM2_IRQHandler /* TIM2 */
|
||||||
|
.word TIM3_IRQHandler /* TIM3 */
|
||||||
|
.word TIM6_DAC_LPTIM1_IRQHandler /* TIM6, DAC and LPTIM1 */
|
||||||
|
.word TIM7_LPTIM2_IRQHandler /* TIM7 and LPTIM2 */
|
||||||
|
.word TIM14_IRQHandler /* TIM14 */
|
||||||
|
.word TIM15_IRQHandler /* TIM15 */
|
||||||
|
.word TIM16_IRQHandler /* TIM16 */
|
||||||
|
.word TIM17_IRQHandler /* TIM17 */
|
||||||
|
.word I2C1_IRQHandler /* I2C1 */
|
||||||
|
.word I2C2_IRQHandler /* I2C2 */
|
||||||
|
.word SPI1_IRQHandler /* SPI1 */
|
||||||
|
.word SPI2_IRQHandler /* SPI2 */
|
||||||
|
.word USART1_IRQHandler /* USART1 */
|
||||||
|
.word USART2_IRQHandler /* USART2 */
|
||||||
|
.word USART3_4_LPUART1_IRQHandler /* USART3, USART4 and LPUART1 */
|
||||||
|
.word CEC_IRQHandler /* CEC */
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
*
|
||||||
|
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||||
|
* As they are weak aliases, any function with the same name will override
|
||||||
|
* this definition.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
.weak NMI_Handler
|
||||||
|
.thumb_set NMI_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak HardFault_Handler
|
||||||
|
.thumb_set HardFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SVC_Handler
|
||||||
|
.thumb_set SVC_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak PendSV_Handler
|
||||||
|
.thumb_set PendSV_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SysTick_Handler
|
||||||
|
.thumb_set SysTick_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak WWDG_IRQHandler
|
||||||
|
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak PVD_IRQHandler
|
||||||
|
.thumb_set PVD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_TAMP_IRQHandler
|
||||||
|
.thumb_set RTC_TAMP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FLASH_IRQHandler
|
||||||
|
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RCC_IRQHandler
|
||||||
|
.thumb_set RCC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI0_1_IRQHandler
|
||||||
|
.thumb_set EXTI0_1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI2_3_IRQHandler
|
||||||
|
.thumb_set EXTI2_3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI4_15_IRQHandler
|
||||||
|
.thumb_set EXTI4_15_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UCPD1_2_IRQHandler
|
||||||
|
.thumb_set UCPD1_2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel2_3_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler
|
||||||
|
.thumb_set DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC1_COMP_IRQHandler
|
||||||
|
.thumb_set ADC1_COMP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_BRK_UP_TRG_COM_IRQHandler
|
||||||
|
.thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_CC_IRQHandler
|
||||||
|
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM2_IRQHandler
|
||||||
|
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM3_IRQHandler
|
||||||
|
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM6_DAC_LPTIM1_IRQHandler
|
||||||
|
.thumb_set TIM6_DAC_LPTIM1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM7_LPTIM2_IRQHandler
|
||||||
|
.thumb_set TIM7_LPTIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM14_IRQHandler
|
||||||
|
.thumb_set TIM14_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM15_IRQHandler
|
||||||
|
.thumb_set TIM15_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM16_IRQHandler
|
||||||
|
.thumb_set TIM16_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM17_IRQHandler
|
||||||
|
.thumb_set TIM17_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_IRQHandler
|
||||||
|
.thumb_set I2C1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_IRQHandler
|
||||||
|
.thumb_set I2C2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI1_IRQHandler
|
||||||
|
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI2_IRQHandler
|
||||||
|
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART1_IRQHandler
|
||||||
|
.thumb_set USART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART2_IRQHandler
|
||||||
|
.thumb_set USART2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART3_4_LPUART1_IRQHandler
|
||||||
|
.thumb_set USART3_4_LPUART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CEC_IRQHandler
|
||||||
|
.thumb_set CEC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
||||||
521
Boot/Debug/openblt_stm32g071.srec
Normal file
521
Boot/Debug/openblt_stm32g071.srec
Normal file
@@ -0,0 +1,521 @@
|
|||||||
|
S01900006F70656E626C745F73746D3332673037312E7372656300
|
||||||
|
S31508000000009000209D050008890500088B0500085A
|
||||||
|
S3150800001000000000000000000000000000000000D2
|
||||||
|
S315080000200000000000000000000000008D05000828
|
||||||
|
S3150800003000000000000000008F0500089105000878
|
||||||
|
S31508000040ED050008ED050008ED050008ED050008BA
|
||||||
|
S31508000050ED050008ED050008ED050008ED050008AA
|
||||||
|
S31508000060ED050008ED050008ED050008ED0500089A
|
||||||
|
S31508000070ED050008ED050008ED050008ED0500088A
|
||||||
|
S31508000080ED050008ED050008ED050008ED0500087A
|
||||||
|
S31508000090ED050008ED050008ED050008ED0500086A
|
||||||
|
S315080000A0ED050008ED050008ED050008ED0500085A
|
||||||
|
S311080000B0ED050008ED050008ED05000848
|
||||||
|
S315080000BC10B5064C2378002B07D1054B002B02D024
|
||||||
|
S315080000CC044800E000BF0123237010BD1000002077
|
||||||
|
S315080000DC000000002C1D0008044B10B5002B03D0A3
|
||||||
|
S315080000EC0349044800E000BF10BDC04600000000EC
|
||||||
|
S315080000FC140000202C1D0008002243088B4274D3E0
|
||||||
|
S3150800010C03098B425FD3030A8B4244D3030B8B42FE
|
||||||
|
S3150800011C28D3030C8B420DD3FF22090212BA030C07
|
||||||
|
S3150800012C8B4202D31212090265D0030B8B4219D3E8
|
||||||
|
S3150800013C00E0090AC30B8B4201D3CB03C01A524108
|
||||||
|
S3150800014C830B8B4201D38B03C01A5241430B8B4250
|
||||||
|
S3150800015C01D34B03C01A5241030B8B4201D30B0339
|
||||||
|
S3150800016CC01A5241C30A8B4201D3CB02C01A524160
|
||||||
|
S3150800017C830A8B4201D38B02C01A5241430A8B4223
|
||||||
|
S3150800018C01D34B02C01A5241030A8B4201D30B020C
|
||||||
|
S3150800019CC01A5241CDD2C3098B4201D3CB01C01A26
|
||||||
|
S315080001AC524183098B4201D38B01C01A5241430930
|
||||||
|
S315080001BC8B4201D34B01C01A524103098B4201D31E
|
||||||
|
S315080001CC0B01C01A5241C3088B4201D3CB00C01A8B
|
||||||
|
S315080001DC524183088B4201D38B00C01A5241430803
|
||||||
|
S315080001EC8B4201D34B00C01A5241411A00D2014628
|
||||||
|
S315080001FC524110467047FFE701B5002000F006F89B
|
||||||
|
S3150800020C02BDC0460029F7D076E770477047C0464E
|
||||||
|
S3150800021C10B501F0EDFA10BD10B501F0F7FA10BDE6
|
||||||
|
S3150800022C10B5054B1B699B0401D4002010BD00F0CA
|
||||||
|
S3150800023C3DF80120FAE7C0460008005010B56420C6
|
||||||
|
S3150800024C00F006F810BD10B500F008F810BD000057
|
||||||
|
S3150800025C014B18807047C0462C00002010B501F0E1
|
||||||
|
S3150800026C79FA0F4B1B68984211D30E4B1B78002B4F
|
||||||
|
S3150800027C0ED10C4B01221A70A023DB051F329A6192
|
||||||
|
S3150800028C01F068FA084B1B881B18054A136010BD49
|
||||||
|
S3150800029C044B00221A70A023DB0520329A62EFE782
|
||||||
|
S315080002AC300000202E0000202C000020A023DB05A7
|
||||||
|
S315080002BC20229A627047000070B588B0142200217B
|
||||||
|
S315080002CC03A801F025FD164B596B042211435963FB
|
||||||
|
S315080002DC596B0A400192019A5A6B01252A435A63B3
|
||||||
|
S315080002EC5B6B2B400293029BA026F605002220216D
|
||||||
|
S315080002FC300000F0E7FB80239B0103930024049451
|
||||||
|
S3150800030C059403A9074800F021FB202303930495C1
|
||||||
|
S3150800031C0594069403A9300000F018FB08B070BDCC
|
||||||
|
S3150800032C0010024000080050F0B591B020220021C0
|
||||||
|
S3150800033C08A801F0EDFC344BD96B802080020143F0
|
||||||
|
S3150800034CD963DA6B02400192019A5A6B01252A434A
|
||||||
|
S3150800035C5A635B6B2B400093009B04230293022782
|
||||||
|
S3150800036C039700240494059406940795A026F6058D
|
||||||
|
S3150800037C02A9300000F054FC082302930397049456
|
||||||
|
S3150800038C05940694079502A9300000F049FC0894D8
|
||||||
|
S3150800039CE1235B0209930A940B940C940C230D939A
|
||||||
|
S315080003AC0E940F94194C08A9200000F06DFDEFF37C
|
||||||
|
S315080003BC108285F31088A368DB00DB08A36082F340
|
||||||
|
S315080003CC1088EFF3108285F31088A36810490B4048
|
||||||
|
S315080003DCA36082F3108823680E4A1340236063686F
|
||||||
|
S315080003EC0D4A13406360A3682A229343A3602368CB
|
||||||
|
S315080003FC1D432560054BDB699B02FBD5034BDB696B
|
||||||
|
S3150800040C5B02F7D511B0F0BD001002400044004065
|
||||||
|
S3150800041CFFFFFFF1FFFFFFDFFFB7FFFF10B5264A0F
|
||||||
|
S3150800042C136807218B4305390B431360224B1A6853
|
||||||
|
S3150800043C07231340022BF9D1204A1168FE330B43CC
|
||||||
|
S3150800044C13601E4B1B685B05FBD51C4BDA681C49F5
|
||||||
|
S3150800045C11401C4A0A43DA601968802252040A437E
|
||||||
|
S3150800046C1A60D968802252050A43DA60134B1B6856
|
||||||
|
S3150800047C9B01FBD5114A936813490B40936093680B
|
||||||
|
S3150800048C07218B4305390B4393600C4B9A68382329
|
||||||
|
S3150800049C1340102BF9D1094CA3680C4A1340A360DE
|
||||||
|
S315080004AC0B4800F087FD002000F0B0F8636D0C22B5
|
||||||
|
S315080004BC9343636510BDC0460020024000100240FD
|
||||||
|
S315080004CC8C80FF1F32400060FFF0FFFFFF8FFFFF9D
|
||||||
|
S315080004DC0090D00310B500F0C5F8FFF79FFFFFF7A3
|
||||||
|
S315080004ECEBFEFFF721FFFFF793FEFFF795FEFCE700
|
||||||
|
S315080004FC00B583B00B4B196C012211431964196CA6
|
||||||
|
S3150800050C0A400092009ADA6B802149050A43DA639D
|
||||||
|
S3150800051CDB6B0B400193019BC020C00000F0C2F8B6
|
||||||
|
S3150800052C03B000BD0010024010B500F0D1FAA024AB
|
||||||
|
S3150800053CE4052023A3620D4800F024FB200000F0FC
|
||||||
|
S3150800054C21FB0B4BDA6B0B490A40DA635A6B042115
|
||||||
|
S3150800055C8A435A635A6B03398A435A63DA6B0648D9
|
||||||
|
S3150800056C0240DA631A6C8A431A6410BD00080050FC
|
||||||
|
S3150800057C00100240FFFFFDFFFFFFFFEF7047FEE78D
|
||||||
|
S3150800058C7047704710B500F081F810BD7047000031
|
||||||
|
S3150800059C0D488546002103E00C4B5B58435004314B
|
||||||
|
S315080005AC0B480C4B42189A42F6D30B4A02E000232E
|
||||||
|
S315080005BC13600432094B9A42F9D3FFF7E7FF01F0AF
|
||||||
|
S315080005CC83FBFFF787FFFEE7009000203420000826
|
||||||
|
S315080005DC000000201000002010000020400500201C
|
||||||
|
S315080005ECFEE7000010B5084B01214942D9620022EA
|
||||||
|
S315080005FCDA6219631A6399629A6259625A62FFF748
|
||||||
|
S3150800060C93FF002010BDC0460010024010B5040030
|
||||||
|
S3150800061C114B1978002901D1012010BDFA20800050
|
||||||
|
S3150800062CFFF76AFD01000D4B1868FFF765FD00F032
|
||||||
|
S3150800063C75F800280DD1032C01D90120EDE70130FE
|
||||||
|
S3150800064C00222100404200F039F8054B1C600020BE
|
||||||
|
S3150800065CE3E70120E1E7C046040000200000002083
|
||||||
|
S3150800066C0800002010B5084A116880235B000B436C
|
||||||
|
S3150800067C13600020FFF7CAFF041E02D001242000D5
|
||||||
|
S3150800068C10BDFFF735FFFAE700200240034B1B7835
|
||||||
|
S3150800069C034A11685B1813607047C04604000020B3
|
||||||
|
S315080006AC3C050020034A136803490B4003431360B7
|
||||||
|
S315080006BC7047C04600000140FFF9FFFF70B50028DF
|
||||||
|
S315080006CC11DB8308134EC0339B009D59032420402D
|
||||||
|
S315080006DCC000FF2214008440A54389010A408240C9
|
||||||
|
S315080006EC2A439A5170BD0F230340083B9B080633D7
|
||||||
|
S315080006FC9B00094A944663445C6803221040C00078
|
||||||
|
S3150800070CFC3215008540AC4389010A4082402243DD
|
||||||
|
S3150800071C5A60E7E700E100E000ED00E001388023CD
|
||||||
|
S3150800072C5B0498420FD2094A50600948036A1B02B7
|
||||||
|
S3150800073C1B0AC02109060B43036200239360073387
|
||||||
|
S3150800074C1360002070470120FCE7C04610E000E06B
|
||||||
|
S3150800075C00ED00E030B5054C61690125294361615E
|
||||||
|
S3150800076C0260BFF36F8F436030BDC0460020024065
|
||||||
|
S3150800077C084B5B69002B01DB00207047054B064ACA
|
||||||
|
S3150800078C9A60064A9A605B69002B01DB0020F4E745
|
||||||
|
S3150800079C0120F2E70020024023016745AB89EFCD23
|
||||||
|
S315080007AC064B5969802212060A435A615B69002B6B
|
||||||
|
S315080007BC01DB012070470020FCE7C0460020024000
|
||||||
|
S315080007CC70B5050000F0CEFF4419134B1B69DB030B
|
||||||
|
S315080007DC05D500F0C7FFA042F7D3032070BD0E491C
|
||||||
|
S315080007EC0A690E4B14001C400D4808611A4203D0C6
|
||||||
|
S315080007FC0C4B5C600120F1E700F0B4FF4519064B81
|
||||||
|
S3150800080C1B695B0305D500F0ADFFA842F7D303209F
|
||||||
|
S3150800081CE4E70020E2E7C04600200240FAC30000E5
|
||||||
|
S3150800082CFBC3000034000020F8B507000C001500C7
|
||||||
|
S3150800083C1E00144B1B78012B22D0124B01221A7066
|
||||||
|
S3150800084C00225A60FA208000FFF7BAFF00280DD163
|
||||||
|
S3150800085C012F0FD02900200001F06EFAFA20800033
|
||||||
|
S3150800086CFFF7AEFF084A5369BB435361054B002299
|
||||||
|
S3150800087C1A70F8BD2A0033002000FFF76BFFEDE76E
|
||||||
|
S3150800088C0220F6E73400002000200240034A536990
|
||||||
|
S3150800089C03438020400218435061704700200240F1
|
||||||
|
S315080008AC044A536904480340C9001943034B1943C6
|
||||||
|
S315080008BC516170470020024007FEFFFF020001004D
|
||||||
|
S315080008CC70B504000E001F4B1B78012B37D01D4B3F
|
||||||
|
S315080008DC01221A7000225A60FA208000FFF770FF76
|
||||||
|
S315080008EC002828D1042363602368042B15D0012320
|
||||||
|
S315080008FC5B423360A568A368E26894466344AB42DE
|
||||||
|
S3150800090C14D929006068FFF7CBFFFA208000FFF79F
|
||||||
|
S3150800091C57FF002809D10135EDE70430FFF7B6FF7C
|
||||||
|
S3150800092CFA208000FFF74CFF05E03560064A53694C
|
||||||
|
S3150800093C02218B435361034B00221A7070BD0220AF
|
||||||
|
S3150800094CFCE7C0463400002000200240F0B5002326
|
||||||
|
S3150800095C5AE084685F000326BE40B4432600CC6880
|
||||||
|
S3150800096CBC4034438460446894434A68160901229F
|
||||||
|
S3150800097C32409A402243426056E0DC080834A40010
|
||||||
|
S3150800098C265805321A4092000F279740BE430F6926
|
||||||
|
S3150800099C97403A00324322505AE0032600E00026DC
|
||||||
|
S315080009ACA64034003C43434E1832920094518022A0
|
||||||
|
S315080009BCB458EA432600AE434F68FF0301D52C43CF
|
||||||
|
S315080009CC26003C4C8027E6518426A459260016405E
|
||||||
|
S315080009DC4F68BF0301D52C432600364C8427E651B5
|
||||||
|
S315080009EC2468260016404F68FF0201D52C432600C2
|
||||||
|
S315080009FC304C2660646822404E68B60201D52A003F
|
||||||
|
S31508000A0C22432C4C626001330C682200DA404FD02A
|
||||||
|
S31508000A1C01229A40250015401442F4D003244E684E
|
||||||
|
S31508000A2C3440013C012C94D903224C682240032AF9
|
||||||
|
S31508000A3C09D0C2685E000324B440A24314008A6835
|
||||||
|
S31508000A4CB2402243C26003224C682240022A94D048
|
||||||
|
S31508000A5C04685E0003221700B740BC434F683A404F
|
||||||
|
S31508000A6CB24022430260C02292024C681442CAD099
|
||||||
|
S31508000A7C9A0814001834A4000E4EA75903241C40D7
|
||||||
|
S31508000A8CE4000F26A640B743A026F605B04286D04A
|
||||||
|
S31508000A9C094EB04208D0094EB04207D0084EB042B3
|
||||||
|
S31508000AAC00D17AE705267BE7012679E7022677E760
|
||||||
|
S31508000ABCF0BDC04600180240000400500008005063
|
||||||
|
S31508000ACC000C0050002A01D0816170478162FCE756
|
||||||
|
S31508000ADC70B500F047FE0400254A116880235B00B8
|
||||||
|
S31508000AEC0B431360224B1B685B0506D400F03AFED9
|
||||||
|
S31508000AFC001B0228F6D9032070BD1D4D8023DB018F
|
||||||
|
S31508000B0C6B6000F02FFE04000023AB60184B9B684B
|
||||||
|
S31508000B1C38221A4207D000F025FE001B154B9842C6
|
||||||
|
S31508000B2CF4D90320E8E7124BC8321A601A6000F0B1
|
||||||
|
S31508000B3C19FE04000E4B1B689B0106D500F012FE2D
|
||||||
|
S31508000B4C001B0228F6D90320D6E7094B802252014E
|
||||||
|
S31508000B5CDA6000229A61013A1A62074B074A1A6050
|
||||||
|
S31508000B6C074B1868FFF752FD0028C5D00120C3E7CC
|
||||||
|
S31508000B7C0010024088130000000000200024F40036
|
||||||
|
S31508000B8C08000020A023DB0598420DD01F4B984285
|
||||||
|
S31508000B9C14D01F4B98421BD01E4B984222D01E4B8A
|
||||||
|
S31508000BAC984229D0012008E01C4B5A6A01210A43B5
|
||||||
|
S31508000BBC5A625A6A8A435A6200207047174B5A6A15
|
||||||
|
S31508000BCC02210A435A625A6A8A435A620020F4E797
|
||||||
|
S31508000BDC124B5A6A04210A435A625A6A8A435A625F
|
||||||
|
S31508000BEC0020EAE70D4B5A6A08210A435A625A6AE8
|
||||||
|
S31508000BFC8A435A620020E0E7084B5A6A20210A43C6
|
||||||
|
S31508000C0C5A625A6A8A435A620020D6E70004005090
|
||||||
|
S31508000C1C00080050000C0050001400500010024050
|
||||||
|
S31508000C2CF0B5002226E083682C006C436600361962
|
||||||
|
S31508000C3CB3438E687443234383604368AB43CC68E1
|
||||||
|
S31508000C4C6C4323434360C6682B006B435F00FF1855
|
||||||
|
S31508000C5CFC43A446BE430F695F433E43C6604C68DB
|
||||||
|
S31508000C6C022C16D0046865462C404D686B4323430A
|
||||||
|
S31508000C7C036001320C682300D34026D0012393402D
|
||||||
|
S31508000C8C25001D401C42F4D04B68013B012BDAD8D9
|
||||||
|
S31508000C9CC9E7FF2D0BD8066A1C006C4365432C016B
|
||||||
|
S31508000CAC641BA6434C69654335430562DAE7466A15
|
||||||
|
S31508000CBC2D0A2C006C436C4365432C01641BA6431C
|
||||||
|
S31508000CCC4C69654335434562CCE70020F0BD00000E
|
||||||
|
S31508000CDC054B9A68120A0F2313409B00034A9A582D
|
||||||
|
S31508000CEC1F231340D8407047001002407C1D000893
|
||||||
|
S31508000CFC054B9A68120B072313409B00034A9A5814
|
||||||
|
S31508000D0C1F231340D840704700100240BC1D000832
|
||||||
|
S31508000D1C10B50E4BDA6803231340032B13D00C4A79
|
||||||
|
S31508000D2C0A4CE3681B0A7F2018405043E3681B09EA
|
||||||
|
S31508000D3C072119400131FFF7DFF9E168490F013145
|
||||||
|
S31508000D4CFFF7DAF910BD034AEAE7C046001002407D
|
||||||
|
S31508000D5C0024F40000127A0010B50A4B9A6838235E
|
||||||
|
S31508000D6C1340082B0CD0102B02D1FFF7D1FF08E04B
|
||||||
|
S31508000D7C044B1A68D20A072313400348D84000E0EC
|
||||||
|
S31508000D8C024810BD001002400024F40000127A003C
|
||||||
|
S31508000D9C10B50400FFF7E0FF2060FFF799FF6060CD
|
||||||
|
S31508000DACFFF7A6FFA06010BD10B5032803D00C28CA
|
||||||
|
S31508000DBC2DD0002010BD2C4B5B6D0340000418434E
|
||||||
|
S31508000DCC2A4B98420FD02A4B984216D0294B984258
|
||||||
|
S31508000DDC06D0FFF7C1FFFFF77BFFFFF789FFE9E7AF
|
||||||
|
S31508000DECFFF7BAFFE6E7204B1A688023DB001000F2
|
||||||
|
S31508000DFC18401A42DED02048DCE71B4BDB6D02227A
|
||||||
|
S31508000E0C100018401A42D5D080200002D2E7164BA3
|
||||||
|
S31508000E1C5B6D034000041843184B98420FD0184BCF
|
||||||
|
S31508000E2C984216D0174B984206D0FFF795FFFFF756
|
||||||
|
S31508000E3C4FFFFFF75DFFBDE7FFF78EFFBAE70A4BDB
|
||||||
|
S31508000E4C1A688023DB00100018401A42B2D00A48F0
|
||||||
|
S31508000E5CB0E7054BDB6D0222100018401A42A9D0E8
|
||||||
|
S31508000E6C80200002A6E7C0460010024002000300DC
|
||||||
|
S31508000E7C03000300010003000024F40008000C0022
|
||||||
|
S31508000E8C0C000C0004000C0070B584B004000D00B6
|
||||||
|
S31508000E9C0368DB0700D578E003683D4A1A408B687F
|
||||||
|
S31508000EAC09690B4369690B43E9690B4313430360EF
|
||||||
|
S31508000EBC4368384A1340EA68134343608368364AE2
|
||||||
|
S31508000ECC1340AA6913438360344B984213D0344BAE
|
||||||
|
S31508000EDC98421AD0334B98421BD0334B98421DD0AC
|
||||||
|
S31508000EEC01202B68E26A0F218A431B041B0C13434F
|
||||||
|
S31508000EFCE36204B070BD0320FFF756FF002842D00A
|
||||||
|
S31508000F0C6E68002E0FD10120EBE70C20FFF74CFF83
|
||||||
|
S31508000F1CF4E701A8FFF73CFF0398EFE701A8FFF7F2
|
||||||
|
S31508000F2C37FF0398EAE72B68EA690B2B14D8002ECF
|
||||||
|
S31508000F3C12D0802109028A4210D0FF2213409B004E
|
||||||
|
S31508000F4C1A4A9958FFF7D8F87308C0183100FFF7F2
|
||||||
|
S31508000F5CD3F80004000CE0600020C2E7FF2213401F
|
||||||
|
S31508000F6C9B00124A9958FFF7C7F840007308C01837
|
||||||
|
S31508000F7C3100FFF7C1F80E4B03404008072210401A
|
||||||
|
S31508000F8C1843E060E8E70120ABE70120B1E7C0466B
|
||||||
|
S31508000F9CF369FFEFFFCFFFFFFFFCFFFF00380140AF
|
||||||
|
S31508000FAC0044004000480040004C0040DC1D00088E
|
||||||
|
S31508000FBCF0FF0000014B18607047C0460000002087
|
||||||
|
S31508000FCC72B6704762B6704710B5FFF7F9FF10BDD9
|
||||||
|
S31508000FDC10B500F0CFFA002800D110BDFFF720F9A4
|
||||||
|
S31508000FEC0028FAD000F040FCFFF7FCFA00F088FB6A
|
||||||
|
S31508000FFC00F0C4FA054B1840054B986000F0BEFA91
|
||||||
|
S3150800100C4468FFF7DFFFA047E7E7C04680FFFF1FEE
|
||||||
|
S3150800101C00ED00E070B5541EA4B2002A09D04D1C90
|
||||||
|
S3150800102C461C0B78037000F05EFC30002900220089
|
||||||
|
S3150800103CF1E770BD70B50500002401E00134E4B297
|
||||||
|
S3150800104C0D2C17D800F04FFC63001B199B000A499E
|
||||||
|
S3150800105C5B58AB42F2D86100091989000648411859
|
||||||
|
S3150800106C49685B18AB42E9D963001A1992008218D1
|
||||||
|
S3150800107C107A00E0FF2070BD581E000870B50500F8
|
||||||
|
S3150800108C00240D2C11D800F02EFC63001B199B00B4
|
||||||
|
S3150800109C074AD3181B7AAB4202D00134E4B2F0E704
|
||||||
|
S315080010AC630019198900885801E00120404270BD77
|
||||||
|
S315080010BC581E000870B5050000240D2C12D800F037
|
||||||
|
S315080010CC12FC63001B199B00074AD3181B7AAB4208
|
||||||
|
S315080010DC02D00134E4B2F0E76300191989005118FB
|
||||||
|
S315080010EC486800E0002070BD581E000810B5CB05F6
|
||||||
|
S315080010FC0BD103688B4201D1012007E002C0802284
|
||||||
|
S3150800110C9200FFF787FF012000E0002010BDF8B51C
|
||||||
|
S3150800111CCE46474680B581460068FFF78BFFFF2809
|
||||||
|
S3150800112C06D1002398464046C0BCB946B046F8BD21
|
||||||
|
S3150800113CFFF71EFB002500E001353F2D18D8EB0004
|
||||||
|
S3150800114C4A461268D4184B445E689F6800F0CBFB7D
|
||||||
|
S3150800115C32003B0021000120FFF766FB8046002881
|
||||||
|
S3150800116C09D122686368B24207D1BB42E4D004E0D5
|
||||||
|
S3150800117C0123984601E000239846FFF711FBD2E7B6
|
||||||
|
S3150800118C70B504000D000F4B984214D00E4B9942C3
|
||||||
|
S3150800119C0BD10C4E3400002E05D029002000FFF789
|
||||||
|
S315080011ACA5FF00280CD0300070BDFFF7B0FF012852
|
||||||
|
S315080011BC04D00026EFE7054E3400ECE72600EAE7F4
|
||||||
|
S315080011CC0026F0E7540200200028000850000020F2
|
||||||
|
S315080011DCF8B5CE46474680B505000C0016001F002C
|
||||||
|
S315080011EC4B0A5B029846036801330CD02B684345BF
|
||||||
|
S315080011FC10D1012399464B46012B14D04846C0BC46
|
||||||
|
S3150800120CB946B046F8BD4146FFF770FF814600283F
|
||||||
|
S3150800121CF1D0EBE741462800FFF7B2FF051E1FD0B9
|
||||||
|
S3150800122C01239946E7E72B68E41A2C19043406E0DF
|
||||||
|
S3150800123C3378237001340136013F002FDED000F0DD
|
||||||
|
S3150800124C52FB291D611A80239B009942F0D3190081
|
||||||
|
S3150800125C41442800FFF794FF051E04D0041DE7E758
|
||||||
|
S3150800126C00239946CAE700239946C7E710B5040038
|
||||||
|
S3150800127C80231B0598420DD3F8231B069C46644411
|
||||||
|
S3150800128C094B1B689B02FF22920213409C4206D212
|
||||||
|
S3150800129C042010BD0549064800F068FAECE7054934
|
||||||
|
S315080012AC034800F063FAF3E7E075FF1FAE0300008E
|
||||||
|
S315080012BC0C1E0008AF03000070B5040080231B0544
|
||||||
|
S315080012CC984211D3F8231B06E5180D4B1B689B0295
|
||||||
|
S315080012DCFF22920213409D420BD22000FFF7C6FF55
|
||||||
|
S315080012EC04280BD0002070BD0649074800F03EFACA
|
||||||
|
S315080012FCE8E70649044800F039FAEEE7E80AF2E7A7
|
||||||
|
S3150800130CE075FF1FCD0300000C1E0008CE0300007D
|
||||||
|
S3150800131CF0B587B00C0000230593884205D804283D
|
||||||
|
S3150800132C3DD912293DD8012700E00027012F02D00C
|
||||||
|
S3150800133C380007B0F0BDFFF7A1FE05002000FFF747
|
||||||
|
S3150800134C9DFE06002000FFF7B5FE3618013E761BFB
|
||||||
|
S3150800135C0136F60AB6B202230193013B0493FFF752
|
||||||
|
S3150800136C07FA0024B44217D22800FFF7A5FF03900A
|
||||||
|
S3150800137C2800FFF77BFF029000F0B5FA05A901A833
|
||||||
|
S3150800138CFFF79EFA002806D180231B019C4665446C
|
||||||
|
S3150800139C0134A4B2E6E70027FFF702FAC8E70027EC
|
||||||
|
S315080013ACC6E70027C4E7000001235B42024A136024
|
||||||
|
S315080013BC024A13607047C0465000002054020020B1
|
||||||
|
S315080013CC70B504000D0016004A1E124B1B1A9A42E1
|
||||||
|
S315080013DC01D9002070BDFFF72DFEFF2811D0281962
|
||||||
|
S315080013EC0138FFF727FEFF280BD0630A5B020A4A6F
|
||||||
|
S315080013FC934208D02B00320021000848FFF7E8FE7C
|
||||||
|
S3150800140CE8E70020E6E72B00320021000448FFF746
|
||||||
|
S3150800141CDFFEDFE7FFFF0108002800085000002068
|
||||||
|
S3150800142C5402002070B505000C004A1E0F4B1B1AFF
|
||||||
|
S3150800143C9A4205D9FF21FF260020012812D070BD3B
|
||||||
|
S3150800144CFFF7F8FD060060190138FFF7F3FD0100F8
|
||||||
|
S3150800145CFF2E03D0FF2803D00120EEE70020ECE78F
|
||||||
|
S3150800146C0020EAE73000FFF753FFE8E7FFFF010823
|
||||||
|
S3150800147C00B583B0104B1B68013302D1012003B0B1
|
||||||
|
S3150800148C00BD0D4A536891688C466344D1688C46F6
|
||||||
|
S3150800149C634411698C46634451698C46634491696B
|
||||||
|
S315080014AC8C466344D2699B185B42019301AA0421BA
|
||||||
|
S315080014BC0248FFF785FFE2E754020020BC28000823
|
||||||
|
S315080014CC0E4B1A680E4B1B68D2180E4B1B689A18D3
|
||||||
|
S315080014DC0D4B1B689B180D4A1268D3180C4A1268D8
|
||||||
|
S315080014ECD2180C4B1B689A180B4B1B689B18002BB5
|
||||||
|
S315080014FC01D1012070470020FCE7C04600280008EF
|
||||||
|
S3150800150C04280008082800080C28000810280008D9
|
||||||
|
S3150800151C1428000818280008BC28000810B50B4B1E
|
||||||
|
S3150800152C1B68013305D10A4B1B68013307D101200F
|
||||||
|
S3150800153C10BD0648FFF7EBFD0028F9D0F3E7044881
|
||||||
|
S3150800154CFFF7E5FD0028F3D00120F1E7540200204F
|
||||||
|
S3150800155C50000020004870470028000810B5FFF717
|
||||||
|
S3150800156C23FF10BD10B5FFF72BFF10BD10B5FFF705
|
||||||
|
S3150800157C59FF10BD10B5FFF7A3FF10BD10B5FFF747
|
||||||
|
S3150800158CE9FF10BD10B5FFF773FF002800D110BD99
|
||||||
|
S3150800159CFFF7C4FFFBE70000054BDB699B0604D588
|
||||||
|
S315080015AC034B5B6A0370012070470020FCE7C046BA
|
||||||
|
S315080015BC0044004010B5084B986200F0CBF80A308E
|
||||||
|
S315080015CC0400054BDB691B0605D400F08CF900F00A
|
||||||
|
S315080015DCC1F8A042F5D910BD0044004030B589B019
|
||||||
|
S315080015EC0C4C23680125AB432360E1231B020193B2
|
||||||
|
S315080015FC00230293039304930C22059206930793F4
|
||||||
|
S3150800160C009369462000FFF73FFC23682B432360B1
|
||||||
|
S3150800161C09B030BD0044004070B506000D004029E5
|
||||||
|
S3150800162C0ED82800FFF7C6FF0024ABB2A3420CD98C
|
||||||
|
S3150800163C00F059F9305DFFF7BDFF0134A4B2F4E7A9
|
||||||
|
S3150800164C7621024800F092F8EBE770BD001F0008FF
|
||||||
|
S3150800165C70B506000D00264B1C78002C17D12548B2
|
||||||
|
S3150800166CFFF79AFF012801D0200070BD214B1B788B
|
||||||
|
S3150800167C013BDBB23F2BF7D800F06CF81E4B186019
|
||||||
|
S3150800168C1E4B00221A701A4B01321A70ECE71B4BD0
|
||||||
|
S3150800169C1B7801331748C018FFF77EFF0400012892
|
||||||
|
S315080016AC17D1164B1A780132D2B21A70114B1B7815
|
||||||
|
S315080016BC9A4201D00024D7E792B20E490131300084
|
||||||
|
S315080016CCFFF7A8FC0A4B00221A700C4B1B782B70E0
|
||||||
|
S315080016DCCAE700F03FF8084B1B686433984204D9F4
|
||||||
|
S315080016EC034B00221A700024BEE70024BCE7C04650
|
||||||
|
S315080016FC99040020580400209C0400209A04002019
|
||||||
|
S3150800170C024B00221A605A609A60704710E000E09B
|
||||||
|
S3150800171C10B5FFF7F5FF054B054A5A6000229A608B
|
||||||
|
S3150800172C05211960034B1A6010BDC04610E000E095
|
||||||
|
S3150800173CFFF90000A0040020044B1B68DB0303D54B
|
||||||
|
S3150800174C034A1368013313607047C04610E000E083
|
||||||
|
S3150800175CA004002010B5FFF7EFFF014B186810BD69
|
||||||
|
S3150800176CA004002010B5FFF7F5FF10BD10B500F06A
|
||||||
|
S3150800177CBAF8FCE710B500F0ABF8012803D00B4B10
|
||||||
|
S3150800178C1B78012B00D010BDFFF7E4FF084B1B6834
|
||||||
|
S3150800179C084A12689B18F533FF339842F3D3034B68
|
||||||
|
S315080017AC00221A70FFF714FCEDE7C046A8040020C7
|
||||||
|
S315080017BCA4040020AC04002010B5054B1B78012BA3
|
||||||
|
S315080017CC00D010BDFFF7C6FF024B1860F9E7C046FC
|
||||||
|
S315080017DCA8040020AC04002010B5044B01221A7092
|
||||||
|
S315080017ECFFF7EAFFFFF7C6FF10BDC046A8040020A6
|
||||||
|
S315080017FC10B5FFF7E9FB00F072F8FFF789FFFFF762
|
||||||
|
S3150800180CADFE00F00DF8FFF7E7FF10BD10B500F0C0
|
||||||
|
S3150800181C6AF8FFF791FF00F00FF8FFF7ABFF10BD62
|
||||||
|
S3150800182C10B500F0D7F9FFF7D9FE024B00221A7053
|
||||||
|
S3150800183C10BDC0460C00002000B583B06B46D91D00
|
||||||
|
S3150800184C0748FFF705FF012801D003B000BD054B7B
|
||||||
|
S3150800185C00221A706B46D979014800F0D9F9F4E7D9
|
||||||
|
S3150800186CB00400200C0000207047000010B5054B92
|
||||||
|
S3150800187C1B78002B02D000F0C3F910BDC9B2FFF7D4
|
||||||
|
S3150800188CCBFEF8E70C000020074B1B78022B07D081
|
||||||
|
S3150800189C032B07D0012B01D0402070470020FCE712
|
||||||
|
S315080018AC0020FAE70020F8E70C000020074B1B780D
|
||||||
|
S315080018BC022B07D0032B07D0012B01D040207047F1
|
||||||
|
S315080018CC0020FCE70020FAE70020F8E70C000020CF
|
||||||
|
S315080018DC10B500F08DF9002800D0012010BD10B508
|
||||||
|
S315080018ECFEF7ACFC10BD10B5FEF7ADFC10BD000044
|
||||||
|
S315080018FC014B00225A707047F0040020034BFE225D
|
||||||
|
S3150800190CDA701871BA3A022199527047F00400201D
|
||||||
|
S3150800191C10B5054C00232370FFF7EAFFFF23E3708D
|
||||||
|
S3150800192CBB3B0122E25210BDF0040020064BFF22FD
|
||||||
|
S3150800193CDA7000221A71597859719A71DA711A7219
|
||||||
|
S3150800194C4432062199527047F004002010B5002045
|
||||||
|
S3150800195CFFF7D4FF10BD0000094BFF22DA70094AC5
|
||||||
|
S3150800196C9A6400221A715A719A710721D971002149
|
||||||
|
S3150800197C1972597299724422083199527047C046A5
|
||||||
|
S3150800198CF004002024200008044BFF22DA70426879
|
||||||
|
S3150800199C9A644422012199527047C046F0040020EB
|
||||||
|
S315080019AC10B53120FFF7AAFF10BD000070B5084C22
|
||||||
|
S315080019BCFF23E370002525716571FFF765FFA0719C
|
||||||
|
S315080019CCE5712572657244230722E25270BDC04642
|
||||||
|
S315080019DCF004002070B5FFF78BFF0D4C0125257020
|
||||||
|
S315080019ECFF23E370EF3B237100236371FFF74CFF72
|
||||||
|
S315080019FCA071FFF75BFFE071FFF758FF000A207232
|
||||||
|
S31508001A0C6572A57244230822E252FFF7A7FD70BD42
|
||||||
|
S31508001A1CF004002070B50400FFF736FF6278904298
|
||||||
|
S31508001A2C10D90A4D281DA96CFFF7F4FAFF23EB70A1
|
||||||
|
S31508001A3C6378AA6C94466344AB6463780133442296
|
||||||
|
S31508001A4CAB5270BD2220FFF759FFFAE7F0040020CD
|
||||||
|
S31508001A5C70B50400FFF718FF6378984212D96168CD
|
||||||
|
S31508001A6C0A4DA9646278281DFFF7D4FAFF23EB7098
|
||||||
|
S31508001A7C6378AA6C94466344AB6463780133442256
|
||||||
|
S31508001A8CAB5270BD2220FFF739FFFAE7F0040020AD
|
||||||
|
S31508001A9CF8B50500170000244E1E002907D02B7830
|
||||||
|
S31508001AAC1C19E4B20135FFF71EFF3100F4E73C6060
|
||||||
|
S31508001ABC0120F8BD10B5084CFF23E370E21D416800
|
||||||
|
S31508001ACCA06CFFF7E5FF207100236371A371443303
|
||||||
|
S31508001ADC0822E25210BDC046F004002070B504007E
|
||||||
|
S31508001AEC0E4B9D6CFFF7D0FE411E621C2800FFF7BB
|
||||||
|
S31508001AFC39FD00280DD0094CFF23E370FFF7C4FE0F
|
||||||
|
S31508001B0C0138A36C9C466044A06444230122E2522B
|
||||||
|
S31508001B1C70BD3130FFF7F2FEFAE7C046F00400203C
|
||||||
|
S31508001B2C10B50400FFF7B0FE01386378984216DD4D
|
||||||
|
S31508001B3C134BFF22DA70BB3A0121995261780029BE
|
||||||
|
S31508001B4C11D00F4B986CA21CFFF70CFD002812D075
|
||||||
|
S31508001B5C63780B4A916C8C466344936410BD2220BF
|
||||||
|
S31508001B6CFFF7CCFEFAE7FFF70DFD0028F6D131306A
|
||||||
|
S31508001B7CFFF7C4FEF2E73130FFF7C0FEEEE7C046CA
|
||||||
|
S31508001B8CF004002010B5094B9B6C41681800FFF750
|
||||||
|
S31508001B9CEDFC002806D0054BFF22DA70BB3A012172
|
||||||
|
S31508001BAC995210BD3130FFF7A9FEFAE7F004002070
|
||||||
|
S31508001BBC10B5FFF70DFA034BFF22DA70BB3A012179
|
||||||
|
S31508001BCC995210BDF004002010B589B2FFF74EFEED
|
||||||
|
S31508001BDC10BD0000054B00221A709A6443215A5412
|
||||||
|
S31508001BEC01315A529A705A707047C046F004002058
|
||||||
|
S31508001BFC024B1878002800D001207047F00400200A
|
||||||
|
S31508001C0C024A43230021D1547047C046F0040020F1
|
||||||
|
S31508001C1C10B50378FF2B0BD0294A1278012A13D159
|
||||||
|
S31508001C2C3733DAB2352A3AD89300264AD3589F4620
|
||||||
|
S31508001C3CFFF7D0FE224A4323D35C012B33D0204A2C
|
||||||
|
S31508001C4C4423D15E002932DC10BDFFF7E3FEF1E731
|
||||||
|
S31508001C5CFFF7FEFEEEE7FFF797FEEBE7FFF72AFF27
|
||||||
|
S31508001C6CE8E7FFF779FEE5E7FFF770FEE2E7FFF72F
|
||||||
|
S31508001C7C5DFEDFE7FFF74CFEDCE7FFF72FFFD9E742
|
||||||
|
S31508001C8CFFF74EFFD6E7FFF791FED3E7FFF77AFF8C
|
||||||
|
S31508001C9CD0E7FFF78DFFCDE7FFF782FECAE72020D6
|
||||||
|
S31508001CACFFF72CFEC6E71020FFF728FEC7E7100043
|
||||||
|
S31508001CBC43230122C2540330FFF786FFC4E7C0460C
|
||||||
|
S31508001CCCF00400204C1F000870B500260C4D0D4C76
|
||||||
|
S31508001CDC641BA410A64209D1002600F021F80A4D6F
|
||||||
|
S31508001CEC0A4C641BA410A64205D170BDB300EB5870
|
||||||
|
S31508001CFC98470136EEE7B300EB5898470136F2E7FA
|
||||||
|
S31508001D0C2C2000082C2000082C2000083020000865
|
||||||
|
S31508001D1C03008218934200D1704719700133F9E712
|
||||||
|
S31508001D2CF8B5C046F8BC08BC9E467047F8B5C04620
|
||||||
|
S30D08001D3CF8BC08BC9E4670477E
|
||||||
|
S31508001D4410B50C4A54698023DB0223435361EFF32D
|
||||||
|
S31508001D54108472B6002303E004C904C00133DBB25D
|
||||||
|
S31508001D643F2BF9D9034B1B69DB03FBD484F3108897
|
||||||
|
S30D08001D7410BDC0460020024024
|
||||||
|
S31508001D7C0000000000000000000000000000000049
|
||||||
|
S31508001D8C0000000000000000000000000000000039
|
||||||
|
S31508001D9C010000000200000003000000040000001F
|
||||||
|
S31508001DAC06000000070000000800000009000000FB
|
||||||
|
S31508001DBC0000000000000000000000000000000009
|
||||||
|
S31508001DCC01000000020000000300000004000000EF
|
||||||
|
S31508001DDC01000000020000000400000006000000DC
|
||||||
|
S31508001DEC080000000A0000000C00000010000000AB
|
||||||
|
S31508001DFC20000000400000008000000000010000E8
|
||||||
|
S31508001E0C433A2F576F726B2F736F667477617265CF
|
||||||
|
S31508001E1C2F4F70656E424C545F53544D33324730D6
|
||||||
|
S31508001E2C5F43414E2F5461726765742F536F7572F9
|
||||||
|
S31508001E3C63652F41524D434D305F53544D333247F2
|
||||||
|
S31508001E4C302F666C6173682E63000000002800084A
|
||||||
|
S31508001E5C000800000500000000300008000800001B
|
||||||
|
S31508001E6C0600000000380008000800000700000003
|
||||||
|
S31508001E7C00400008000800000800000000480008A0
|
||||||
|
S31508001E8C00080000090000000050000800080000C7
|
||||||
|
S31508001E9C0A00000000580008000800000B000000AB
|
||||||
|
S31508001EAC00600008000800000C000000006800082C
|
||||||
|
S31508001EBC000800000D000000007000080008000073
|
||||||
|
S31508001ECC0E00000000780008000800000F00000053
|
||||||
|
S31508001EDC00800008008000001000000000000108C7
|
||||||
|
S31508001EEC008000001100000000800108008000003E
|
||||||
|
S31508001EFC12000000433A2F576F726B2F736F66747C
|
||||||
|
S31508001F0C776172652F4F70656E424C545F53544D12
|
||||||
|
S31508001F1C333247305F43414E2F5461726765742FD5
|
||||||
|
S31508001F2C536F757263652F41524D434D305F535451
|
||||||
|
S31508001F3C4D333247302F72733233322E6300000022
|
||||||
|
S31508001F4C861C0008AA1C0008AA1C0008A41C000869
|
||||||
|
S31508001F5CAA1C0008AA1C00089E1C00088C1C000859
|
||||||
|
S31508001F6C981C0008921C0008AA1C0008AA1C000849
|
||||||
|
S31508001F7CAA1C0008AA1C0008AA1C0008AA1C00080F
|
||||||
|
S31508001F8CAA1C0008AA1C0008AA1C0008AA1C0008FF
|
||||||
|
S31508001F9CAA1C0008AA1C0008AA1C0008AA1C0008EF
|
||||||
|
S31508001FACAA1C0008AA1C0008AA1C0008AA1C0008DF
|
||||||
|
S31508001FBCAA1C0008AA1C0008AA1C0008AA1C0008CF
|
||||||
|
S31508001FCCAA1C0008AA1C0008AA1C0008AA1C0008BF
|
||||||
|
S31508001FDCAA1C0008AA1C0008AA1C0008AA1C0008AF
|
||||||
|
S31508001FECAA1C0008AA1C0008681C00085C1C00082F
|
||||||
|
S31508001FFC561C0008621C0008AA1C0008AA1C00082B
|
||||||
|
S3150800200CAA1C00086E1C0008AA1C0008741C0008F0
|
||||||
|
S3150800201C7A1C0008801C00084F70656E424C5400F0
|
||||||
|
S3090800202CE5000008B5
|
||||||
|
S30908002030BD000008D9
|
||||||
|
S315080020340024F4000100000004000000040000006D
|
||||||
|
S7050800059D50
|
||||||
7725
Boot/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g070xx.h
Normal file
7725
Boot/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g070xx.h
Normal file
File diff suppressed because it is too large
Load Diff
244
Boot/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h
Normal file
244
Boot/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h
Normal file
@@ -0,0 +1,244 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32g0xx.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @brief CMSIS STM32G0xx Device Peripheral Access Layer Header File.
|
||||||
|
*
|
||||||
|
* The file is the unique include file that the application programmer
|
||||||
|
* is using in the C source code, usually in main.c. This file contains:
|
||||||
|
* - Configuration section that allows to select:
|
||||||
|
* - The STM32G0xx device used in the target application
|
||||||
|
* - To use or not the peripherals drivers in application code(i.e.
|
||||||
|
* code will be based on direct access to peripherals registers
|
||||||
|
* rather than drivers API), this option is controlled by
|
||||||
|
* "#define USE_HAL_DRIVER"
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* Copyright (c) 2018-2021 STMicroelectronics.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* This software is licensed under terms that can be found in the LICENSE file
|
||||||
|
* in the root directory of this software component.
|
||||||
|
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
/** @addtogroup CMSIS
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup stm32g0xx
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef STM32G0xx_H
|
||||||
|
#define STM32G0xx_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif /* __cplusplus */
|
||||||
|
|
||||||
|
/** @addtogroup Library_configuration_section
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief STM32 Family
|
||||||
|
*/
|
||||||
|
#if !defined (STM32G0)
|
||||||
|
#define STM32G0
|
||||||
|
#endif /* STM32G0 */
|
||||||
|
|
||||||
|
/* Uncomment the line below according to the target STM32G0 device used in your
|
||||||
|
application
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if !defined (STM32G071xx) && !defined (STM32G081xx) && !defined (STM32G070xx) \
|
||||||
|
&& !defined (STM32G030xx) && !defined (STM32G031xx) && !defined (STM32G041xx) \
|
||||||
|
&& !defined (STM32G0B0xx) && !defined (STM32G0B1xx) && !defined (STM32G0C1xx) \
|
||||||
|
&& !defined (STM32G050xx) && !defined (STM32G051xx) && !defined (STM32G061xx)
|
||||||
|
/* #define STM32G0B0xx */ /*!< STM32G0B0xx Devices */
|
||||||
|
/* #define STM32G0B1xx */ /*!< STM32G0B1xx Devices */
|
||||||
|
/* #define STM32G0C1xx */ /*!< STM32G0C1xx Devices */
|
||||||
|
/* #define STM32G070xx */ /*!< STM32G070xx Devices */
|
||||||
|
/* #define STM32G071xx */ /*!< STM32G071xx Devices */
|
||||||
|
/* #define STM32G081xx */ /*!< STM32G081xx Devices */
|
||||||
|
/* #define STM32G050xx */ /*!< STM32G050xx Devices */
|
||||||
|
/* #define STM32G051xx */ /*!< STM32G051xx Devices */
|
||||||
|
/* #define STM32G061xx */ /*!< STM32G061xx Devices */
|
||||||
|
/* #define STM32G030xx */ /*!< STM32G030xx Devices */
|
||||||
|
/* #define STM32G031xx */ /*!< STM32G031xx Devices */
|
||||||
|
/* #define STM32G041xx */ /*!< STM32G041xx Devices */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Tip: To avoid modifying this file each time you need to switch between these
|
||||||
|
devices, you can define the device in your toolchain compiler preprocessor.
|
||||||
|
*/
|
||||||
|
#if !defined (USE_HAL_DRIVER)
|
||||||
|
/**
|
||||||
|
* @brief Comment the line below if you will not use the peripherals drivers.
|
||||||
|
In this case, these drivers will not be included and the application code will
|
||||||
|
be based on direct access to peripherals registers
|
||||||
|
*/
|
||||||
|
/*#define USE_HAL_DRIVER */
|
||||||
|
#endif /* USE_HAL_DRIVER */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief CMSIS Device version number $VERSION$
|
||||||
|
*/
|
||||||
|
#define __STM32G0_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
|
||||||
|
#define __STM32G0_CMSIS_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */
|
||||||
|
#define __STM32G0_CMSIS_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */
|
||||||
|
#define __STM32G0_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
|
||||||
|
#define __STM32G0_CMSIS_VERSION ((__STM32G0_CMSIS_VERSION_MAIN << 24)\
|
||||||
|
|(__STM32G0_CMSIS_VERSION_SUB1 << 16)\
|
||||||
|
|(__STM32G0_CMSIS_VERSION_SUB2 << 8 )\
|
||||||
|
|(__STM32G0_CMSIS_VERSION_RC))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup Device_Included
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined(STM32G0B1xx)
|
||||||
|
#include "stm32g0b1xx.h"
|
||||||
|
#elif defined(STM32G0C1xx)
|
||||||
|
#include "stm32g0c1xx.h"
|
||||||
|
#elif defined(STM32G0B0xx)
|
||||||
|
#include "stm32g0b0xx.h"
|
||||||
|
#elif defined(STM32G071xx)
|
||||||
|
#include "stm32g071xx.h"
|
||||||
|
#elif defined(STM32G081xx)
|
||||||
|
#include "stm32g081xx.h"
|
||||||
|
#elif defined(STM32G070xx)
|
||||||
|
#include "stm32g070xx.h"
|
||||||
|
#elif defined(STM32G031xx)
|
||||||
|
#include "stm32g031xx.h"
|
||||||
|
#elif defined(STM32G041xx)
|
||||||
|
#include "stm32g041xx.h"
|
||||||
|
#elif defined(STM32G030xx)
|
||||||
|
#include "stm32g030xx.h"
|
||||||
|
#elif defined(STM32G051xx)
|
||||||
|
#include "stm32g051xx.h"
|
||||||
|
#elif defined(STM32G061xx)
|
||||||
|
#include "stm32g061xx.h"
|
||||||
|
#elif defined(STM32G050xx)
|
||||||
|
#include "stm32g050xx.h"
|
||||||
|
#else
|
||||||
|
#error "Please select first the target STM32G0xx device used in your application (in stm32g0xx.h file)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup Exported_types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
RESET = 0,
|
||||||
|
SET = !RESET
|
||||||
|
} FlagStatus, ITStatus;
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
DISABLE = 0,
|
||||||
|
ENABLE = !DISABLE
|
||||||
|
} FunctionalState;
|
||||||
|
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
SUCCESS = 0,
|
||||||
|
ERROR = !SUCCESS
|
||||||
|
} ErrorStatus;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Exported_macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
|
||||||
|
|
||||||
|
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
|
||||||
|
|
||||||
|
#define READ_BIT(REG, BIT) ((REG) & (BIT))
|
||||||
|
|
||||||
|
#define CLEAR_REG(REG) ((REG) = (0x0))
|
||||||
|
|
||||||
|
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
|
||||||
|
|
||||||
|
#define READ_REG(REG) ((REG))
|
||||||
|
|
||||||
|
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
|
||||||
|
|
||||||
|
/* Use of interrupt control for register exclusive access */
|
||||||
|
/* Atomic 32-bit register access macro to set one or several bits */
|
||||||
|
#define ATOMIC_SET_BIT(REG, BIT) \
|
||||||
|
do { \
|
||||||
|
uint32_t primask; \
|
||||||
|
primask = __get_PRIMASK(); \
|
||||||
|
__set_PRIMASK(1); \
|
||||||
|
SET_BIT((REG), (BIT)); \
|
||||||
|
__set_PRIMASK(primask); \
|
||||||
|
} while(0)
|
||||||
|
|
||||||
|
/* Atomic 32-bit register access macro to clear one or several bits */
|
||||||
|
#define ATOMIC_CLEAR_BIT(REG, BIT) \
|
||||||
|
do { \
|
||||||
|
uint32_t primask; \
|
||||||
|
primask = __get_PRIMASK(); \
|
||||||
|
__set_PRIMASK(1); \
|
||||||
|
CLEAR_BIT((REG), (BIT)); \
|
||||||
|
__set_PRIMASK(primask); \
|
||||||
|
} while(0)
|
||||||
|
|
||||||
|
/* Atomic 32-bit register access macro to clear and set one or several bits */
|
||||||
|
#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
|
||||||
|
do { \
|
||||||
|
uint32_t primask; \
|
||||||
|
primask = __get_PRIMASK(); \
|
||||||
|
__set_PRIMASK(1); \
|
||||||
|
MODIFY_REG((REG), (CLEARMSK), (SETMASK)); \
|
||||||
|
__set_PRIMASK(primask); \
|
||||||
|
} while(0)
|
||||||
|
|
||||||
|
/* Atomic 16-bit register access macro to set one or several bits */
|
||||||
|
#define ATOMIC_SETH_BIT(REG, BIT) ATOMIC_SET_BIT(REG, BIT) \
|
||||||
|
|
||||||
|
/* Atomic 16-bit register access macro to clear one or several bits */
|
||||||
|
#define ATOMIC_CLEARH_BIT(REG, BIT) ATOMIC_CLEAR_BIT(REG, BIT) \
|
||||||
|
|
||||||
|
/* Atomic 16-bit register access macro to clear and set one or several bits */
|
||||||
|
#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
|
||||||
|
|
||||||
|
/*#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))*/
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined (USE_HAL_DRIVER)
|
||||||
|
#include "stm32g0xx_hal.h"
|
||||||
|
#endif /* USE_HAL_DRIVER */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif /* __cplusplus */
|
||||||
|
|
||||||
|
#endif /* STM32G0xx_H */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
@@ -0,0 +1,103 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file system_stm32g0xx.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @brief CMSIS Cortex-M0+ Device System Source File for STM32G0xx devices.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* Copyright (c) 2018-2021 STMicroelectronics.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* This software is licensed under terms that can be found in the LICENSE file
|
||||||
|
* in the root directory of this software component.
|
||||||
|
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
/** @addtogroup CMSIS
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup stm32g0xx_system
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Define to prevent recursive inclusion
|
||||||
|
*/
|
||||||
|
#ifndef SYSTEM_STM32G0XX_H
|
||||||
|
#define SYSTEM_STM32G0XX_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** @addtogroup STM32G0xx_System_Includes
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup STM32G0xx_System_Exported_types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* This variable is updated in three ways:
|
||||||
|
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||||
|
2) by calling HAL API function HAL_RCC_GetSysClockFreq()
|
||||||
|
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||||
|
Note: If you use this function to configure the system clock; then there
|
||||||
|
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||||
|
variable is updated automatically.
|
||||||
|
*/
|
||||||
|
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||||
|
|
||||||
|
extern const uint32_t AHBPrescTable[16]; /*!< AHB prescalers table values */
|
||||||
|
extern const uint32_t APBPrescTable[8]; /*!< APB prescalers table values */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup STM32G0xx_System_Exported_Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup STM32G0xx_System_Exported_Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup STM32G0xx_System_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
extern void SystemInit(void);
|
||||||
|
extern void SystemCoreClockUpdate(void);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /*SYSTEM_STM32G0XX_H */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
6
Boot/Drivers/CMSIS/Device/ST/STM32G0xx/LICENSE.txt
Normal file
6
Boot/Drivers/CMSIS/Device/ST/STM32G0xx/LICENSE.txt
Normal file
@@ -0,0 +1,6 @@
|
|||||||
|
This software component is provided to you as part of a software package and
|
||||||
|
applicable license terms are in the Package_license file. If you received this
|
||||||
|
software component outside of a package or without applicable license terms,
|
||||||
|
the terms of the Apache-2.0 license shall apply.
|
||||||
|
You may obtain a copy of the Apache-2.0 at:
|
||||||
|
https://opensource.org/licenses/Apache-2.0
|
||||||
894
Boot/Drivers/CMSIS/Include/cmsis_armcc.h
Normal file
894
Boot/Drivers/CMSIS/Include/cmsis_armcc.h
Normal file
@@ -0,0 +1,894 @@
|
|||||||
|
/**************************************************************************//**
|
||||||
|
* @file cmsis_armcc.h
|
||||||
|
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
|
||||||
|
* @version V5.1.0
|
||||||
|
* @date 08. May 2019
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CMSIS_ARMCC_H
|
||||||
|
#define __CMSIS_ARMCC_H
|
||||||
|
|
||||||
|
|
||||||
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
|
||||||
|
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* CMSIS compiler control architecture macros */
|
||||||
|
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
|
||||||
|
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
|
||||||
|
#define __ARM_ARCH_6M__ 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
|
||||||
|
#define __ARM_ARCH_7M__ 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
|
||||||
|
#define __ARM_ARCH_7EM__ 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* __ARM_ARCH_8M_BASE__ not applicable */
|
||||||
|
/* __ARM_ARCH_8M_MAIN__ not applicable */
|
||||||
|
|
||||||
|
/* CMSIS compiler control DSP macros */
|
||||||
|
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||||
|
#define __ARM_FEATURE_DSP 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* CMSIS compiler specific defines */
|
||||||
|
#ifndef __ASM
|
||||||
|
#define __ASM __asm
|
||||||
|
#endif
|
||||||
|
#ifndef __INLINE
|
||||||
|
#define __INLINE __inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_INLINE
|
||||||
|
#define __STATIC_INLINE static __inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_FORCEINLINE
|
||||||
|
#define __STATIC_FORCEINLINE static __forceinline
|
||||||
|
#endif
|
||||||
|
#ifndef __NO_RETURN
|
||||||
|
#define __NO_RETURN __declspec(noreturn)
|
||||||
|
#endif
|
||||||
|
#ifndef __USED
|
||||||
|
#define __USED __attribute__((used))
|
||||||
|
#endif
|
||||||
|
#ifndef __WEAK
|
||||||
|
#define __WEAK __attribute__((weak))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED
|
||||||
|
#define __PACKED __attribute__((packed))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_STRUCT
|
||||||
|
#define __PACKED_STRUCT __packed struct
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_UNION
|
||||||
|
#define __PACKED_UNION __packed union
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
|
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
|
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
|
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
|
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
|
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
|
||||||
|
#endif
|
||||||
|
#ifndef __ALIGNED
|
||||||
|
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||||
|
#endif
|
||||||
|
#ifndef __RESTRICT
|
||||||
|
#define __RESTRICT __restrict
|
||||||
|
#endif
|
||||||
|
#ifndef __COMPILER_BARRIER
|
||||||
|
#define __COMPILER_BARRIER() __memory_changed()
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* ######################### Startup and Lowlevel Init ######################## */
|
||||||
|
|
||||||
|
#ifndef __PROGRAM_START
|
||||||
|
#define __PROGRAM_START __main
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __INITIAL_SP
|
||||||
|
#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __STACK_LIMIT
|
||||||
|
#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __VECTOR_TABLE
|
||||||
|
#define __VECTOR_TABLE __Vectors
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __VECTOR_TABLE_ATTRIBUTE
|
||||||
|
#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET")))
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* ########################### Core Function Access ########################### */
|
||||||
|
/** \ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Enable IRQ Interrupts
|
||||||
|
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||||||
|
Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
|
/* intrinsic void __enable_irq(); */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable IRQ Interrupts
|
||||||
|
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||||
|
Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
|
/* intrinsic void __disable_irq(); */
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Control Register
|
||||||
|
\details Returns the content of the Control Register.
|
||||||
|
\return Control Register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regControl __ASM("control");
|
||||||
|
return(__regControl);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Control Register
|
||||||
|
\details Writes the given value to the Control Register.
|
||||||
|
\param [in] control Control Register value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||||
|
{
|
||||||
|
register uint32_t __regControl __ASM("control");
|
||||||
|
__regControl = control;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get IPSR Register
|
||||||
|
\details Returns the content of the IPSR Register.
|
||||||
|
\return IPSR Register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_IPSR(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regIPSR __ASM("ipsr");
|
||||||
|
return(__regIPSR);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get APSR Register
|
||||||
|
\details Returns the content of the APSR Register.
|
||||||
|
\return APSR Register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regAPSR __ASM("apsr");
|
||||||
|
return(__regAPSR);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get xPSR Register
|
||||||
|
\details Returns the content of the xPSR Register.
|
||||||
|
\return xPSR Register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_xPSR(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regXPSR __ASM("xpsr");
|
||||||
|
return(__regXPSR);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Process Stack Pointer
|
||||||
|
\details Returns the current value of the Process Stack Pointer (PSP).
|
||||||
|
\return PSP Register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_PSP(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||||
|
return(__regProcessStackPointer);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Process Stack Pointer
|
||||||
|
\details Assigns the given value to the Process Stack Pointer (PSP).
|
||||||
|
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||||
|
{
|
||||||
|
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||||
|
__regProcessStackPointer = topOfProcStack;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Main Stack Pointer
|
||||||
|
\details Returns the current value of the Main Stack Pointer (MSP).
|
||||||
|
\return MSP Register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_MSP(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regMainStackPointer __ASM("msp");
|
||||||
|
return(__regMainStackPointer);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Main Stack Pointer
|
||||||
|
\details Assigns the given value to the Main Stack Pointer (MSP).
|
||||||
|
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||||
|
{
|
||||||
|
register uint32_t __regMainStackPointer __ASM("msp");
|
||||||
|
__regMainStackPointer = topOfMainStack;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Priority Mask
|
||||||
|
\details Returns the current state of the priority mask bit from the Priority Mask Register.
|
||||||
|
\return Priority Mask value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regPriMask __ASM("primask");
|
||||||
|
return(__regPriMask);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Priority Mask
|
||||||
|
\details Assigns the given value to the Priority Mask Register.
|
||||||
|
\param [in] priMask Priority Mask
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||||
|
{
|
||||||
|
register uint32_t __regPriMask __ASM("primask");
|
||||||
|
__regPriMask = (priMask);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Enable FIQ
|
||||||
|
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||||
|
Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
|
#define __enable_fault_irq __enable_fiq
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable FIQ
|
||||||
|
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||||
|
Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
|
#define __disable_fault_irq __disable_fiq
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Base Priority
|
||||||
|
\details Returns the current value of the Base Priority register.
|
||||||
|
\return Base Priority register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regBasePri __ASM("basepri");
|
||||||
|
return(__regBasePri);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Base Priority
|
||||||
|
\details Assigns the given value to the Base Priority register.
|
||||||
|
\param [in] basePri Base Priority value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
|
||||||
|
{
|
||||||
|
register uint32_t __regBasePri __ASM("basepri");
|
||||||
|
__regBasePri = (basePri & 0xFFU);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Base Priority with condition
|
||||||
|
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
|
||||||
|
or the new value increases the BASEPRI priority level.
|
||||||
|
\param [in] basePri Base Priority value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
|
||||||
|
{
|
||||||
|
register uint32_t __regBasePriMax __ASM("basepri_max");
|
||||||
|
__regBasePriMax = (basePri & 0xFFU);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Fault Mask
|
||||||
|
\details Returns the current value of the Fault Mask register.
|
||||||
|
\return Fault Mask register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regFaultMask __ASM("faultmask");
|
||||||
|
return(__regFaultMask);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Fault Mask
|
||||||
|
\details Assigns the given value to the Fault Mask register.
|
||||||
|
\param [in] faultMask Fault Mask value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||||
|
{
|
||||||
|
register uint32_t __regFaultMask __ASM("faultmask");
|
||||||
|
__regFaultMask = (faultMask & (uint32_t)1U);
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get FPSCR
|
||||||
|
\details Returns the current value of the Floating Point Status/Control register.
|
||||||
|
\return Floating Point Status/Control register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||||
|
{
|
||||||
|
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||||
|
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||||
|
register uint32_t __regfpscr __ASM("fpscr");
|
||||||
|
return(__regfpscr);
|
||||||
|
#else
|
||||||
|
return(0U);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set FPSCR
|
||||||
|
\details Assigns the given value to the Floating Point Status/Control register.
|
||||||
|
\param [in] fpscr Floating Point Status/Control value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||||
|
{
|
||||||
|
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||||
|
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||||
|
register uint32_t __regfpscr __ASM("fpscr");
|
||||||
|
__regfpscr = (fpscr);
|
||||||
|
#else
|
||||||
|
(void)fpscr;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
/* ########################## Core Instruction Access ######################### */
|
||||||
|
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||||
|
Access to dedicated instructions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief No Operation
|
||||||
|
\details No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||||
|
*/
|
||||||
|
#define __NOP __nop
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Wait For Interrupt
|
||||||
|
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
|
||||||
|
*/
|
||||||
|
#define __WFI __wfi
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Wait For Event
|
||||||
|
\details Wait For Event is a hint instruction that permits the processor to enter
|
||||||
|
a low-power state until one of a number of events occurs.
|
||||||
|
*/
|
||||||
|
#define __WFE __wfe
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Send Event
|
||||||
|
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||||
|
*/
|
||||||
|
#define __SEV __sev
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Instruction Synchronization Barrier
|
||||||
|
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||||
|
so that all instructions following the ISB are fetched from cache or memory,
|
||||||
|
after the instruction has been completed.
|
||||||
|
*/
|
||||||
|
#define __ISB() do {\
|
||||||
|
__schedule_barrier();\
|
||||||
|
__isb(0xF);\
|
||||||
|
__schedule_barrier();\
|
||||||
|
} while (0U)
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Data Synchronization Barrier
|
||||||
|
\details Acts as a special kind of Data Memory Barrier.
|
||||||
|
It completes when all explicit memory accesses before this instruction complete.
|
||||||
|
*/
|
||||||
|
#define __DSB() do {\
|
||||||
|
__schedule_barrier();\
|
||||||
|
__dsb(0xF);\
|
||||||
|
__schedule_barrier();\
|
||||||
|
} while (0U)
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Data Memory Barrier
|
||||||
|
\details Ensures the apparent order of the explicit memory operations before
|
||||||
|
and after the instruction, without ensuring their completion.
|
||||||
|
*/
|
||||||
|
#define __DMB() do {\
|
||||||
|
__schedule_barrier();\
|
||||||
|
__dmb(0xF);\
|
||||||
|
__schedule_barrier();\
|
||||||
|
} while (0U)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Reverse byte order (32 bit)
|
||||||
|
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
|
||||||
|
\param [in] value Value to reverse
|
||||||
|
\return Reversed value
|
||||||
|
*/
|
||||||
|
#define __REV __rev
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Reverse byte order (16 bit)
|
||||||
|
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
|
||||||
|
\param [in] value Value to reverse
|
||||||
|
\return Reversed value
|
||||||
|
*/
|
||||||
|
#ifndef __NO_EMBEDDED_ASM
|
||||||
|
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||||
|
{
|
||||||
|
rev16 r0, r0
|
||||||
|
bx lr
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Reverse byte order (16 bit)
|
||||||
|
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
|
||||||
|
\param [in] value Value to reverse
|
||||||
|
\return Reversed value
|
||||||
|
*/
|
||||||
|
#ifndef __NO_EMBEDDED_ASM
|
||||||
|
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
|
||||||
|
{
|
||||||
|
revsh r0, r0
|
||||||
|
bx lr
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Rotate Right in unsigned value (32 bit)
|
||||||
|
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||||
|
\param [in] op1 Value to rotate
|
||||||
|
\param [in] op2 Number of Bits to rotate
|
||||||
|
\return Rotated value
|
||||||
|
*/
|
||||||
|
#define __ROR __ror
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Breakpoint
|
||||||
|
\details Causes the processor to enter Debug state.
|
||||||
|
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||||
|
\param [in] value is ignored by the processor.
|
||||||
|
If required, a debugger can use it to store additional information about the breakpoint.
|
||||||
|
*/
|
||||||
|
#define __BKPT(value) __breakpoint(value)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Reverse bit order of value
|
||||||
|
\details Reverses the bit order of the given value.
|
||||||
|
\param [in] value Value to reverse
|
||||||
|
\return Reversed value
|
||||||
|
*/
|
||||||
|
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||||
|
#define __RBIT __rbit
|
||||||
|
#else
|
||||||
|
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
|
||||||
|
|
||||||
|
result = value; /* r will be reversed bits of v; first get LSB of v */
|
||||||
|
for (value >>= 1U; value != 0U; value >>= 1U)
|
||||||
|
{
|
||||||
|
result <<= 1U;
|
||||||
|
result |= value & 1U;
|
||||||
|
s--;
|
||||||
|
}
|
||||||
|
result <<= s; /* shift when v's highest bits are zero */
|
||||||
|
return result;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Count leading zeros
|
||||||
|
\details Counts the number of leading zeros of a data value.
|
||||||
|
\param [in] value Value to count the leading zeros
|
||||||
|
\return number of leading zeros in value
|
||||||
|
*/
|
||||||
|
#define __CLZ __clz
|
||||||
|
|
||||||
|
|
||||||
|
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief LDR Exclusive (8 bit)
|
||||||
|
\details Executes a exclusive LDR instruction for 8 bit value.
|
||||||
|
\param [in] ptr Pointer to data
|
||||||
|
\return value of type uint8_t at (*ptr)
|
||||||
|
*/
|
||||||
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||||
|
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
||||||
|
#else
|
||||||
|
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief LDR Exclusive (16 bit)
|
||||||
|
\details Executes a exclusive LDR instruction for 16 bit values.
|
||||||
|
\param [in] ptr Pointer to data
|
||||||
|
\return value of type uint16_t at (*ptr)
|
||||||
|
*/
|
||||||
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||||
|
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||||
|
#else
|
||||||
|
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief LDR Exclusive (32 bit)
|
||||||
|
\details Executes a exclusive LDR instruction for 32 bit values.
|
||||||
|
\param [in] ptr Pointer to data
|
||||||
|
\return value of type uint32_t at (*ptr)
|
||||||
|
*/
|
||||||
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||||
|
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||||
|
#else
|
||||||
|
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief STR Exclusive (8 bit)
|
||||||
|
\details Executes a exclusive STR instruction for 8 bit values.
|
||||||
|
\param [in] value Value to store
|
||||||
|
\param [in] ptr Pointer to location
|
||||||
|
\return 0 Function succeeded
|
||||||
|
\return 1 Function failed
|
||||||
|
*/
|
||||||
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||||
|
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||||
|
#else
|
||||||
|
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief STR Exclusive (16 bit)
|
||||||
|
\details Executes a exclusive STR instruction for 16 bit values.
|
||||||
|
\param [in] value Value to store
|
||||||
|
\param [in] ptr Pointer to location
|
||||||
|
\return 0 Function succeeded
|
||||||
|
\return 1 Function failed
|
||||||
|
*/
|
||||||
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||||
|
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||||
|
#else
|
||||||
|
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief STR Exclusive (32 bit)
|
||||||
|
\details Executes a exclusive STR instruction for 32 bit values.
|
||||||
|
\param [in] value Value to store
|
||||||
|
\param [in] ptr Pointer to location
|
||||||
|
\return 0 Function succeeded
|
||||||
|
\return 1 Function failed
|
||||||
|
*/
|
||||||
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||||
|
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||||
|
#else
|
||||||
|
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Remove the exclusive lock
|
||||||
|
\details Removes the exclusive lock which is created by LDREX.
|
||||||
|
*/
|
||||||
|
#define __CLREX __clrex
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Signed Saturate
|
||||||
|
\details Saturates a signed value.
|
||||||
|
\param [in] value Value to be saturated
|
||||||
|
\param [in] sat Bit position to saturate to (1..32)
|
||||||
|
\return Saturated value
|
||||||
|
*/
|
||||||
|
#define __SSAT __ssat
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Unsigned Saturate
|
||||||
|
\details Saturates an unsigned value.
|
||||||
|
\param [in] value Value to be saturated
|
||||||
|
\param [in] sat Bit position to saturate to (0..31)
|
||||||
|
\return Saturated value
|
||||||
|
*/
|
||||||
|
#define __USAT __usat
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Rotate Right with Extend (32 bit)
|
||||||
|
\details Moves each bit of a bitstring right by one bit.
|
||||||
|
The carry input is shifted in at the left end of the bitstring.
|
||||||
|
\param [in] value Value to rotate
|
||||||
|
\return Rotated value
|
||||||
|
*/
|
||||||
|
#ifndef __NO_EMBEDDED_ASM
|
||||||
|
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
|
||||||
|
{
|
||||||
|
rrx r0, r0
|
||||||
|
bx lr
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief LDRT Unprivileged (8 bit)
|
||||||
|
\details Executes a Unprivileged LDRT instruction for 8 bit value.
|
||||||
|
\param [in] ptr Pointer to data
|
||||||
|
\return value of type uint8_t at (*ptr)
|
||||||
|
*/
|
||||||
|
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief LDRT Unprivileged (16 bit)
|
||||||
|
\details Executes a Unprivileged LDRT instruction for 16 bit values.
|
||||||
|
\param [in] ptr Pointer to data
|
||||||
|
\return value of type uint16_t at (*ptr)
|
||||||
|
*/
|
||||||
|
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief LDRT Unprivileged (32 bit)
|
||||||
|
\details Executes a Unprivileged LDRT instruction for 32 bit values.
|
||||||
|
\param [in] ptr Pointer to data
|
||||||
|
\return value of type uint32_t at (*ptr)
|
||||||
|
*/
|
||||||
|
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief STRT Unprivileged (8 bit)
|
||||||
|
\details Executes a Unprivileged STRT instruction for 8 bit values.
|
||||||
|
\param [in] value Value to store
|
||||||
|
\param [in] ptr Pointer to location
|
||||||
|
*/
|
||||||
|
#define __STRBT(value, ptr) __strt(value, ptr)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief STRT Unprivileged (16 bit)
|
||||||
|
\details Executes a Unprivileged STRT instruction for 16 bit values.
|
||||||
|
\param [in] value Value to store
|
||||||
|
\param [in] ptr Pointer to location
|
||||||
|
*/
|
||||||
|
#define __STRHT(value, ptr) __strt(value, ptr)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief STRT Unprivileged (32 bit)
|
||||||
|
\details Executes a Unprivileged STRT instruction for 32 bit values.
|
||||||
|
\param [in] value Value to store
|
||||||
|
\param [in] ptr Pointer to location
|
||||||
|
*/
|
||||||
|
#define __STRT(value, ptr) __strt(value, ptr)
|
||||||
|
|
||||||
|
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Signed Saturate
|
||||||
|
\details Saturates a signed value.
|
||||||
|
\param [in] value Value to be saturated
|
||||||
|
\param [in] sat Bit position to saturate to (1..32)
|
||||||
|
\return Saturated value
|
||||||
|
*/
|
||||||
|
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||||
|
{
|
||||||
|
if ((sat >= 1U) && (sat <= 32U))
|
||||||
|
{
|
||||||
|
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||||
|
const int32_t min = -1 - max ;
|
||||||
|
if (val > max)
|
||||||
|
{
|
||||||
|
return max;
|
||||||
|
}
|
||||||
|
else if (val < min)
|
||||||
|
{
|
||||||
|
return min;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return val;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Unsigned Saturate
|
||||||
|
\details Saturates an unsigned value.
|
||||||
|
\param [in] value Value to be saturated
|
||||||
|
\param [in] sat Bit position to saturate to (0..31)
|
||||||
|
\return Saturated value
|
||||||
|
*/
|
||||||
|
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||||
|
{
|
||||||
|
if (sat <= 31U)
|
||||||
|
{
|
||||||
|
const uint32_t max = ((1U << sat) - 1U);
|
||||||
|
if (val > (int32_t)max)
|
||||||
|
{
|
||||||
|
return max;
|
||||||
|
}
|
||||||
|
else if (val < 0)
|
||||||
|
{
|
||||||
|
return 0U;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return (uint32_t)val;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||||
|
|
||||||
|
|
||||||
|
/* ################### Compiler specific Intrinsics ########################### */
|
||||||
|
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||||
|
Access to dedicated SIMD instructions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||||
|
|
||||||
|
#define __SADD8 __sadd8
|
||||||
|
#define __QADD8 __qadd8
|
||||||
|
#define __SHADD8 __shadd8
|
||||||
|
#define __UADD8 __uadd8
|
||||||
|
#define __UQADD8 __uqadd8
|
||||||
|
#define __UHADD8 __uhadd8
|
||||||
|
#define __SSUB8 __ssub8
|
||||||
|
#define __QSUB8 __qsub8
|
||||||
|
#define __SHSUB8 __shsub8
|
||||||
|
#define __USUB8 __usub8
|
||||||
|
#define __UQSUB8 __uqsub8
|
||||||
|
#define __UHSUB8 __uhsub8
|
||||||
|
#define __SADD16 __sadd16
|
||||||
|
#define __QADD16 __qadd16
|
||||||
|
#define __SHADD16 __shadd16
|
||||||
|
#define __UADD16 __uadd16
|
||||||
|
#define __UQADD16 __uqadd16
|
||||||
|
#define __UHADD16 __uhadd16
|
||||||
|
#define __SSUB16 __ssub16
|
||||||
|
#define __QSUB16 __qsub16
|
||||||
|
#define __SHSUB16 __shsub16
|
||||||
|
#define __USUB16 __usub16
|
||||||
|
#define __UQSUB16 __uqsub16
|
||||||
|
#define __UHSUB16 __uhsub16
|
||||||
|
#define __SASX __sasx
|
||||||
|
#define __QASX __qasx
|
||||||
|
#define __SHASX __shasx
|
||||||
|
#define __UASX __uasx
|
||||||
|
#define __UQASX __uqasx
|
||||||
|
#define __UHASX __uhasx
|
||||||
|
#define __SSAX __ssax
|
||||||
|
#define __QSAX __qsax
|
||||||
|
#define __SHSAX __shsax
|
||||||
|
#define __USAX __usax
|
||||||
|
#define __UQSAX __uqsax
|
||||||
|
#define __UHSAX __uhsax
|
||||||
|
#define __USAD8 __usad8
|
||||||
|
#define __USADA8 __usada8
|
||||||
|
#define __SSAT16 __ssat16
|
||||||
|
#define __USAT16 __usat16
|
||||||
|
#define __UXTB16 __uxtb16
|
||||||
|
#define __UXTAB16 __uxtab16
|
||||||
|
#define __SXTB16 __sxtb16
|
||||||
|
#define __SXTAB16 __sxtab16
|
||||||
|
#define __SMUAD __smuad
|
||||||
|
#define __SMUADX __smuadx
|
||||||
|
#define __SMLAD __smlad
|
||||||
|
#define __SMLADX __smladx
|
||||||
|
#define __SMLALD __smlald
|
||||||
|
#define __SMLALDX __smlaldx
|
||||||
|
#define __SMUSD __smusd
|
||||||
|
#define __SMUSDX __smusdx
|
||||||
|
#define __SMLSD __smlsd
|
||||||
|
#define __SMLSDX __smlsdx
|
||||||
|
#define __SMLSLD __smlsld
|
||||||
|
#define __SMLSLDX __smlsldx
|
||||||
|
#define __SEL __sel
|
||||||
|
#define __QADD __qadd
|
||||||
|
#define __QSUB __qsub
|
||||||
|
|
||||||
|
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
|
||||||
|
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|
||||||
|
|
||||||
|
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
||||||
|
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
||||||
|
|
||||||
|
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
||||||
|
((int64_t)(ARG3) << 32U) ) >> 32U))
|
||||||
|
|
||||||
|
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||||
|
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* __CMSIS_ARMCC_H */
|
||||||
1444
Boot/Drivers/CMSIS/Include/cmsis_armclang.h
Normal file
1444
Boot/Drivers/CMSIS/Include/cmsis_armclang.h
Normal file
File diff suppressed because it is too large
Load Diff
1891
Boot/Drivers/CMSIS/Include/cmsis_armclang_ltm.h
Normal file
1891
Boot/Drivers/CMSIS/Include/cmsis_armclang_ltm.h
Normal file
File diff suppressed because it is too large
Load Diff
283
Boot/Drivers/CMSIS/Include/cmsis_compiler.h
Normal file
283
Boot/Drivers/CMSIS/Include/cmsis_compiler.h
Normal file
@@ -0,0 +1,283 @@
|
|||||||
|
/**************************************************************************//**
|
||||||
|
* @file cmsis_compiler.h
|
||||||
|
* @brief CMSIS compiler generic header file
|
||||||
|
* @version V5.1.0
|
||||||
|
* @date 09. October 2018
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CMSIS_COMPILER_H
|
||||||
|
#define __CMSIS_COMPILER_H
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Arm Compiler 4/5
|
||||||
|
*/
|
||||||
|
#if defined ( __CC_ARM )
|
||||||
|
#include "cmsis_armcc.h"
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Arm Compiler 6.6 LTM (armclang)
|
||||||
|
*/
|
||||||
|
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
|
||||||
|
#include "cmsis_armclang_ltm.h"
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Arm Compiler above 6.10.1 (armclang)
|
||||||
|
*/
|
||||||
|
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
|
||||||
|
#include "cmsis_armclang.h"
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* GNU Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __GNUC__ )
|
||||||
|
#include "cmsis_gcc.h"
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* IAR Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __ICCARM__ )
|
||||||
|
#include <cmsis_iccarm.h>
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* TI Arm Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __TI_ARM__ )
|
||||||
|
#include <cmsis_ccs.h>
|
||||||
|
|
||||||
|
#ifndef __ASM
|
||||||
|
#define __ASM __asm
|
||||||
|
#endif
|
||||||
|
#ifndef __INLINE
|
||||||
|
#define __INLINE inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_INLINE
|
||||||
|
#define __STATIC_INLINE static inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_FORCEINLINE
|
||||||
|
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||||
|
#endif
|
||||||
|
#ifndef __NO_RETURN
|
||||||
|
#define __NO_RETURN __attribute__((noreturn))
|
||||||
|
#endif
|
||||||
|
#ifndef __USED
|
||||||
|
#define __USED __attribute__((used))
|
||||||
|
#endif
|
||||||
|
#ifndef __WEAK
|
||||||
|
#define __WEAK __attribute__((weak))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED
|
||||||
|
#define __PACKED __attribute__((packed))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_STRUCT
|
||||||
|
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_UNION
|
||||||
|
#define __PACKED_UNION union __attribute__((packed))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
|
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
|
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
|
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __ALIGNED
|
||||||
|
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||||
|
#endif
|
||||||
|
#ifndef __RESTRICT
|
||||||
|
#define __RESTRICT __restrict
|
||||||
|
#endif
|
||||||
|
#ifndef __COMPILER_BARRIER
|
||||||
|
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||||
|
#define __COMPILER_BARRIER() (void)0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* TASKING Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __TASKING__ )
|
||||||
|
/*
|
||||||
|
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||||
|
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||||
|
* Including the CMSIS ones.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __ASM
|
||||||
|
#define __ASM __asm
|
||||||
|
#endif
|
||||||
|
#ifndef __INLINE
|
||||||
|
#define __INLINE inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_INLINE
|
||||||
|
#define __STATIC_INLINE static inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_FORCEINLINE
|
||||||
|
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||||
|
#endif
|
||||||
|
#ifndef __NO_RETURN
|
||||||
|
#define __NO_RETURN __attribute__((noreturn))
|
||||||
|
#endif
|
||||||
|
#ifndef __USED
|
||||||
|
#define __USED __attribute__((used))
|
||||||
|
#endif
|
||||||
|
#ifndef __WEAK
|
||||||
|
#define __WEAK __attribute__((weak))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED
|
||||||
|
#define __PACKED __packed__
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_STRUCT
|
||||||
|
#define __PACKED_STRUCT struct __packed__
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_UNION
|
||||||
|
#define __PACKED_UNION union __packed__
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
|
struct __packed__ T_UINT32 { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
|
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
|
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __ALIGNED
|
||||||
|
#define __ALIGNED(x) __align(x)
|
||||||
|
#endif
|
||||||
|
#ifndef __RESTRICT
|
||||||
|
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||||
|
#define __RESTRICT
|
||||||
|
#endif
|
||||||
|
#ifndef __COMPILER_BARRIER
|
||||||
|
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||||
|
#define __COMPILER_BARRIER() (void)0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* COSMIC Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __CSMC__ )
|
||||||
|
#include <cmsis_csm.h>
|
||||||
|
|
||||||
|
#ifndef __ASM
|
||||||
|
#define __ASM _asm
|
||||||
|
#endif
|
||||||
|
#ifndef __INLINE
|
||||||
|
#define __INLINE inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_INLINE
|
||||||
|
#define __STATIC_INLINE static inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_FORCEINLINE
|
||||||
|
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||||
|
#endif
|
||||||
|
#ifndef __NO_RETURN
|
||||||
|
// NO RETURN is automatically detected hence no warning here
|
||||||
|
#define __NO_RETURN
|
||||||
|
#endif
|
||||||
|
#ifndef __USED
|
||||||
|
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||||
|
#define __USED
|
||||||
|
#endif
|
||||||
|
#ifndef __WEAK
|
||||||
|
#define __WEAK __weak
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED
|
||||||
|
#define __PACKED @packed
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_STRUCT
|
||||||
|
#define __PACKED_STRUCT @packed struct
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_UNION
|
||||||
|
#define __PACKED_UNION @packed union
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
|
@packed struct T_UINT32 { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
|
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
|
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __ALIGNED
|
||||||
|
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||||
|
#define __ALIGNED(x)
|
||||||
|
#endif
|
||||||
|
#ifndef __RESTRICT
|
||||||
|
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||||
|
#define __RESTRICT
|
||||||
|
#endif
|
||||||
|
#ifndef __COMPILER_BARRIER
|
||||||
|
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||||
|
#define __COMPILER_BARRIER() (void)0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#else
|
||||||
|
#error Unknown compiler.
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* __CMSIS_COMPILER_H */
|
||||||
|
|
||||||
2168
Boot/Drivers/CMSIS/Include/cmsis_gcc.h
Normal file
2168
Boot/Drivers/CMSIS/Include/cmsis_gcc.h
Normal file
File diff suppressed because it is too large
Load Diff
964
Boot/Drivers/CMSIS/Include/cmsis_iccarm.h
Normal file
964
Boot/Drivers/CMSIS/Include/cmsis_iccarm.h
Normal file
@@ -0,0 +1,964 @@
|
|||||||
|
/**************************************************************************//**
|
||||||
|
* @file cmsis_iccarm.h
|
||||||
|
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
|
||||||
|
* @version V5.1.0
|
||||||
|
* @date 08. May 2019
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
//------------------------------------------------------------------------------
|
||||||
|
//
|
||||||
|
// Copyright (c) 2017-2019 IAR Systems
|
||||||
|
// Copyright (c) 2017-2019 Arm Limited. All rights reserved.
|
||||||
|
//
|
||||||
|
// Licensed under the Apache License, Version 2.0 (the "License")
|
||||||
|
// you may not use this file except in compliance with the License.
|
||||||
|
// You may obtain a copy of the License at
|
||||||
|
// http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
//
|
||||||
|
// Unless required by applicable law or agreed to in writing, software
|
||||||
|
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
// See the License for the specific language governing permissions and
|
||||||
|
// limitations under the License.
|
||||||
|
//
|
||||||
|
//------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef __CMSIS_ICCARM_H__
|
||||||
|
#define __CMSIS_ICCARM_H__
|
||||||
|
|
||||||
|
#ifndef __ICCARM__
|
||||||
|
#error This file should only be compiled by ICCARM
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#pragma system_include
|
||||||
|
|
||||||
|
#define __IAR_FT _Pragma("inline=forced") __intrinsic
|
||||||
|
|
||||||
|
#if (__VER__ >= 8000000)
|
||||||
|
#define __ICCARM_V8 1
|
||||||
|
#else
|
||||||
|
#define __ICCARM_V8 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __ALIGNED
|
||||||
|
#if __ICCARM_V8
|
||||||
|
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||||
|
#elif (__VER__ >= 7080000)
|
||||||
|
/* Needs IAR language extensions */
|
||||||
|
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||||
|
#else
|
||||||
|
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
|
||||||
|
#define __ALIGNED(x)
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/* Define compiler macros for CPU architecture, used in CMSIS 5.
|
||||||
|
*/
|
||||||
|
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
|
||||||
|
/* Macros already defined */
|
||||||
|
#else
|
||||||
|
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
|
||||||
|
#define __ARM_ARCH_8M_MAIN__ 1
|
||||||
|
#elif defined(__ARM8M_BASELINE__)
|
||||||
|
#define __ARM_ARCH_8M_BASE__ 1
|
||||||
|
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
|
||||||
|
#if __ARM_ARCH == 6
|
||||||
|
#define __ARM_ARCH_6M__ 1
|
||||||
|
#elif __ARM_ARCH == 7
|
||||||
|
#if __ARM_FEATURE_DSP
|
||||||
|
#define __ARM_ARCH_7EM__ 1
|
||||||
|
#else
|
||||||
|
#define __ARM_ARCH_7M__ 1
|
||||||
|
#endif
|
||||||
|
#endif /* __ARM_ARCH */
|
||||||
|
#endif /* __ARM_ARCH_PROFILE == 'M' */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Alternativ core deduction for older ICCARM's */
|
||||||
|
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
|
||||||
|
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
|
||||||
|
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
|
||||||
|
#define __ARM_ARCH_6M__ 1
|
||||||
|
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
|
||||||
|
#define __ARM_ARCH_7M__ 1
|
||||||
|
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
|
||||||
|
#define __ARM_ARCH_7EM__ 1
|
||||||
|
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
|
||||||
|
#define __ARM_ARCH_8M_BASE__ 1
|
||||||
|
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
|
||||||
|
#define __ARM_ARCH_8M_MAIN__ 1
|
||||||
|
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
|
||||||
|
#define __ARM_ARCH_8M_MAIN__ 1
|
||||||
|
#else
|
||||||
|
#error "Unknown target."
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
|
||||||
|
#define __IAR_M0_FAMILY 1
|
||||||
|
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
|
||||||
|
#define __IAR_M0_FAMILY 1
|
||||||
|
#else
|
||||||
|
#define __IAR_M0_FAMILY 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef __ASM
|
||||||
|
#define __ASM __asm
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __COMPILER_BARRIER
|
||||||
|
#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __INLINE
|
||||||
|
#define __INLINE inline
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __NO_RETURN
|
||||||
|
#if __ICCARM_V8
|
||||||
|
#define __NO_RETURN __attribute__((__noreturn__))
|
||||||
|
#else
|
||||||
|
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __PACKED
|
||||||
|
#if __ICCARM_V8
|
||||||
|
#define __PACKED __attribute__((packed, aligned(1)))
|
||||||
|
#else
|
||||||
|
/* Needs IAR language extensions */
|
||||||
|
#define __PACKED __packed
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __PACKED_STRUCT
|
||||||
|
#if __ICCARM_V8
|
||||||
|
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
|
||||||
|
#else
|
||||||
|
/* Needs IAR language extensions */
|
||||||
|
#define __PACKED_STRUCT __packed struct
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __PACKED_UNION
|
||||||
|
#if __ICCARM_V8
|
||||||
|
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
|
||||||
|
#else
|
||||||
|
/* Needs IAR language extensions */
|
||||||
|
#define __PACKED_UNION __packed union
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __RESTRICT
|
||||||
|
#if __ICCARM_V8
|
||||||
|
#define __RESTRICT __restrict
|
||||||
|
#else
|
||||||
|
/* Needs IAR language extensions */
|
||||||
|
#define __RESTRICT restrict
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __STATIC_INLINE
|
||||||
|
#define __STATIC_INLINE static inline
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __FORCEINLINE
|
||||||
|
#define __FORCEINLINE _Pragma("inline=forced")
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __STATIC_FORCEINLINE
|
||||||
|
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
|
#pragma language=save
|
||||||
|
#pragma language=extended
|
||||||
|
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
|
||||||
|
{
|
||||||
|
return *(__packed uint16_t*)(ptr);
|
||||||
|
}
|
||||||
|
#pragma language=restore
|
||||||
|
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
|
#pragma language=save
|
||||||
|
#pragma language=extended
|
||||||
|
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
|
||||||
|
{
|
||||||
|
*(__packed uint16_t*)(ptr) = val;;
|
||||||
|
}
|
||||||
|
#pragma language=restore
|
||||||
|
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
|
#pragma language=save
|
||||||
|
#pragma language=extended
|
||||||
|
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
|
||||||
|
{
|
||||||
|
return *(__packed uint32_t*)(ptr);
|
||||||
|
}
|
||||||
|
#pragma language=restore
|
||||||
|
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
|
#pragma language=save
|
||||||
|
#pragma language=extended
|
||||||
|
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
|
||||||
|
{
|
||||||
|
*(__packed uint32_t*)(ptr) = val;;
|
||||||
|
}
|
||||||
|
#pragma language=restore
|
||||||
|
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
|
#pragma language=save
|
||||||
|
#pragma language=extended
|
||||||
|
__packed struct __iar_u32 { uint32_t v; };
|
||||||
|
#pragma language=restore
|
||||||
|
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __USED
|
||||||
|
#if __ICCARM_V8
|
||||||
|
#define __USED __attribute__((used))
|
||||||
|
#else
|
||||||
|
#define __USED _Pragma("__root")
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __WEAK
|
||||||
|
#if __ICCARM_V8
|
||||||
|
#define __WEAK __attribute__((weak))
|
||||||
|
#else
|
||||||
|
#define __WEAK _Pragma("__weak")
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __PROGRAM_START
|
||||||
|
#define __PROGRAM_START __iar_program_start
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __INITIAL_SP
|
||||||
|
#define __INITIAL_SP CSTACK$$Limit
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __STACK_LIMIT
|
||||||
|
#define __STACK_LIMIT CSTACK$$Base
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __VECTOR_TABLE
|
||||||
|
#define __VECTOR_TABLE __vector_table
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __VECTOR_TABLE_ATTRIBUTE
|
||||||
|
#define __VECTOR_TABLE_ATTRIBUTE @".intvec"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __ICCARM_INTRINSICS_VERSION__
|
||||||
|
#define __ICCARM_INTRINSICS_VERSION__ 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if __ICCARM_INTRINSICS_VERSION__ == 2
|
||||||
|
|
||||||
|
#if defined(__CLZ)
|
||||||
|
#undef __CLZ
|
||||||
|
#endif
|
||||||
|
#if defined(__REVSH)
|
||||||
|
#undef __REVSH
|
||||||
|
#endif
|
||||||
|
#if defined(__RBIT)
|
||||||
|
#undef __RBIT
|
||||||
|
#endif
|
||||||
|
#if defined(__SSAT)
|
||||||
|
#undef __SSAT
|
||||||
|
#endif
|
||||||
|
#if defined(__USAT)
|
||||||
|
#undef __USAT
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "iccarm_builtin.h"
|
||||||
|
|
||||||
|
#define __disable_fault_irq __iar_builtin_disable_fiq
|
||||||
|
#define __disable_irq __iar_builtin_disable_interrupt
|
||||||
|
#define __enable_fault_irq __iar_builtin_enable_fiq
|
||||||
|
#define __enable_irq __iar_builtin_enable_interrupt
|
||||||
|
#define __arm_rsr __iar_builtin_rsr
|
||||||
|
#define __arm_wsr __iar_builtin_wsr
|
||||||
|
|
||||||
|
|
||||||
|
#define __get_APSR() (__arm_rsr("APSR"))
|
||||||
|
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
|
||||||
|
#define __get_CONTROL() (__arm_rsr("CONTROL"))
|
||||||
|
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
|
||||||
|
|
||||||
|
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||||
|
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||||
|
#define __get_FPSCR() (__arm_rsr("FPSCR"))
|
||||||
|
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
|
||||||
|
#else
|
||||||
|
#define __get_FPSCR() ( 0 )
|
||||||
|
#define __set_FPSCR(VALUE) ((void)VALUE)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define __get_IPSR() (__arm_rsr("IPSR"))
|
||||||
|
#define __get_MSP() (__arm_rsr("MSP"))
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||||
|
#define __get_MSPLIM() (0U)
|
||||||
|
#else
|
||||||
|
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
|
||||||
|
#endif
|
||||||
|
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
|
||||||
|
#define __get_PSP() (__arm_rsr("PSP"))
|
||||||
|
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||||
|
#define __get_PSPLIM() (0U)
|
||||||
|
#else
|
||||||
|
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define __get_xPSR() (__arm_rsr("xPSR"))
|
||||||
|
|
||||||
|
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
|
||||||
|
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
|
||||||
|
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
|
||||||
|
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
|
||||||
|
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
|
||||||
|
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||||
|
#define __set_MSPLIM(VALUE) ((void)(VALUE))
|
||||||
|
#else
|
||||||
|
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
|
||||||
|
#endif
|
||||||
|
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
|
||||||
|
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||||
|
#define __set_PSPLIM(VALUE) ((void)(VALUE))
|
||||||
|
#else
|
||||||
|
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
|
||||||
|
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
|
||||||
|
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
|
||||||
|
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
|
||||||
|
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
|
||||||
|
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
|
||||||
|
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
|
||||||
|
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
|
||||||
|
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
|
||||||
|
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
|
||||||
|
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
|
||||||
|
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
|
||||||
|
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
|
||||||
|
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
|
||||||
|
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||||
|
#define __TZ_get_PSPLIM_NS() (0U)
|
||||||
|
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
|
||||||
|
#else
|
||||||
|
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
|
||||||
|
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
|
||||||
|
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
|
||||||
|
|
||||||
|
#define __NOP __iar_builtin_no_operation
|
||||||
|
|
||||||
|
#define __CLZ __iar_builtin_CLZ
|
||||||
|
#define __CLREX __iar_builtin_CLREX
|
||||||
|
|
||||||
|
#define __DMB __iar_builtin_DMB
|
||||||
|
#define __DSB __iar_builtin_DSB
|
||||||
|
#define __ISB __iar_builtin_ISB
|
||||||
|
|
||||||
|
#define __LDREXB __iar_builtin_LDREXB
|
||||||
|
#define __LDREXH __iar_builtin_LDREXH
|
||||||
|
#define __LDREXW __iar_builtin_LDREX
|
||||||
|
|
||||||
|
#define __RBIT __iar_builtin_RBIT
|
||||||
|
#define __REV __iar_builtin_REV
|
||||||
|
#define __REV16 __iar_builtin_REV16
|
||||||
|
|
||||||
|
__IAR_FT int16_t __REVSH(int16_t val)
|
||||||
|
{
|
||||||
|
return (int16_t) __iar_builtin_REVSH(val);
|
||||||
|
}
|
||||||
|
|
||||||
|
#define __ROR __iar_builtin_ROR
|
||||||
|
#define __RRX __iar_builtin_RRX
|
||||||
|
|
||||||
|
#define __SEV __iar_builtin_SEV
|
||||||
|
|
||||||
|
#if !__IAR_M0_FAMILY
|
||||||
|
#define __SSAT __iar_builtin_SSAT
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define __STREXB __iar_builtin_STREXB
|
||||||
|
#define __STREXH __iar_builtin_STREXH
|
||||||
|
#define __STREXW __iar_builtin_STREX
|
||||||
|
|
||||||
|
#if !__IAR_M0_FAMILY
|
||||||
|
#define __USAT __iar_builtin_USAT
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define __WFE __iar_builtin_WFE
|
||||||
|
#define __WFI __iar_builtin_WFI
|
||||||
|
|
||||||
|
#if __ARM_MEDIA__
|
||||||
|
#define __SADD8 __iar_builtin_SADD8
|
||||||
|
#define __QADD8 __iar_builtin_QADD8
|
||||||
|
#define __SHADD8 __iar_builtin_SHADD8
|
||||||
|
#define __UADD8 __iar_builtin_UADD8
|
||||||
|
#define __UQADD8 __iar_builtin_UQADD8
|
||||||
|
#define __UHADD8 __iar_builtin_UHADD8
|
||||||
|
#define __SSUB8 __iar_builtin_SSUB8
|
||||||
|
#define __QSUB8 __iar_builtin_QSUB8
|
||||||
|
#define __SHSUB8 __iar_builtin_SHSUB8
|
||||||
|
#define __USUB8 __iar_builtin_USUB8
|
||||||
|
#define __UQSUB8 __iar_builtin_UQSUB8
|
||||||
|
#define __UHSUB8 __iar_builtin_UHSUB8
|
||||||
|
#define __SADD16 __iar_builtin_SADD16
|
||||||
|
#define __QADD16 __iar_builtin_QADD16
|
||||||
|
#define __SHADD16 __iar_builtin_SHADD16
|
||||||
|
#define __UADD16 __iar_builtin_UADD16
|
||||||
|
#define __UQADD16 __iar_builtin_UQADD16
|
||||||
|
#define __UHADD16 __iar_builtin_UHADD16
|
||||||
|
#define __SSUB16 __iar_builtin_SSUB16
|
||||||
|
#define __QSUB16 __iar_builtin_QSUB16
|
||||||
|
#define __SHSUB16 __iar_builtin_SHSUB16
|
||||||
|
#define __USUB16 __iar_builtin_USUB16
|
||||||
|
#define __UQSUB16 __iar_builtin_UQSUB16
|
||||||
|
#define __UHSUB16 __iar_builtin_UHSUB16
|
||||||
|
#define __SASX __iar_builtin_SASX
|
||||||
|
#define __QASX __iar_builtin_QASX
|
||||||
|
#define __SHASX __iar_builtin_SHASX
|
||||||
|
#define __UASX __iar_builtin_UASX
|
||||||
|
#define __UQASX __iar_builtin_UQASX
|
||||||
|
#define __UHASX __iar_builtin_UHASX
|
||||||
|
#define __SSAX __iar_builtin_SSAX
|
||||||
|
#define __QSAX __iar_builtin_QSAX
|
||||||
|
#define __SHSAX __iar_builtin_SHSAX
|
||||||
|
#define __USAX __iar_builtin_USAX
|
||||||
|
#define __UQSAX __iar_builtin_UQSAX
|
||||||
|
#define __UHSAX __iar_builtin_UHSAX
|
||||||
|
#define __USAD8 __iar_builtin_USAD8
|
||||||
|
#define __USADA8 __iar_builtin_USADA8
|
||||||
|
#define __SSAT16 __iar_builtin_SSAT16
|
||||||
|
#define __USAT16 __iar_builtin_USAT16
|
||||||
|
#define __UXTB16 __iar_builtin_UXTB16
|
||||||
|
#define __UXTAB16 __iar_builtin_UXTAB16
|
||||||
|
#define __SXTB16 __iar_builtin_SXTB16
|
||||||
|
#define __SXTAB16 __iar_builtin_SXTAB16
|
||||||
|
#define __SMUAD __iar_builtin_SMUAD
|
||||||
|
#define __SMUADX __iar_builtin_SMUADX
|
||||||
|
#define __SMMLA __iar_builtin_SMMLA
|
||||||
|
#define __SMLAD __iar_builtin_SMLAD
|
||||||
|
#define __SMLADX __iar_builtin_SMLADX
|
||||||
|
#define __SMLALD __iar_builtin_SMLALD
|
||||||
|
#define __SMLALDX __iar_builtin_SMLALDX
|
||||||
|
#define __SMUSD __iar_builtin_SMUSD
|
||||||
|
#define __SMUSDX __iar_builtin_SMUSDX
|
||||||
|
#define __SMLSD __iar_builtin_SMLSD
|
||||||
|
#define __SMLSDX __iar_builtin_SMLSDX
|
||||||
|
#define __SMLSLD __iar_builtin_SMLSLD
|
||||||
|
#define __SMLSLDX __iar_builtin_SMLSLDX
|
||||||
|
#define __SEL __iar_builtin_SEL
|
||||||
|
#define __QADD __iar_builtin_QADD
|
||||||
|
#define __QSUB __iar_builtin_QSUB
|
||||||
|
#define __PKHBT __iar_builtin_PKHBT
|
||||||
|
#define __PKHTB __iar_builtin_PKHTB
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
|
||||||
|
|
||||||
|
#if __IAR_M0_FAMILY
|
||||||
|
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
|
||||||
|
#define __CLZ __cmsis_iar_clz_not_active
|
||||||
|
#define __SSAT __cmsis_iar_ssat_not_active
|
||||||
|
#define __USAT __cmsis_iar_usat_not_active
|
||||||
|
#define __RBIT __cmsis_iar_rbit_not_active
|
||||||
|
#define __get_APSR __cmsis_iar_get_APSR_not_active
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||||
|
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
|
||||||
|
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
|
||||||
|
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef __INTRINSICS_INCLUDED
|
||||||
|
#error intrinsics.h is already included previously!
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include <intrinsics.h>
|
||||||
|
|
||||||
|
#if __IAR_M0_FAMILY
|
||||||
|
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
|
||||||
|
#undef __CLZ
|
||||||
|
#undef __SSAT
|
||||||
|
#undef __USAT
|
||||||
|
#undef __RBIT
|
||||||
|
#undef __get_APSR
|
||||||
|
|
||||||
|
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
|
||||||
|
{
|
||||||
|
if (data == 0U) { return 32U; }
|
||||||
|
|
||||||
|
uint32_t count = 0U;
|
||||||
|
uint32_t mask = 0x80000000U;
|
||||||
|
|
||||||
|
while ((data & mask) == 0U)
|
||||||
|
{
|
||||||
|
count += 1U;
|
||||||
|
mask = mask >> 1U;
|
||||||
|
}
|
||||||
|
return count;
|
||||||
|
}
|
||||||
|
|
||||||
|
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
|
||||||
|
{
|
||||||
|
uint8_t sc = 31U;
|
||||||
|
uint32_t r = v;
|
||||||
|
for (v >>= 1U; v; v >>= 1U)
|
||||||
|
{
|
||||||
|
r <<= 1U;
|
||||||
|
r |= v & 1U;
|
||||||
|
sc--;
|
||||||
|
}
|
||||||
|
return (r << sc);
|
||||||
|
}
|
||||||
|
|
||||||
|
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm("MRS %0,APSR" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||||
|
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
|
||||||
|
#undef __get_FPSCR
|
||||||
|
#undef __set_FPSCR
|
||||||
|
#define __get_FPSCR() (0)
|
||||||
|
#define __set_FPSCR(VALUE) ((void)VALUE)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#pragma diag_suppress=Pe940
|
||||||
|
#pragma diag_suppress=Pe177
|
||||||
|
|
||||||
|
#define __enable_irq __enable_interrupt
|
||||||
|
#define __disable_irq __disable_interrupt
|
||||||
|
#define __NOP __no_operation
|
||||||
|
|
||||||
|
#define __get_xPSR __get_PSR
|
||||||
|
|
||||||
|
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
|
||||||
|
{
|
||||||
|
return __LDREX((unsigned long *)ptr);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
|
||||||
|
{
|
||||||
|
return __STREX(value, (unsigned long *)ptr);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
|
||||||
|
#if (__CORTEX_M >= 0x03)
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __RRX(uint32_t value)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#define __enable_fault_irq __enable_fiq
|
||||||
|
#define __disable_fault_irq __disable_fiq
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* (__CORTEX_M >= 0x03) */
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
|
||||||
|
}
|
||||||
|
|
||||||
|
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __get_MSPLIM(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||||
|
res = 0U;
|
||||||
|
#else
|
||||||
|
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
|
||||||
|
#endif
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __set_MSPLIM(uint32_t value)
|
||||||
|
{
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||||
|
(void)value;
|
||||||
|
#else
|
||||||
|
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __get_PSPLIM(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||||
|
res = 0U;
|
||||||
|
#else
|
||||||
|
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
|
||||||
|
#endif
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __set_PSPLIM(uint32_t value)
|
||||||
|
{
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||||
|
(void)value;
|
||||||
|
#else
|
||||||
|
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_SP_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,SP_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR SP_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||||
|
res = 0U;
|
||||||
|
#else
|
||||||
|
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
|
||||||
|
#endif
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||||
|
(void)value;
|
||||||
|
#else
|
||||||
|
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
|
||||||
|
|
||||||
|
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
|
||||||
|
|
||||||
|
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
|
||||||
|
|
||||||
|
#if __IAR_M0_FAMILY
|
||||||
|
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||||
|
{
|
||||||
|
if ((sat >= 1U) && (sat <= 32U))
|
||||||
|
{
|
||||||
|
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||||
|
const int32_t min = -1 - max ;
|
||||||
|
if (val > max)
|
||||||
|
{
|
||||||
|
return max;
|
||||||
|
}
|
||||||
|
else if (val < min)
|
||||||
|
{
|
||||||
|
return min;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return val;
|
||||||
|
}
|
||||||
|
|
||||||
|
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||||
|
{
|
||||||
|
if (sat <= 31U)
|
||||||
|
{
|
||||||
|
const uint32_t max = ((1U << sat) - 1U);
|
||||||
|
if (val > (int32_t)max)
|
||||||
|
{
|
||||||
|
return max;
|
||||||
|
}
|
||||||
|
else if (val < 0)
|
||||||
|
{
|
||||||
|
return 0U;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return (uint32_t)val;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
|
||||||
|
|
||||||
|
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||||
|
return ((uint8_t)res);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||||
|
return ((uint16_t)res);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
|
||||||
|
{
|
||||||
|
__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
|
||||||
|
{
|
||||||
|
__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
|
||||||
|
{
|
||||||
|
__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* (__CORTEX_M >= 0x03) */
|
||||||
|
|
||||||
|
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||||
|
|
||||||
|
|
||||||
|
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||||
|
return ((uint8_t)res);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||||
|
return ((uint16_t)res);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
|
||||||
|
{
|
||||||
|
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
|
||||||
|
{
|
||||||
|
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
|
||||||
|
{
|
||||||
|
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||||
|
return ((uint8_t)res);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||||
|
return ((uint16_t)res);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
|
||||||
|
|
||||||
|
#undef __IAR_FT
|
||||||
|
#undef __IAR_M0_FAMILY
|
||||||
|
#undef __ICCARM_V8
|
||||||
|
|
||||||
|
#pragma diag_default=Pe940
|
||||||
|
#pragma diag_default=Pe177
|
||||||
|
|
||||||
|
#endif /* __CMSIS_ICCARM_H__ */
|
||||||
39
Boot/Drivers/CMSIS/Include/cmsis_version.h
Normal file
39
Boot/Drivers/CMSIS/Include/cmsis_version.h
Normal file
@@ -0,0 +1,39 @@
|
|||||||
|
/**************************************************************************//**
|
||||||
|
* @file cmsis_version.h
|
||||||
|
* @brief CMSIS Core(M) Version definitions
|
||||||
|
* @version V5.0.3
|
||||||
|
* @date 24. June 2019
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#elif defined (__clang__)
|
||||||
|
#pragma clang system_header /* treat file as system include file */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __CMSIS_VERSION_H
|
||||||
|
#define __CMSIS_VERSION_H
|
||||||
|
|
||||||
|
/* CMSIS Version definitions */
|
||||||
|
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||||
|
#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||||
|
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||||
|
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||||
|
#endif
|
||||||
2968
Boot/Drivers/CMSIS/Include/core_armv81mml.h
Normal file
2968
Boot/Drivers/CMSIS/Include/core_armv81mml.h
Normal file
File diff suppressed because it is too large
Load Diff
1921
Boot/Drivers/CMSIS/Include/core_armv8mbl.h
Normal file
1921
Boot/Drivers/CMSIS/Include/core_armv8mbl.h
Normal file
File diff suppressed because it is too large
Load Diff
2835
Boot/Drivers/CMSIS/Include/core_armv8mml.h
Normal file
2835
Boot/Drivers/CMSIS/Include/core_armv8mml.h
Normal file
File diff suppressed because it is too large
Load Diff
952
Boot/Drivers/CMSIS/Include/core_cm0.h
Normal file
952
Boot/Drivers/CMSIS/Include/core_cm0.h
Normal file
@@ -0,0 +1,952 @@
|
|||||||
|
/**************************************************************************//**
|
||||||
|
* @file core_cm0.h
|
||||||
|
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
|
||||||
|
* @version V5.0.6
|
||||||
|
* @date 13. March 2019
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#elif defined (__clang__)
|
||||||
|
#pragma clang system_header /* treat file as system include file */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __CORE_CM0_H_GENERIC
|
||||||
|
#define __CORE_CM0_H_GENERIC
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||||
|
CMSIS violates the following MISRA-C:2004 rules:
|
||||||
|
|
||||||
|
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||||
|
Function definitions in header files are used to allow 'inlining'.
|
||||||
|
|
||||||
|
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||||
|
Unions are used for effective representation of core registers.
|
||||||
|
|
||||||
|
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||||
|
Function-like macros are used to allow more efficient code.
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* CMSIS definitions
|
||||||
|
******************************************************************************/
|
||||||
|
/**
|
||||||
|
\ingroup Cortex_M0
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "cmsis_version.h"
|
||||||
|
|
||||||
|
/* CMSIS CM0 definitions */
|
||||||
|
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||||
|
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||||
|
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
|
||||||
|
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||||
|
|
||||||
|
#define __CORTEX_M (0U) /*!< Cortex-M Core */
|
||||||
|
|
||||||
|
/** __FPU_USED indicates whether an FPU is used or not.
|
||||||
|
This core does not support an FPU at all
|
||||||
|
*/
|
||||||
|
#define __FPU_USED 0U
|
||||||
|
|
||||||
|
#if defined ( __CC_ARM )
|
||||||
|
#if defined __TARGET_FPU_VFP
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||||
|
#if defined __ARM_FP
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __GNUC__ )
|
||||||
|
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __ICCARM__ )
|
||||||
|
#if defined __ARMVFP__
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __TI_ARM__ )
|
||||||
|
#if defined __TI_VFP_SUPPORT__
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __TASKING__ )
|
||||||
|
#if defined __FPU_VFP__
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __CSMC__ )
|
||||||
|
#if ( __CSMC__ & 0x400U)
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __CORE_CM0_H_GENERIC */
|
||||||
|
|
||||||
|
#ifndef __CMSIS_GENERIC
|
||||||
|
|
||||||
|
#ifndef __CORE_CM0_H_DEPENDANT
|
||||||
|
#define __CORE_CM0_H_DEPENDANT
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* check device defines and use defaults */
|
||||||
|
#if defined __CHECK_DEVICE_DEFINES
|
||||||
|
#ifndef __CM0_REV
|
||||||
|
#define __CM0_REV 0x0000U
|
||||||
|
#warning "__CM0_REV not defined in device header file; using default!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __NVIC_PRIO_BITS
|
||||||
|
#define __NVIC_PRIO_BITS 2U
|
||||||
|
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __Vendor_SysTickConfig
|
||||||
|
#define __Vendor_SysTickConfig 0U
|
||||||
|
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* IO definitions (access restrictions to peripheral registers) */
|
||||||
|
/**
|
||||||
|
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||||
|
|
||||||
|
<strong>IO Type Qualifiers</strong> are used
|
||||||
|
\li to specify the access to peripheral variables.
|
||||||
|
\li for automatic generation of peripheral register debug information.
|
||||||
|
*/
|
||||||
|
#ifdef __cplusplus
|
||||||
|
#define __I volatile /*!< Defines 'read only' permissions */
|
||||||
|
#else
|
||||||
|
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||||
|
#endif
|
||||||
|
#define __O volatile /*!< Defines 'write only' permissions */
|
||||||
|
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||||
|
|
||||||
|
/* following defines should be used for structure members */
|
||||||
|
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||||
|
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||||
|
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||||
|
|
||||||
|
/*@} end of group Cortex_M0 */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Register Abstraction
|
||||||
|
Core Register contain:
|
||||||
|
- Core Register
|
||||||
|
- Core NVIC Register
|
||||||
|
- Core SCB Register
|
||||||
|
- Core SysTick Register
|
||||||
|
******************************************************************************/
|
||||||
|
/**
|
||||||
|
\defgroup CMSIS_core_register Defines and Type Definitions
|
||||||
|
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_CORE Status and Control Registers
|
||||||
|
\brief Core Register type definitions.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Union type to access the Application Program Status Register (APSR).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||||
|
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||||
|
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||||
|
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||||
|
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} APSR_Type;
|
||||||
|
|
||||||
|
/* APSR Register Definitions */
|
||||||
|
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||||
|
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||||
|
|
||||||
|
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
|
||||||
|
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
|
||||||
|
|
||||||
|
#define APSR_C_Pos 29U /*!< APSR: C Position */
|
||||||
|
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
|
||||||
|
|
||||||
|
#define APSR_V_Pos 28U /*!< APSR: V Position */
|
||||||
|
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||||
|
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} IPSR_Type;
|
||||||
|
|
||||||
|
/* IPSR Register Definitions */
|
||||||
|
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||||
|
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||||
|
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||||
|
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||||
|
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||||
|
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||||
|
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||||
|
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||||
|
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} xPSR_Type;
|
||||||
|
|
||||||
|
/* xPSR Register Definitions */
|
||||||
|
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||||
|
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||||
|
|
||||||
|
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
|
||||||
|
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
|
||||||
|
|
||||||
|
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
|
||||||
|
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
|
||||||
|
|
||||||
|
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
|
||||||
|
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
|
||||||
|
|
||||||
|
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||||
|
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||||
|
|
||||||
|
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||||
|
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Union type to access the Control Registers (CONTROL).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
|
||||||
|
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||||
|
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} CONTROL_Type;
|
||||||
|
|
||||||
|
/* CONTROL Register Definitions */
|
||||||
|
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||||
|
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_CORE */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||||
|
\brief Type definitions for the NVIC Registers
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||||
|
uint32_t RESERVED0[31U];
|
||||||
|
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||||
|
uint32_t RESERVED1[31U];
|
||||||
|
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||||
|
uint32_t RESERVED2[31U];
|
||||||
|
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||||
|
uint32_t RESERVED3[31U];
|
||||||
|
uint32_t RESERVED4[64U];
|
||||||
|
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||||
|
} NVIC_Type;
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_NVIC */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||||
|
\brief Type definitions for the System Control Block Registers
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Structure type to access the System Control Block (SCB).
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||||
|
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||||
|
uint32_t RESERVED0;
|
||||||
|
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||||
|
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||||
|
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||||
|
uint32_t RESERVED1;
|
||||||
|
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||||
|
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||||
|
} SCB_Type;
|
||||||
|
|
||||||
|
/* SCB CPUID Register Definitions */
|
||||||
|
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||||
|
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
||||||
|
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
||||||
|
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
||||||
|
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||||
|
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||||
|
|
||||||
|
/* SCB Interrupt Control State Register Definitions */
|
||||||
|
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||||
|
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
||||||
|
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
||||||
|
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
||||||
|
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
||||||
|
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
||||||
|
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
||||||
|
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
||||||
|
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||||
|
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||||
|
|
||||||
|
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||||
|
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||||
|
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||||
|
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
||||||
|
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||||
|
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||||
|
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||||
|
|
||||||
|
/* SCB System Control Register Definitions */
|
||||||
|
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||||
|
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||||
|
|
||||||
|
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
||||||
|
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||||
|
|
||||||
|
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||||
|
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||||
|
|
||||||
|
/* SCB Configuration Control Register Definitions */
|
||||||
|
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||||
|
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||||
|
|
||||||
|
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||||
|
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||||
|
|
||||||
|
/* SCB System Handler Control and State Register Definitions */
|
||||||
|
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||||
|
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_SCB */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||||
|
\brief Type definitions for the System Timer Registers.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Structure type to access the System Timer (SysTick).
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||||
|
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||||
|
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||||
|
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||||
|
} SysTick_Type;
|
||||||
|
|
||||||
|
/* SysTick Control / Status Register Definitions */
|
||||||
|
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||||
|
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||||
|
|
||||||
|
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
||||||
|
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||||
|
|
||||||
|
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
||||||
|
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||||
|
|
||||||
|
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||||
|
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||||
|
|
||||||
|
/* SysTick Reload Register Definitions */
|
||||||
|
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||||
|
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||||
|
|
||||||
|
/* SysTick Current Register Definitions */
|
||||||
|
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||||
|
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||||
|
|
||||||
|
/* SysTick Calibration Register Definitions */
|
||||||
|
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||||
|
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||||
|
|
||||||
|
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
||||||
|
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||||
|
|
||||||
|
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
||||||
|
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_SysTick */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||||
|
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
|
||||||
|
Therefore they are not covered by the Cortex-M0 header file.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
/*@} end of group CMSIS_CoreDebug */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_core_bitfield Core register bit field macros
|
||||||
|
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Mask and shift a bit field value for use in a register bit range.
|
||||||
|
\param[in] field Name of the register bit field.
|
||||||
|
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
||||||
|
\return Masked and shifted value.
|
||||||
|
*/
|
||||||
|
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Mask and shift a register value to extract a bit filed value.
|
||||||
|
\param[in] field Name of the register bit field.
|
||||||
|
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
||||||
|
\return Masked and shifted bit field value.
|
||||||
|
*/
|
||||||
|
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_core_bitfield */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_core_base Core Definitions
|
||||||
|
\brief Definitions for base addresses, unions, and structures.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Memory mapping of Core Hardware */
|
||||||
|
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||||
|
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||||
|
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||||
|
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||||
|
|
||||||
|
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||||
|
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||||
|
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||||
|
|
||||||
|
|
||||||
|
/*@} */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Hardware Abstraction Layer
|
||||||
|
Core Function Interface contains:
|
||||||
|
- Core NVIC Functions
|
||||||
|
- Core SysTick Functions
|
||||||
|
- Core Register Access Functions
|
||||||
|
******************************************************************************/
|
||||||
|
/**
|
||||||
|
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* ########################## NVIC functions #################################### */
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||||
|
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef CMSIS_NVIC_VIRTUAL
|
||||||
|
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||||
|
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||||
|
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||||
|
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||||
|
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||||
|
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||||
|
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||||
|
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||||
|
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
|
||||||
|
#define NVIC_SetPriority __NVIC_SetPriority
|
||||||
|
#define NVIC_GetPriority __NVIC_GetPriority
|
||||||
|
#define NVIC_SystemReset __NVIC_SystemReset
|
||||||
|
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||||
|
|
||||||
|
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||||
|
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
#define NVIC_SetVector __NVIC_SetVector
|
||||||
|
#define NVIC_GetVector __NVIC_GetVector
|
||||||
|
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||||
|
|
||||||
|
#define NVIC_USER_IRQ_OFFSET 16
|
||||||
|
|
||||||
|
|
||||||
|
/* The following EXC_RETURN values are saved the LR on exception entry */
|
||||||
|
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
|
||||||
|
|
||||||
|
|
||||||
|
/* Interrupt Priorities are WORD accessible only under Armv6-M */
|
||||||
|
/* The following MACROS handle generation of the register offset and byte masks */
|
||||||
|
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||||
|
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||||
|
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||||
|
|
||||||
|
#define __NVIC_SetPriorityGrouping(X) (void)(X)
|
||||||
|
#define __NVIC_GetPriorityGrouping() (0U)
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Enable Interrupt
|
||||||
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
__COMPILER_BARRIER();
|
||||||
|
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
__COMPILER_BARRIER();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Enable status
|
||||||
|
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\return 0 Interrupt is not enabled.
|
||||||
|
\return 1 Interrupt is enabled.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable Interrupt
|
||||||
|
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Pending Interrupt
|
||||||
|
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\return 0 Interrupt status is not pending.
|
||||||
|
\return 1 Interrupt status is pending.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Pending Interrupt
|
||||||
|
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Clear Pending Interrupt
|
||||||
|
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Interrupt Priority
|
||||||
|
\details Sets the priority of a device specific interrupt or a processor exception.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\param [in] priority Priority to set.
|
||||||
|
\note The priority cannot be set for every processor exception.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||||
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||||
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Priority
|
||||||
|
\details Reads the priority of a device specific interrupt or a processor exception.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\return Interrupt Priority.
|
||||||
|
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Encode Priority
|
||||||
|
\details Encodes the priority for an interrupt with the given priority group,
|
||||||
|
preemptive priority value, and subpriority value.
|
||||||
|
In case of a conflict between priority grouping and available
|
||||||
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
||||||
|
\param [in] PriorityGroup Used priority group.
|
||||||
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
||||||
|
\param [in] SubPriority Subpriority value (starting from 0).
|
||||||
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||||
|
{
|
||||||
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||||
|
uint32_t PreemptPriorityBits;
|
||||||
|
uint32_t SubPriorityBits;
|
||||||
|
|
||||||
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||||
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||||
|
|
||||||
|
return (
|
||||||
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
||||||
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
||||||
|
);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Decode Priority
|
||||||
|
\details Decodes an interrupt priority value with a given priority group to
|
||||||
|
preemptive priority value and subpriority value.
|
||||||
|
In case of a conflict between priority grouping and available
|
||||||
|
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
|
||||||
|
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
|
||||||
|
\param [in] PriorityGroup Used priority group.
|
||||||
|
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
|
||||||
|
\param [out] pSubPriority Subpriority value (starting from 0).
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
|
||||||
|
{
|
||||||
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||||
|
uint32_t PreemptPriorityBits;
|
||||||
|
uint32_t SubPriorityBits;
|
||||||
|
|
||||||
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||||
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||||
|
|
||||||
|
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
|
||||||
|
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Interrupt Vector
|
||||||
|
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
Address 0 must be mapped to SRAM.
|
||||||
|
\param [in] IRQn Interrupt number
|
||||||
|
\param [in] vector Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||||
|
{
|
||||||
|
uint32_t vectors = 0x0U;
|
||||||
|
(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector;
|
||||||
|
/* ARM Application Note 321 states that the M0 does not require the architectural barrier */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Vector
|
||||||
|
\details Reads an interrupt vector from interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\return Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
uint32_t vectors = 0x0U;
|
||||||
|
return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief System Reset
|
||||||
|
\details Initiates a system reset request to reset the MCU.
|
||||||
|
*/
|
||||||
|
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
||||||
|
{
|
||||||
|
__DSB(); /* Ensure all outstanding memory accesses included
|
||||||
|
buffered write are completed before reset */
|
||||||
|
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||||
|
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||||
|
__DSB(); /* Ensure completion of memory access */
|
||||||
|
|
||||||
|
for(;;) /* wait until reset */
|
||||||
|
{
|
||||||
|
__NOP();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_NVICFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
/* ########################## FPU functions #################################### */
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_FpuFunctions FPU Functions
|
||||||
|
\brief Function that provides FPU type.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief get FPU type
|
||||||
|
\details returns the FPU type
|
||||||
|
\returns
|
||||||
|
- \b 0: No FPU
|
||||||
|
- \b 1: Single precision FPU
|
||||||
|
- \b 2: Double + Single precision FPU
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||||||
|
{
|
||||||
|
return 0U; /* No FPU */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_FpuFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* ################################## SysTick function ############################################ */
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||||
|
\brief Functions that configure the System.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief System Tick Configuration
|
||||||
|
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||||
|
Counter is in free running mode to generate periodic interrupts.
|
||||||
|
\param [in] ticks Number of ticks between two interrupts.
|
||||||
|
\return 0 Function succeeded.
|
||||||
|
\return 1 Function failed.
|
||||||
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||||
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||||
|
must contain a vendor-specific implementation of this function.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||||
|
{
|
||||||
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||||||
|
{
|
||||||
|
return (1UL); /* Reload value impossible */
|
||||||
|
}
|
||||||
|
|
||||||
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||||
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||||
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||||
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||||
|
SysTick_CTRL_TICKINT_Msk |
|
||||||
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||||
|
return (0UL); /* Function successful */
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __CORE_CM0_H_DEPENDANT */
|
||||||
|
|
||||||
|
#endif /* __CMSIS_GENERIC */
|
||||||
1085
Boot/Drivers/CMSIS/Include/core_cm0plus.h
Normal file
1085
Boot/Drivers/CMSIS/Include/core_cm0plus.h
Normal file
File diff suppressed because it is too large
Load Diff
979
Boot/Drivers/CMSIS/Include/core_cm1.h
Normal file
979
Boot/Drivers/CMSIS/Include/core_cm1.h
Normal file
@@ -0,0 +1,979 @@
|
|||||||
|
/**************************************************************************//**
|
||||||
|
* @file core_cm1.h
|
||||||
|
* @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
|
||||||
|
* @version V1.0.1
|
||||||
|
* @date 12. November 2018
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#elif defined (__clang__)
|
||||||
|
#pragma clang system_header /* treat file as system include file */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __CORE_CM1_H_GENERIC
|
||||||
|
#define __CORE_CM1_H_GENERIC
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||||
|
CMSIS violates the following MISRA-C:2004 rules:
|
||||||
|
|
||||||
|
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||||
|
Function definitions in header files are used to allow 'inlining'.
|
||||||
|
|
||||||
|
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||||
|
Unions are used for effective representation of core registers.
|
||||||
|
|
||||||
|
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||||
|
Function-like macros are used to allow more efficient code.
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* CMSIS definitions
|
||||||
|
******************************************************************************/
|
||||||
|
/**
|
||||||
|
\ingroup Cortex_M1
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "cmsis_version.h"
|
||||||
|
|
||||||
|
/* CMSIS CM1 definitions */
|
||||||
|
#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||||
|
#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||||
|
#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
|
||||||
|
__CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||||
|
|
||||||
|
#define __CORTEX_M (1U) /*!< Cortex-M Core */
|
||||||
|
|
||||||
|
/** __FPU_USED indicates whether an FPU is used or not.
|
||||||
|
This core does not support an FPU at all
|
||||||
|
*/
|
||||||
|
#define __FPU_USED 0U
|
||||||
|
|
||||||
|
#if defined ( __CC_ARM )
|
||||||
|
#if defined __TARGET_FPU_VFP
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||||
|
#if defined __ARM_FP
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __GNUC__ )
|
||||||
|
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __ICCARM__ )
|
||||||
|
#if defined __ARMVFP__
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __TI_ARM__ )
|
||||||
|
#if defined __TI_VFP_SUPPORT__
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __TASKING__ )
|
||||||
|
#if defined __FPU_VFP__
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __CSMC__ )
|
||||||
|
#if ( __CSMC__ & 0x400U)
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __CORE_CM1_H_GENERIC */
|
||||||
|
|
||||||
|
#ifndef __CMSIS_GENERIC
|
||||||
|
|
||||||
|
#ifndef __CORE_CM1_H_DEPENDANT
|
||||||
|
#define __CORE_CM1_H_DEPENDANT
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* check device defines and use defaults */
|
||||||
|
#if defined __CHECK_DEVICE_DEFINES
|
||||||
|
#ifndef __CM1_REV
|
||||||
|
#define __CM1_REV 0x0100U
|
||||||
|
#warning "__CM1_REV not defined in device header file; using default!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __NVIC_PRIO_BITS
|
||||||
|
#define __NVIC_PRIO_BITS 2U
|
||||||
|
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __Vendor_SysTickConfig
|
||||||
|
#define __Vendor_SysTickConfig 0U
|
||||||
|
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* IO definitions (access restrictions to peripheral registers) */
|
||||||
|
/**
|
||||||
|
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||||
|
|
||||||
|
<strong>IO Type Qualifiers</strong> are used
|
||||||
|
\li to specify the access to peripheral variables.
|
||||||
|
\li for automatic generation of peripheral register debug information.
|
||||||
|
*/
|
||||||
|
#ifdef __cplusplus
|
||||||
|
#define __I volatile /*!< Defines 'read only' permissions */
|
||||||
|
#else
|
||||||
|
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||||
|
#endif
|
||||||
|
#define __O volatile /*!< Defines 'write only' permissions */
|
||||||
|
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||||
|
|
||||||
|
/* following defines should be used for structure members */
|
||||||
|
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||||
|
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||||
|
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||||
|
|
||||||
|
/*@} end of group Cortex_M1 */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Register Abstraction
|
||||||
|
Core Register contain:
|
||||||
|
- Core Register
|
||||||
|
- Core NVIC Register
|
||||||
|
- Core SCB Register
|
||||||
|
- Core SysTick Register
|
||||||
|
******************************************************************************/
|
||||||
|
/**
|
||||||
|
\defgroup CMSIS_core_register Defines and Type Definitions
|
||||||
|
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_CORE Status and Control Registers
|
||||||
|
\brief Core Register type definitions.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Union type to access the Application Program Status Register (APSR).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||||
|
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||||
|
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||||
|
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||||
|
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} APSR_Type;
|
||||||
|
|
||||||
|
/* APSR Register Definitions */
|
||||||
|
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||||
|
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||||
|
|
||||||
|
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
|
||||||
|
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
|
||||||
|
|
||||||
|
#define APSR_C_Pos 29U /*!< APSR: C Position */
|
||||||
|
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
|
||||||
|
|
||||||
|
#define APSR_V_Pos 28U /*!< APSR: V Position */
|
||||||
|
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||||
|
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} IPSR_Type;
|
||||||
|
|
||||||
|
/* IPSR Register Definitions */
|
||||||
|
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||||
|
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||||
|
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||||
|
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||||
|
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||||
|
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||||
|
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||||
|
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||||
|
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} xPSR_Type;
|
||||||
|
|
||||||
|
/* xPSR Register Definitions */
|
||||||
|
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||||
|
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||||
|
|
||||||
|
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
|
||||||
|
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
|
||||||
|
|
||||||
|
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
|
||||||
|
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
|
||||||
|
|
||||||
|
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
|
||||||
|
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
|
||||||
|
|
||||||
|
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||||
|
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||||
|
|
||||||
|
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||||
|
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Union type to access the Control Registers (CONTROL).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
|
||||||
|
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||||
|
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} CONTROL_Type;
|
||||||
|
|
||||||
|
/* CONTROL Register Definitions */
|
||||||
|
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||||
|
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_CORE */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||||
|
\brief Type definitions for the NVIC Registers
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||||
|
uint32_t RESERVED0[31U];
|
||||||
|
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||||
|
uint32_t RSERVED1[31U];
|
||||||
|
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||||
|
uint32_t RESERVED2[31U];
|
||||||
|
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||||
|
uint32_t RESERVED3[31U];
|
||||||
|
uint32_t RESERVED4[64U];
|
||||||
|
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||||
|
} NVIC_Type;
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_NVIC */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||||
|
\brief Type definitions for the System Control Block Registers
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Structure type to access the System Control Block (SCB).
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||||
|
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||||
|
uint32_t RESERVED0;
|
||||||
|
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||||
|
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||||
|
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||||
|
uint32_t RESERVED1;
|
||||||
|
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||||
|
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||||
|
} SCB_Type;
|
||||||
|
|
||||||
|
/* SCB CPUID Register Definitions */
|
||||||
|
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||||
|
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
||||||
|
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
||||||
|
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
||||||
|
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||||
|
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||||
|
|
||||||
|
/* SCB Interrupt Control State Register Definitions */
|
||||||
|
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||||
|
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
||||||
|
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
||||||
|
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
||||||
|
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
||||||
|
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
||||||
|
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
||||||
|
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
||||||
|
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||||
|
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||||
|
|
||||||
|
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||||
|
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||||
|
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||||
|
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
||||||
|
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||||
|
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||||
|
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||||
|
|
||||||
|
/* SCB System Control Register Definitions */
|
||||||
|
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||||
|
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||||
|
|
||||||
|
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
||||||
|
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||||
|
|
||||||
|
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||||
|
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||||
|
|
||||||
|
/* SCB Configuration Control Register Definitions */
|
||||||
|
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||||
|
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||||
|
|
||||||
|
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||||
|
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||||
|
|
||||||
|
/* SCB System Handler Control and State Register Definitions */
|
||||||
|
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||||
|
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_SCB */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
|
||||||
|
\brief Type definitions for the System Control and ID Register not in the SCB
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Structure type to access the System Control and ID Register not in the SCB.
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t RESERVED0[2U];
|
||||||
|
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
|
||||||
|
} SCnSCB_Type;
|
||||||
|
|
||||||
|
/* Auxiliary Control Register Definitions */
|
||||||
|
#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
|
||||||
|
#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
|
||||||
|
|
||||||
|
#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
|
||||||
|
#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_SCnotSCB */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||||
|
\brief Type definitions for the System Timer Registers.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Structure type to access the System Timer (SysTick).
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||||
|
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||||
|
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||||
|
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||||
|
} SysTick_Type;
|
||||||
|
|
||||||
|
/* SysTick Control / Status Register Definitions */
|
||||||
|
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||||
|
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||||
|
|
||||||
|
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
||||||
|
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||||
|
|
||||||
|
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
||||||
|
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||||
|
|
||||||
|
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||||
|
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||||
|
|
||||||
|
/* SysTick Reload Register Definitions */
|
||||||
|
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||||
|
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||||
|
|
||||||
|
/* SysTick Current Register Definitions */
|
||||||
|
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||||
|
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||||
|
|
||||||
|
/* SysTick Calibration Register Definitions */
|
||||||
|
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||||
|
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||||
|
|
||||||
|
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
||||||
|
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||||
|
|
||||||
|
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
||||||
|
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_SysTick */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||||
|
\brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
|
||||||
|
Therefore they are not covered by the Cortex-M1 header file.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
/*@} end of group CMSIS_CoreDebug */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_core_bitfield Core register bit field macros
|
||||||
|
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Mask and shift a bit field value for use in a register bit range.
|
||||||
|
\param[in] field Name of the register bit field.
|
||||||
|
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
||||||
|
\return Masked and shifted value.
|
||||||
|
*/
|
||||||
|
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Mask and shift a register value to extract a bit filed value.
|
||||||
|
\param[in] field Name of the register bit field.
|
||||||
|
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
||||||
|
\return Masked and shifted bit field value.
|
||||||
|
*/
|
||||||
|
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_core_bitfield */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_core_base Core Definitions
|
||||||
|
\brief Definitions for base addresses, unions, and structures.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Memory mapping of Core Hardware */
|
||||||
|
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||||
|
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||||
|
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||||
|
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||||
|
|
||||||
|
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
|
||||||
|
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||||
|
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||||
|
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||||
|
|
||||||
|
|
||||||
|
/*@} */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Hardware Abstraction Layer
|
||||||
|
Core Function Interface contains:
|
||||||
|
- Core NVIC Functions
|
||||||
|
- Core SysTick Functions
|
||||||
|
- Core Register Access Functions
|
||||||
|
******************************************************************************/
|
||||||
|
/**
|
||||||
|
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* ########################## NVIC functions #################################### */
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||||
|
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef CMSIS_NVIC_VIRTUAL
|
||||||
|
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||||
|
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||||
|
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||||
|
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||||
|
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||||
|
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||||
|
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||||
|
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||||
|
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
|
||||||
|
#define NVIC_SetPriority __NVIC_SetPriority
|
||||||
|
#define NVIC_GetPriority __NVIC_GetPriority
|
||||||
|
#define NVIC_SystemReset __NVIC_SystemReset
|
||||||
|
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||||
|
|
||||||
|
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||||
|
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
#define NVIC_SetVector __NVIC_SetVector
|
||||||
|
#define NVIC_GetVector __NVIC_GetVector
|
||||||
|
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||||
|
|
||||||
|
#define NVIC_USER_IRQ_OFFSET 16
|
||||||
|
|
||||||
|
|
||||||
|
/* The following EXC_RETURN values are saved the LR on exception entry */
|
||||||
|
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
|
||||||
|
|
||||||
|
|
||||||
|
/* Interrupt Priorities are WORD accessible only under Armv6-M */
|
||||||
|
/* The following MACROS handle generation of the register offset and byte masks */
|
||||||
|
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||||
|
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||||
|
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||||
|
|
||||||
|
#define __NVIC_SetPriorityGrouping(X) (void)(X)
|
||||||
|
#define __NVIC_GetPriorityGrouping() (0U)
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Enable Interrupt
|
||||||
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
__COMPILER_BARRIER();
|
||||||
|
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
__COMPILER_BARRIER();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Enable status
|
||||||
|
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\return 0 Interrupt is not enabled.
|
||||||
|
\return 1 Interrupt is enabled.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable Interrupt
|
||||||
|
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Pending Interrupt
|
||||||
|
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\return 0 Interrupt status is not pending.
|
||||||
|
\return 1 Interrupt status is pending.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Pending Interrupt
|
||||||
|
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Clear Pending Interrupt
|
||||||
|
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Interrupt Priority
|
||||||
|
\details Sets the priority of a device specific interrupt or a processor exception.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\param [in] priority Priority to set.
|
||||||
|
\note The priority cannot be set for every processor exception.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||||
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||||
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Priority
|
||||||
|
\details Reads the priority of a device specific interrupt or a processor exception.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\return Interrupt Priority.
|
||||||
|
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Encode Priority
|
||||||
|
\details Encodes the priority for an interrupt with the given priority group,
|
||||||
|
preemptive priority value, and subpriority value.
|
||||||
|
In case of a conflict between priority grouping and available
|
||||||
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
||||||
|
\param [in] PriorityGroup Used priority group.
|
||||||
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
||||||
|
\param [in] SubPriority Subpriority value (starting from 0).
|
||||||
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||||
|
{
|
||||||
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||||
|
uint32_t PreemptPriorityBits;
|
||||||
|
uint32_t SubPriorityBits;
|
||||||
|
|
||||||
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||||
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||||
|
|
||||||
|
return (
|
||||||
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
||||||
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
||||||
|
);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Decode Priority
|
||||||
|
\details Decodes an interrupt priority value with a given priority group to
|
||||||
|
preemptive priority value and subpriority value.
|
||||||
|
In case of a conflict between priority grouping and available
|
||||||
|
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
|
||||||
|
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
|
||||||
|
\param [in] PriorityGroup Used priority group.
|
||||||
|
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
|
||||||
|
\param [out] pSubPriority Subpriority value (starting from 0).
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
|
||||||
|
{
|
||||||
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||||
|
uint32_t PreemptPriorityBits;
|
||||||
|
uint32_t SubPriorityBits;
|
||||||
|
|
||||||
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||||
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||||
|
|
||||||
|
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
|
||||||
|
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Interrupt Vector
|
||||||
|
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
Address 0 must be mapped to SRAM.
|
||||||
|
\param [in] IRQn Interrupt number
|
||||||
|
\param [in] vector Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||||
|
{
|
||||||
|
uint32_t *vectors = (uint32_t *)0x0U;
|
||||||
|
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||||
|
/* ARM Application Note 321 states that the M1 does not require the architectural barrier */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Vector
|
||||||
|
\details Reads an interrupt vector from interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\return Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
uint32_t *vectors = (uint32_t *)0x0U;
|
||||||
|
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief System Reset
|
||||||
|
\details Initiates a system reset request to reset the MCU.
|
||||||
|
*/
|
||||||
|
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
||||||
|
{
|
||||||
|
__DSB(); /* Ensure all outstanding memory accesses included
|
||||||
|
buffered write are completed before reset */
|
||||||
|
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||||
|
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||||
|
__DSB(); /* Ensure completion of memory access */
|
||||||
|
|
||||||
|
for(;;) /* wait until reset */
|
||||||
|
{
|
||||||
|
__NOP();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_NVICFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
/* ########################## FPU functions #################################### */
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_FpuFunctions FPU Functions
|
||||||
|
\brief Function that provides FPU type.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief get FPU type
|
||||||
|
\details returns the FPU type
|
||||||
|
\returns
|
||||||
|
- \b 0: No FPU
|
||||||
|
- \b 1: Single precision FPU
|
||||||
|
- \b 2: Double + Single precision FPU
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||||||
|
{
|
||||||
|
return 0U; /* No FPU */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_FpuFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* ################################## SysTick function ############################################ */
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||||
|
\brief Functions that configure the System.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief System Tick Configuration
|
||||||
|
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||||
|
Counter is in free running mode to generate periodic interrupts.
|
||||||
|
\param [in] ticks Number of ticks between two interrupts.
|
||||||
|
\return 0 Function succeeded.
|
||||||
|
\return 1 Function failed.
|
||||||
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||||
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||||
|
must contain a vendor-specific implementation of this function.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||||
|
{
|
||||||
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||||||
|
{
|
||||||
|
return (1UL); /* Reload value impossible */
|
||||||
|
}
|
||||||
|
|
||||||
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||||
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||||
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||||
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||||
|
SysTick_CTRL_TICKINT_Msk |
|
||||||
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||||
|
return (0UL); /* Function successful */
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __CORE_CM1_H_DEPENDANT */
|
||||||
|
|
||||||
|
#endif /* __CMSIS_GENERIC */
|
||||||
1996
Boot/Drivers/CMSIS/Include/core_cm23.h
Normal file
1996
Boot/Drivers/CMSIS/Include/core_cm23.h
Normal file
File diff suppressed because it is too large
Load Diff
1937
Boot/Drivers/CMSIS/Include/core_cm3.h
Normal file
1937
Boot/Drivers/CMSIS/Include/core_cm3.h
Normal file
File diff suppressed because it is too large
Load Diff
2910
Boot/Drivers/CMSIS/Include/core_cm33.h
Normal file
2910
Boot/Drivers/CMSIS/Include/core_cm33.h
Normal file
File diff suppressed because it is too large
Load Diff
2910
Boot/Drivers/CMSIS/Include/core_cm35p.h
Normal file
2910
Boot/Drivers/CMSIS/Include/core_cm35p.h
Normal file
File diff suppressed because it is too large
Load Diff
2124
Boot/Drivers/CMSIS/Include/core_cm4.h
Normal file
2124
Boot/Drivers/CMSIS/Include/core_cm4.h
Normal file
File diff suppressed because it is too large
Load Diff
2725
Boot/Drivers/CMSIS/Include/core_cm7.h
Normal file
2725
Boot/Drivers/CMSIS/Include/core_cm7.h
Normal file
File diff suppressed because it is too large
Load Diff
1025
Boot/Drivers/CMSIS/Include/core_sc000.h
Normal file
1025
Boot/Drivers/CMSIS/Include/core_sc000.h
Normal file
File diff suppressed because it is too large
Load Diff
1912
Boot/Drivers/CMSIS/Include/core_sc300.h
Normal file
1912
Boot/Drivers/CMSIS/Include/core_sc300.h
Normal file
File diff suppressed because it is too large
Load Diff
272
Boot/Drivers/CMSIS/Include/mpu_armv7.h
Normal file
272
Boot/Drivers/CMSIS/Include/mpu_armv7.h
Normal file
@@ -0,0 +1,272 @@
|
|||||||
|
/******************************************************************************
|
||||||
|
* @file mpu_armv7.h
|
||||||
|
* @brief CMSIS MPU API for Armv7-M MPU
|
||||||
|
* @version V5.1.0
|
||||||
|
* @date 08. March 2019
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2017-2019 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#elif defined (__clang__)
|
||||||
|
#pragma clang system_header /* treat file as system include file */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef ARM_MPU_ARMV7_H
|
||||||
|
#define ARM_MPU_ARMV7_H
|
||||||
|
|
||||||
|
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
|
||||||
|
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
|
||||||
|
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
|
||||||
|
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
|
||||||
|
|
||||||
|
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
|
||||||
|
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
|
||||||
|
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
|
||||||
|
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
|
||||||
|
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
|
||||||
|
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
|
||||||
|
|
||||||
|
/** MPU Region Base Address Register Value
|
||||||
|
*
|
||||||
|
* \param Region The region to be configured, number 0 to 15.
|
||||||
|
* \param BaseAddress The base address for the region.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_RBAR(Region, BaseAddress) \
|
||||||
|
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
|
||||||
|
((Region) & MPU_RBAR_REGION_Msk) | \
|
||||||
|
(MPU_RBAR_VALID_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attributes
|
||||||
|
*
|
||||||
|
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||||
|
* \param IsShareable Region is shareable between multiple bus masters.
|
||||||
|
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||||
|
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
|
||||||
|
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
||||||
|
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
||||||
|
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
|
||||||
|
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Region Attribute and Size Register Value
|
||||||
|
*
|
||||||
|
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||||
|
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||||
|
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
|
||||||
|
* \param SubRegionDisable Sub-region disable field.
|
||||||
|
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
|
||||||
|
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
|
||||||
|
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
|
||||||
|
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
|
||||||
|
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
|
||||||
|
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
|
||||||
|
(((MPU_RASR_ENABLE_Msk))))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Region Attribute and Size Register Value
|
||||||
|
*
|
||||||
|
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||||
|
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||||
|
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||||
|
* \param IsShareable Region is shareable between multiple bus masters.
|
||||||
|
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||||
|
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||||
|
* \param SubRegionDisable Sub-region disable field.
|
||||||
|
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
|
||||||
|
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute for strongly ordered memory.
|
||||||
|
* - TEX: 000b
|
||||||
|
* - Shareable
|
||||||
|
* - Non-cacheable
|
||||||
|
* - Non-bufferable
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute for device memory.
|
||||||
|
* - TEX: 000b (if shareable) or 010b (if non-shareable)
|
||||||
|
* - Shareable or non-shareable
|
||||||
|
* - Non-cacheable
|
||||||
|
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
|
||||||
|
*
|
||||||
|
* \param IsShareable Configures the device memory as shareable or non-shareable.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute for normal memory.
|
||||||
|
* - TEX: 1BBb (reflecting outer cacheability rules)
|
||||||
|
* - Shareable or non-shareable
|
||||||
|
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
|
||||||
|
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
|
||||||
|
*
|
||||||
|
* \param OuterCp Configures the outer cache policy.
|
||||||
|
* \param InnerCp Configures the inner cache policy.
|
||||||
|
* \param IsShareable Configures the memory as shareable or non-shareable.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute non-cacheable policy.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_CACHEP_NOCACHE 0U
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute write-back, write and read allocate policy.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_CACHEP_WB_WRA 1U
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute write-through, no write allocate policy.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_CACHEP_WT_NWA 2U
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute write-back, no write allocate policy.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_CACHEP_WB_NWA 3U
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Struct for a single MPU Region
|
||||||
|
*/
|
||||||
|
typedef struct {
|
||||||
|
uint32_t RBAR; //!< The region base address register value (RBAR)
|
||||||
|
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
||||||
|
} ARM_MPU_Region_t;
|
||||||
|
|
||||||
|
/** Enable the MPU.
|
||||||
|
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||||
|
{
|
||||||
|
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||||
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
|
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
|
#endif
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Disable the MPU.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||||
|
{
|
||||||
|
__DMB();
|
||||||
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
|
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
|
#endif
|
||||||
|
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Clear and disable the given MPU region.
|
||||||
|
* \param rnr Region number to be cleared.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||||
|
{
|
||||||
|
MPU->RNR = rnr;
|
||||||
|
MPU->RASR = 0U;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Configure an MPU region.
|
||||||
|
* \param rbar Value for RBAR register.
|
||||||
|
* \param rsar Value for RSAR register.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
|
||||||
|
{
|
||||||
|
MPU->RBAR = rbar;
|
||||||
|
MPU->RASR = rasr;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Configure the given MPU region.
|
||||||
|
* \param rnr Region number to be configured.
|
||||||
|
* \param rbar Value for RBAR register.
|
||||||
|
* \param rsar Value for RSAR register.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
|
||||||
|
{
|
||||||
|
MPU->RNR = rnr;
|
||||||
|
MPU->RBAR = rbar;
|
||||||
|
MPU->RASR = rasr;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||||
|
* \param dst Destination data is copied to.
|
||||||
|
* \param src Source data is copied from.
|
||||||
|
* \param len Amount of data words to be copied.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||||
|
{
|
||||||
|
uint32_t i;
|
||||||
|
for (i = 0U; i < len; ++i)
|
||||||
|
{
|
||||||
|
dst[i] = src[i];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Load the given number of MPU regions from a table.
|
||||||
|
* \param table Pointer to the MPU configuration table.
|
||||||
|
* \param cnt Amount of regions to be configured.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||||
|
{
|
||||||
|
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||||
|
while (cnt > MPU_TYPE_RALIASES) {
|
||||||
|
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
|
||||||
|
table += MPU_TYPE_RALIASES;
|
||||||
|
cnt -= MPU_TYPE_RALIASES;
|
||||||
|
}
|
||||||
|
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
346
Boot/Drivers/CMSIS/Include/mpu_armv8.h
Normal file
346
Boot/Drivers/CMSIS/Include/mpu_armv8.h
Normal file
@@ -0,0 +1,346 @@
|
|||||||
|
/******************************************************************************
|
||||||
|
* @file mpu_armv8.h
|
||||||
|
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
|
||||||
|
* @version V5.1.0
|
||||||
|
* @date 08. March 2019
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2017-2019 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#elif defined (__clang__)
|
||||||
|
#pragma clang system_header /* treat file as system include file */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef ARM_MPU_ARMV8_H
|
||||||
|
#define ARM_MPU_ARMV8_H
|
||||||
|
|
||||||
|
/** \brief Attribute for device memory (outer only) */
|
||||||
|
#define ARM_MPU_ATTR_DEVICE ( 0U )
|
||||||
|
|
||||||
|
/** \brief Attribute for non-cacheable, normal memory */
|
||||||
|
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
|
||||||
|
|
||||||
|
/** \brief Attribute for normal memory (outer and inner)
|
||||||
|
* \param NT Non-Transient: Set to 1 for non-transient data.
|
||||||
|
* \param WB Write-Back: Set to 1 to use write-back update policy.
|
||||||
|
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
|
||||||
|
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
|
||||||
|
(((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
|
||||||
|
|
||||||
|
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
|
||||||
|
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
|
||||||
|
|
||||||
|
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
|
||||||
|
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
|
||||||
|
|
||||||
|
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
|
||||||
|
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
|
||||||
|
|
||||||
|
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
|
||||||
|
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
|
||||||
|
|
||||||
|
/** \brief Memory Attribute
|
||||||
|
* \param O Outer memory attributes
|
||||||
|
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
|
||||||
|
|
||||||
|
/** \brief Normal memory non-shareable */
|
||||||
|
#define ARM_MPU_SH_NON (0U)
|
||||||
|
|
||||||
|
/** \brief Normal memory outer shareable */
|
||||||
|
#define ARM_MPU_SH_OUTER (2U)
|
||||||
|
|
||||||
|
/** \brief Normal memory inner shareable */
|
||||||
|
#define ARM_MPU_SH_INNER (3U)
|
||||||
|
|
||||||
|
/** \brief Memory access permissions
|
||||||
|
* \param RO Read-Only: Set to 1 for read-only memory.
|
||||||
|
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
|
||||||
|
|
||||||
|
/** \brief Region Base Address Register value
|
||||||
|
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
|
||||||
|
* \param SH Defines the Shareability domain for this memory region.
|
||||||
|
* \param RO Read-Only: Set to 1 for a read-only memory region.
|
||||||
|
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
|
||||||
|
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
|
||||||
|
((BASE & MPU_RBAR_BASE_Msk) | \
|
||||||
|
((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
|
||||||
|
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
||||||
|
((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
|
||||||
|
|
||||||
|
/** \brief Region Limit Address Register value
|
||||||
|
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||||
|
* \param IDX The attribute index to be associated with this memory region.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_RLAR(LIMIT, IDX) \
|
||||||
|
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
|
||||||
|
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||||
|
(MPU_RLAR_EN_Msk))
|
||||||
|
|
||||||
|
#if defined(MPU_RLAR_PXN_Pos)
|
||||||
|
|
||||||
|
/** \brief Region Limit Address Register with PXN value
|
||||||
|
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||||
|
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
|
||||||
|
* \param IDX The attribute index to be associated with this memory region.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
|
||||||
|
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
|
||||||
|
((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
|
||||||
|
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||||
|
(MPU_RLAR_EN_Msk))
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Struct for a single MPU Region
|
||||||
|
*/
|
||||||
|
typedef struct {
|
||||||
|
uint32_t RBAR; /*!< Region Base Address Register value */
|
||||||
|
uint32_t RLAR; /*!< Region Limit Address Register value */
|
||||||
|
} ARM_MPU_Region_t;
|
||||||
|
|
||||||
|
/** Enable the MPU.
|
||||||
|
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||||
|
{
|
||||||
|
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||||
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
|
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
|
#endif
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Disable the MPU.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||||
|
{
|
||||||
|
__DMB();
|
||||||
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
|
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
|
#endif
|
||||||
|
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef MPU_NS
|
||||||
|
/** Enable the Non-secure MPU.
|
||||||
|
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
|
||||||
|
{
|
||||||
|
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||||
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
|
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
|
#endif
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Disable the Non-secure MPU.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
|
||||||
|
{
|
||||||
|
__DMB();
|
||||||
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
|
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
|
#endif
|
||||||
|
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** Set the memory attribute encoding to the given MPU.
|
||||||
|
* \param mpu Pointer to the MPU to be configured.
|
||||||
|
* \param idx The attribute index to be set [0-7]
|
||||||
|
* \param attr The attribute value to be set.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
|
||||||
|
{
|
||||||
|
const uint8_t reg = idx / 4U;
|
||||||
|
const uint32_t pos = ((idx % 4U) * 8U);
|
||||||
|
const uint32_t mask = 0xFFU << pos;
|
||||||
|
|
||||||
|
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
|
||||||
|
return; // invalid index
|
||||||
|
}
|
||||||
|
|
||||||
|
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Set the memory attribute encoding.
|
||||||
|
* \param idx The attribute index to be set [0-7]
|
||||||
|
* \param attr The attribute value to be set.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
|
||||||
|
{
|
||||||
|
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef MPU_NS
|
||||||
|
/** Set the memory attribute encoding to the Non-secure MPU.
|
||||||
|
* \param idx The attribute index to be set [0-7]
|
||||||
|
* \param attr The attribute value to be set.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
|
||||||
|
{
|
||||||
|
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** Clear and disable the given MPU region of the given MPU.
|
||||||
|
* \param mpu Pointer to MPU to be used.
|
||||||
|
* \param rnr Region number to be cleared.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
|
||||||
|
{
|
||||||
|
mpu->RNR = rnr;
|
||||||
|
mpu->RLAR = 0U;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Clear and disable the given MPU region.
|
||||||
|
* \param rnr Region number to be cleared.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||||
|
{
|
||||||
|
ARM_MPU_ClrRegionEx(MPU, rnr);
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef MPU_NS
|
||||||
|
/** Clear and disable the given Non-secure MPU region.
|
||||||
|
* \param rnr Region number to be cleared.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
|
||||||
|
{
|
||||||
|
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** Configure the given MPU region of the given MPU.
|
||||||
|
* \param mpu Pointer to MPU to be used.
|
||||||
|
* \param rnr Region number to be configured.
|
||||||
|
* \param rbar Value for RBAR register.
|
||||||
|
* \param rlar Value for RLAR register.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||||
|
{
|
||||||
|
mpu->RNR = rnr;
|
||||||
|
mpu->RBAR = rbar;
|
||||||
|
mpu->RLAR = rlar;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Configure the given MPU region.
|
||||||
|
* \param rnr Region number to be configured.
|
||||||
|
* \param rbar Value for RBAR register.
|
||||||
|
* \param rlar Value for RLAR register.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||||
|
{
|
||||||
|
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef MPU_NS
|
||||||
|
/** Configure the given Non-secure MPU region.
|
||||||
|
* \param rnr Region number to be configured.
|
||||||
|
* \param rbar Value for RBAR register.
|
||||||
|
* \param rlar Value for RLAR register.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||||
|
{
|
||||||
|
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||||
|
* \param dst Destination data is copied to.
|
||||||
|
* \param src Source data is copied from.
|
||||||
|
* \param len Amount of data words to be copied.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||||
|
{
|
||||||
|
uint32_t i;
|
||||||
|
for (i = 0U; i < len; ++i)
|
||||||
|
{
|
||||||
|
dst[i] = src[i];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Load the given number of MPU regions from a table to the given MPU.
|
||||||
|
* \param mpu Pointer to the MPU registers to be used.
|
||||||
|
* \param rnr First region number to be configured.
|
||||||
|
* \param table Pointer to the MPU configuration table.
|
||||||
|
* \param cnt Amount of regions to be configured.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||||
|
{
|
||||||
|
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||||
|
if (cnt == 1U) {
|
||||||
|
mpu->RNR = rnr;
|
||||||
|
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
|
||||||
|
} else {
|
||||||
|
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
|
||||||
|
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
|
||||||
|
|
||||||
|
mpu->RNR = rnrBase;
|
||||||
|
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
|
||||||
|
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
|
||||||
|
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
|
||||||
|
table += c;
|
||||||
|
cnt -= c;
|
||||||
|
rnrOffset = 0U;
|
||||||
|
rnrBase += MPU_TYPE_RALIASES;
|
||||||
|
mpu->RNR = rnrBase;
|
||||||
|
}
|
||||||
|
|
||||||
|
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Load the given number of MPU regions from a table.
|
||||||
|
* \param rnr First region number to be configured.
|
||||||
|
* \param table Pointer to the MPU configuration table.
|
||||||
|
* \param cnt Amount of regions to be configured.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||||
|
{
|
||||||
|
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef MPU_NS
|
||||||
|
/** Load the given number of MPU regions from a table to the Non-secure MPU.
|
||||||
|
* \param rnr First region number to be configured.
|
||||||
|
* \param table Pointer to the MPU configuration table.
|
||||||
|
* \param cnt Amount of regions to be configured.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||||
|
{
|
||||||
|
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
70
Boot/Drivers/CMSIS/Include/tz_context.h
Normal file
70
Boot/Drivers/CMSIS/Include/tz_context.h
Normal file
@@ -0,0 +1,70 @@
|
|||||||
|
/******************************************************************************
|
||||||
|
* @file tz_context.h
|
||||||
|
* @brief Context Management for Armv8-M TrustZone
|
||||||
|
* @version V1.0.1
|
||||||
|
* @date 10. January 2018
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#elif defined (__clang__)
|
||||||
|
#pragma clang system_header /* treat file as system include file */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef TZ_CONTEXT_H
|
||||||
|
#define TZ_CONTEXT_H
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
#ifndef TZ_MODULEID_T
|
||||||
|
#define TZ_MODULEID_T
|
||||||
|
/// \details Data type that identifies secure software modules called by a process.
|
||||||
|
typedef uint32_t TZ_ModuleId_t;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/// \details TZ Memory ID identifies an allocated memory slot.
|
||||||
|
typedef uint32_t TZ_MemoryId_t;
|
||||||
|
|
||||||
|
/// Initialize secure context memory system
|
||||||
|
/// \return execution status (1: success, 0: error)
|
||||||
|
uint32_t TZ_InitContextSystem_S (void);
|
||||||
|
|
||||||
|
/// Allocate context memory for calling secure software modules in TrustZone
|
||||||
|
/// \param[in] module identifies software modules called from non-secure mode
|
||||||
|
/// \return value != 0 id TrustZone memory slot identifier
|
||||||
|
/// \return value 0 no memory available or internal error
|
||||||
|
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
|
||||||
|
|
||||||
|
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
|
||||||
|
/// \param[in] id TrustZone memory slot identifier
|
||||||
|
/// \return execution status (1: success, 0: error)
|
||||||
|
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
|
||||||
|
|
||||||
|
/// Load secure context (called on RTOS thread context switch)
|
||||||
|
/// \param[in] id TrustZone memory slot identifier
|
||||||
|
/// \return execution status (1: success, 0: error)
|
||||||
|
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
|
||||||
|
|
||||||
|
/// Store secure context (called on RTOS thread context switch)
|
||||||
|
/// \param[in] id TrustZone memory slot identifier
|
||||||
|
/// \return execution status (1: success, 0: error)
|
||||||
|
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
|
||||||
|
|
||||||
|
#endif // TZ_CONTEXT_H
|
||||||
201
Boot/Drivers/CMSIS/LICENSE.txt
Normal file
201
Boot/Drivers/CMSIS/LICENSE.txt
Normal file
@@ -0,0 +1,201 @@
|
|||||||
|
Apache License
|
||||||
|
Version 2.0, January 2004
|
||||||
|
http://www.apache.org/licenses/
|
||||||
|
|
||||||
|
TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
|
||||||
|
|
||||||
|
1. Definitions.
|
||||||
|
|
||||||
|
"License" shall mean the terms and conditions for use, reproduction,
|
||||||
|
and distribution as defined by Sections 1 through 9 of this document.
|
||||||
|
|
||||||
|
"Licensor" shall mean the copyright owner or entity authorized by
|
||||||
|
the copyright owner that is granting the License.
|
||||||
|
|
||||||
|
"Legal Entity" shall mean the union of the acting entity and all
|
||||||
|
other entities that control, are controlled by, or are under common
|
||||||
|
control with that entity. For the purposes of this definition,
|
||||||
|
"control" means (i) the power, direct or indirect, to cause the
|
||||||
|
direction or management of such entity, whether by contract or
|
||||||
|
otherwise, or (ii) ownership of fifty percent (50%) or more of the
|
||||||
|
outstanding shares, or (iii) beneficial ownership of such entity.
|
||||||
|
|
||||||
|
"You" (or "Your") shall mean an individual or Legal Entity
|
||||||
|
exercising permissions granted by this License.
|
||||||
|
|
||||||
|
"Source" form shall mean the preferred form for making modifications,
|
||||||
|
including but not limited to software source code, documentation
|
||||||
|
source, and configuration files.
|
||||||
|
|
||||||
|
"Object" form shall mean any form resulting from mechanical
|
||||||
|
transformation or translation of a Source form, including but
|
||||||
|
not limited to compiled object code, generated documentation,
|
||||||
|
and conversions to other media types.
|
||||||
|
|
||||||
|
"Work" shall mean the work of authorship, whether in Source or
|
||||||
|
Object form, made available under the License, as indicated by a
|
||||||
|
copyright notice that is included in or attached to the work
|
||||||
|
(an example is provided in the Appendix below).
|
||||||
|
|
||||||
|
"Derivative Works" shall mean any work, whether in Source or Object
|
||||||
|
form, that is based on (or derived from) the Work and for which the
|
||||||
|
editorial revisions, annotations, elaborations, or other modifications
|
||||||
|
represent, as a whole, an original work of authorship. For the purposes
|
||||||
|
of this License, Derivative Works shall not include works that remain
|
||||||
|
separable from, or merely link (or bind by name) to the interfaces of,
|
||||||
|
the Work and Derivative Works thereof.
|
||||||
|
|
||||||
|
"Contribution" shall mean any work of authorship, including
|
||||||
|
the original version of the Work and any modifications or additions
|
||||||
|
to that Work or Derivative Works thereof, that is intentionally
|
||||||
|
submitted to Licensor for inclusion in the Work by the copyright owner
|
||||||
|
or by an individual or Legal Entity authorized to submit on behalf of
|
||||||
|
the copyright owner. For the purposes of this definition, "submitted"
|
||||||
|
means any form of electronic, verbal, or written communication sent
|
||||||
|
to the Licensor or its representatives, including but not limited to
|
||||||
|
communication on electronic mailing lists, source code control systems,
|
||||||
|
and issue tracking systems that are managed by, or on behalf of, the
|
||||||
|
Licensor for the purpose of discussing and improving the Work, but
|
||||||
|
excluding communication that is conspicuously marked or otherwise
|
||||||
|
designated in writing by the copyright owner as "Not a Contribution."
|
||||||
|
|
||||||
|
"Contributor" shall mean Licensor and any individual or Legal Entity
|
||||||
|
on behalf of whom a Contribution has been received by Licensor and
|
||||||
|
subsequently incorporated within the Work.
|
||||||
|
|
||||||
|
2. Grant of Copyright License. Subject to the terms and conditions of
|
||||||
|
this License, each Contributor hereby grants to You a perpetual,
|
||||||
|
worldwide, non-exclusive, no-charge, royalty-free, irrevocable
|
||||||
|
copyright license to reproduce, prepare Derivative Works of,
|
||||||
|
publicly display, publicly perform, sublicense, and distribute the
|
||||||
|
Work and such Derivative Works in Source or Object form.
|
||||||
|
|
||||||
|
3. Grant of Patent License. Subject to the terms and conditions of
|
||||||
|
this License, each Contributor hereby grants to You a perpetual,
|
||||||
|
worldwide, non-exclusive, no-charge, royalty-free, irrevocable
|
||||||
|
(except as stated in this section) patent license to make, have made,
|
||||||
|
use, offer to sell, sell, import, and otherwise transfer the Work,
|
||||||
|
where such license applies only to those patent claims licensable
|
||||||
|
by such Contributor that are necessarily infringed by their
|
||||||
|
Contribution(s) alone or by combination of their Contribution(s)
|
||||||
|
with the Work to which such Contribution(s) was submitted. If You
|
||||||
|
institute patent litigation against any entity (including a
|
||||||
|
cross-claim or counterclaim in a lawsuit) alleging that the Work
|
||||||
|
or a Contribution incorporated within the Work constitutes direct
|
||||||
|
or contributory patent infringement, then any patent licenses
|
||||||
|
granted to You under this License for that Work shall terminate
|
||||||
|
as of the date such litigation is filed.
|
||||||
|
|
||||||
|
4. Redistribution. You may reproduce and distribute copies of the
|
||||||
|
Work or Derivative Works thereof in any medium, with or without
|
||||||
|
modifications, and in Source or Object form, provided that You
|
||||||
|
meet the following conditions:
|
||||||
|
|
||||||
|
(a) You must give any other recipients of the Work or
|
||||||
|
Derivative Works a copy of this License; and
|
||||||
|
|
||||||
|
(b) You must cause any modified files to carry prominent notices
|
||||||
|
stating that You changed the files; and
|
||||||
|
|
||||||
|
(c) You must retain, in the Source form of any Derivative Works
|
||||||
|
that You distribute, all copyright, patent, trademark, and
|
||||||
|
attribution notices from the Source form of the Work,
|
||||||
|
excluding those notices that do not pertain to any part of
|
||||||
|
the Derivative Works; and
|
||||||
|
|
||||||
|
(d) If the Work includes a "NOTICE" text file as part of its
|
||||||
|
distribution, then any Derivative Works that You distribute must
|
||||||
|
include a readable copy of the attribution notices contained
|
||||||
|
within such NOTICE file, excluding those notices that do not
|
||||||
|
pertain to any part of the Derivative Works, in at least one
|
||||||
|
of the following places: within a NOTICE text file distributed
|
||||||
|
as part of the Derivative Works; within the Source form or
|
||||||
|
documentation, if provided along with the Derivative Works; or,
|
||||||
|
within a display generated by the Derivative Works, if and
|
||||||
|
wherever such third-party notices normally appear. The contents
|
||||||
|
of the NOTICE file are for informational purposes only and
|
||||||
|
do not modify the License. You may add Your own attribution
|
||||||
|
notices within Derivative Works that You distribute, alongside
|
||||||
|
or as an addendum to the NOTICE text from the Work, provided
|
||||||
|
that such additional attribution notices cannot be construed
|
||||||
|
as modifying the License.
|
||||||
|
|
||||||
|
You may add Your own copyright statement to Your modifications and
|
||||||
|
may provide additional or different license terms and conditions
|
||||||
|
for use, reproduction, or distribution of Your modifications, or
|
||||||
|
for any such Derivative Works as a whole, provided Your use,
|
||||||
|
reproduction, and distribution of the Work otherwise complies with
|
||||||
|
the conditions stated in this License.
|
||||||
|
|
||||||
|
5. Submission of Contributions. Unless You explicitly state otherwise,
|
||||||
|
any Contribution intentionally submitted for inclusion in the Work
|
||||||
|
by You to the Licensor shall be under the terms and conditions of
|
||||||
|
this License, without any additional terms or conditions.
|
||||||
|
Notwithstanding the above, nothing herein shall supersede or modify
|
||||||
|
the terms of any separate license agreement you may have executed
|
||||||
|
with Licensor regarding such Contributions.
|
||||||
|
|
||||||
|
6. Trademarks. This License does not grant permission to use the trade
|
||||||
|
names, trademarks, service marks, or product names of the Licensor,
|
||||||
|
except as required for reasonable and customary use in describing the
|
||||||
|
origin of the Work and reproducing the content of the NOTICE file.
|
||||||
|
|
||||||
|
7. Disclaimer of Warranty. Unless required by applicable law or
|
||||||
|
agreed to in writing, Licensor provides the Work (and each
|
||||||
|
Contributor provides its Contributions) on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
|
||||||
|
implied, including, without limitation, any warranties or conditions
|
||||||
|
of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A
|
||||||
|
PARTICULAR PURPOSE. You are solely responsible for determining the
|
||||||
|
appropriateness of using or redistributing the Work and assume any
|
||||||
|
risks associated with Your exercise of permissions under this License.
|
||||||
|
|
||||||
|
8. Limitation of Liability. In no event and under no legal theory,
|
||||||
|
whether in tort (including negligence), contract, or otherwise,
|
||||||
|
unless required by applicable law (such as deliberate and grossly
|
||||||
|
negligent acts) or agreed to in writing, shall any Contributor be
|
||||||
|
liable to You for damages, including any direct, indirect, special,
|
||||||
|
incidental, or consequential damages of any character arising as a
|
||||||
|
result of this License or out of the use or inability to use the
|
||||||
|
Work (including but not limited to damages for loss of goodwill,
|
||||||
|
work stoppage, computer failure or malfunction, or any and all
|
||||||
|
other commercial damages or losses), even if such Contributor
|
||||||
|
has been advised of the possibility of such damages.
|
||||||
|
|
||||||
|
9. Accepting Warranty or Additional Liability. While redistributing
|
||||||
|
the Work or Derivative Works thereof, You may choose to offer,
|
||||||
|
and charge a fee for, acceptance of support, warranty, indemnity,
|
||||||
|
or other liability obligations and/or rights consistent with this
|
||||||
|
License. However, in accepting such obligations, You may act only
|
||||||
|
on Your own behalf and on Your sole responsibility, not on behalf
|
||||||
|
of any other Contributor, and only if You agree to indemnify,
|
||||||
|
defend, and hold each Contributor harmless for any liability
|
||||||
|
incurred by, or claims asserted against, such Contributor by reason
|
||||||
|
of your accepting any such warranty or additional liability.
|
||||||
|
|
||||||
|
END OF TERMS AND CONDITIONS
|
||||||
|
|
||||||
|
APPENDIX: How to apply the Apache License to your work.
|
||||||
|
|
||||||
|
To apply the Apache License to your work, attach the following
|
||||||
|
boilerplate notice, with the fields enclosed by brackets "{}"
|
||||||
|
replaced with your own identifying information. (Don't include
|
||||||
|
the brackets!) The text should be enclosed in the appropriate
|
||||||
|
comment syntax for the file format. We also recommend that a
|
||||||
|
file or class name and description of purpose be included on the
|
||||||
|
same "printed page" as the copyright notice for easier
|
||||||
|
identification within third-party archives.
|
||||||
|
|
||||||
|
Copyright {yyyy} {name of copyright owner}
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
||||||
4014
Boot/Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
Normal file
4014
Boot/Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
Normal file
File diff suppressed because it is too large
Load Diff
838
Boot/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h
Normal file
838
Boot/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h
Normal file
@@ -0,0 +1,838 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32g0xx_hal.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @brief This file contains all the functions prototypes for the HAL
|
||||||
|
* module driver.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* Copyright (c) 2018 STMicroelectronics.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* This software is licensed under terms that can be found in the LICENSE file
|
||||||
|
* in the root directory of this software component.
|
||||||
|
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef STM32G0xx_HAL_H
|
||||||
|
#define STM32G0xx_HAL_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32g0xx_hal_conf.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32G0xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup HAL HAL
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
/** @defgroup HAL_TICK_FREQ Tick Frequency
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_TICK_FREQ_10HZ = 100U,
|
||||||
|
HAL_TICK_FREQ_100HZ = 10U,
|
||||||
|
HAL_TICK_FREQ_1KHZ = 1U,
|
||||||
|
HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
|
||||||
|
} HAL_TickFreqTypeDef;
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/** @defgroup HAL_Exported_Constants HAL Exported Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SYSCFG_BootMode Boot Mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define SYSCFG_BOOT_MAINFLASH 0x00000000U /*!< Main Flash memory mapped at 0x0000 0000 */
|
||||||
|
#define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /*!< System Flash memory mapped at 0x0000 0000 */
|
||||||
|
#define SYSCFG_BOOT_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /*!< Embedded SRAM mapped at 0x0000 0000 */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SYSCFG_Break Break
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define SYSCFG_BREAK_SP SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM Parity error signal with Break Input of TIM1/15/16/17 */
|
||||||
|
#if defined(SYSCFG_CFGR2_PVDL)
|
||||||
|
#define SYSCFG_BREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */
|
||||||
|
#endif /* SYSCFG_CFGR2_PVDL */
|
||||||
|
#define SYSCFG_BREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM0+ with Break Input of TIM1/15/16/17 */
|
||||||
|
#define SYSCFG_BREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC of CortexM0+ with Break Input of TIM1/15/16/17 */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined(SYSCFG_CDEN_SUPPORT)
|
||||||
|
/** @defgroup SYSCFG_ClampingDiode Clamping Diode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define SYSCFG_CDEN_PA1 SYSCFG_CFGR2_PA1_CDEN /*!< Enables Clamping Diode on PA1 */
|
||||||
|
#define SYSCFG_CDEN_PA3 SYSCFG_CFGR2_PA3_CDEN /*!< Enables Clamping Diode on PA3 */
|
||||||
|
#define SYSCFG_CDEN_PA5 SYSCFG_CFGR2_PA5_CDEN /*!< Enables Clamping Diode on PA5 */
|
||||||
|
#define SYSCFG_CDEN_PA6 SYSCFG_CFGR2_PA6_CDEN /*!< Enables Clamping Diode on PA6 */
|
||||||
|
#define SYSCFG_CDEN_PA13 SYSCFG_CFGR2_PA13_CDEN /*!< Enables Clamping Diode on PA13 */
|
||||||
|
#define SYSCFG_CDEN_PB0 SYSCFG_CFGR2_PB0_CDEN /*!< Enables Clamping Diode on PB0 */
|
||||||
|
#define SYSCFG_CDEN_PB1 SYSCFG_CFGR2_PB1_CDEN /*!< Enables Clamping Diode on PB1 */
|
||||||
|
#define SYSCFG_CDEN_PB2 SYSCFG_CFGR2_PB2_CDEN /*!< Enables Clamping Diode on PB2 */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
#endif /* SYSCFG_CDEN_SUPPORT */
|
||||||
|
|
||||||
|
/** @defgroup HAL_Pin_remapping Pin remapping
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Only available on cut2.0 */
|
||||||
|
#define SYSCFG_REMAP_PA11 SYSCFG_CFGR1_PA11_RMP /*!< PA11 pad behaves digitally as PA9 GPIO pin */
|
||||||
|
#define SYSCFG_REMAP_PA12 SYSCFG_CFGR1_PA12_RMP /*!< PA12 pad behaves digitally as PA10 GPIO pin */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup HAL_IR_ENV_SEL IR Modulation Envelope signal selection
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define HAL_SYSCFG_IRDA_ENV_SEL_TIM16 (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1) /*!< 00: Timer16 is selected as IR Modulation envelope source */
|
||||||
|
#define HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IR_MOD_0) /*!< 01: USART1 is selected as IR Modulation envelope source */
|
||||||
|
#if defined(USART4)
|
||||||
|
#define HAL_SYSCFG_IRDA_ENV_SEL_USART4 (SYSCFG_CFGR1_IR_MOD_1) /*!< 10: USART4 is selected as IR Modulation envelope source */
|
||||||
|
#else
|
||||||
|
#define HAL_SYSCFG_IRDA_ENV_SEL_USART2 (SYSCFG_CFGR1_IR_MOD_1) /*!< 10: USART2 is selected as IR Modulation envelope source */
|
||||||
|
#endif /* USART4 */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup HAL_IR_POL_SEL IR output polarity selection
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define HAL_SYSCFG_IRDA_POLARITY_NOT_INVERTED 0x00000000U /*!< 00: IR output polarity not inverted */
|
||||||
|
#define HAL_SYSCFG_IRDA_POLARITY_INVERTED SYSCFG_CFGR1_IR_POL /*!< 01: IR output polarity inverted */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined(VREFBUF)
|
||||||
|
/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 0x00000000U /*!< Voltage reference scale 0: VREF_OUT1 around 2.048 V.
|
||||||
|
This requires VDDA equal to or higher than 2.4 V. */
|
||||||
|
#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1: VREF_OUT1 around 2.5 V.
|
||||||
|
This requires VDDA equal to or higher than 2.8 V. */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0x00000000U /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
|
||||||
|
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
#endif /* VREFBUF */
|
||||||
|
|
||||||
|
/** @defgroup SYSCFG_FastModePlus_GPIO Fast mode Plus on GPIO
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @brief Fast mode Plus driving capability on a specific GPIO
|
||||||
|
*/
|
||||||
|
#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast mode Plus on PB6 */
|
||||||
|
#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast mode Plus on PB7 */
|
||||||
|
#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast mode Plus on PB8 */
|
||||||
|
#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast mode Plus on PB9 */
|
||||||
|
#define SYSCFG_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_PA9_FMP /*!< Enable Fast mode Plus on PA9 */
|
||||||
|
#define SYSCFG_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_PA10_FMP /*!< Enable Fast mode Plus on PA10 */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SYSCFG_FastModePlus_I2Cx Fast mode Plus driving capability activation for I2Cx
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @brief Fast mode Plus driving capability on a specific GPIO
|
||||||
|
*/
|
||||||
|
#define SYSCFG_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast mode Plus on I2C1 */
|
||||||
|
#define SYSCFG_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast mode Plus on I2C2 */
|
||||||
|
#if defined (I2C3)
|
||||||
|
#define SYSCFG_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast mode Plus on I2C3 */
|
||||||
|
#endif /* I2C3 */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
#if defined (SYSCFG_CFGR1_UCPD1_STROBE) || defined (SYSCFG_CFGR1_UCPD2_STROBE)
|
||||||
|
/** @defgroup SYSCFG_UCPDx_STROBE SYSCFG Dead Battery feature configuration
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define SYSCFG_UCPD1_STROBE SYSCFG_CFGR1_UCPD1_STROBE /*!< UCPD1 Dead battery sw configuration */
|
||||||
|
#define SYSCFG_UCPD2_STROBE SYSCFG_CFGR1_UCPD2_STROBE /*!< UCPD2 Dead battery sw configuration */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
#endif /* SYSCFG_CFGR1_UCPD1_STROBE) || SYSCFG_CFGR1_UCPD2_STROBE */
|
||||||
|
|
||||||
|
/** @defgroup HAL_ISR_Wrapper HAL ISR Wrapper
|
||||||
|
* @brief ISR Wrapper
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define HAL_SYSCFG_ITLINE0 0x00000000U /*!< Internal define for macro handling */
|
||||||
|
#define HAL_SYSCFG_ITLINE1 0x00000001U /*!< Internal define for macro handling */
|
||||||
|
#define HAL_SYSCFG_ITLINE2 0x00000002U /*!< Internal define for macro handling */
|
||||||
|
#define HAL_SYSCFG_ITLINE3 0x00000003U /*!< Internal define for macro handling */
|
||||||
|
#define HAL_SYSCFG_ITLINE4 0x00000004U /*!< Internal define for macro handling */
|
||||||
|
#define HAL_SYSCFG_ITLINE5 0x00000005U /*!< Internal define for macro handling */
|
||||||
|
#define HAL_SYSCFG_ITLINE6 0x00000006U /*!< Internal define for macro handling */
|
||||||
|
#define HAL_SYSCFG_ITLINE7 0x00000007U /*!< Internal define for macro handling */
|
||||||
|
#define HAL_SYSCFG_ITLINE8 0x00000008U /*!< Internal define for macro handling */
|
||||||
|
#define HAL_SYSCFG_ITLINE9 0x00000009U /*!< Internal define for macro handling */
|
||||||
|
#define HAL_SYSCFG_ITLINE10 0x0000000AU /*!< Internal define for macro handling */
|
||||||
|
#define HAL_SYSCFG_ITLINE11 0x0000000BU /*!< Internal define for macro handling */
|
||||||
|
#define HAL_SYSCFG_ITLINE12 0x0000000CU /*!< Internal define for macro handling */
|
||||||
|
#define HAL_SYSCFG_ITLINE13 0x0000000DU /*!< Internal define for macro handling */
|
||||||
|
#define HAL_SYSCFG_ITLINE14 0x0000000EU /*!< Internal define for macro handling */
|
||||||
|
#define HAL_SYSCFG_ITLINE15 0x0000000FU /*!< Internal define for macro handling */
|
||||||
|
#define HAL_SYSCFG_ITLINE16 0x00000010U /*!< Internal define for macro handling */
|
||||||
|
#define HAL_SYSCFG_ITLINE17 0x00000011U /*!< Internal define for macro handling */
|
||||||
|
#define HAL_SYSCFG_ITLINE18 0x00000012U /*!< Internal define for macro handling */
|
||||||
|
#define HAL_SYSCFG_ITLINE19 0x00000013U /*!< Internal define for macro handling */
|
||||||
|
#define HAL_SYSCFG_ITLINE20 0x00000014U /*!< Internal define for macro handling */
|
||||||
|
#define HAL_SYSCFG_ITLINE21 0x00000015U /*!< Internal define for macro handling */
|
||||||
|
#define HAL_SYSCFG_ITLINE22 0x00000016U /*!< Internal define for macro handling */
|
||||||
|
#define HAL_SYSCFG_ITLINE23 0x00000017U /*!< Internal define for macro handling */
|
||||||
|
#define HAL_SYSCFG_ITLINE24 0x00000018U /*!< Internal define for macro handling */
|
||||||
|
#define HAL_SYSCFG_ITLINE25 0x00000019U /*!< Internal define for macro handling */
|
||||||
|
#define HAL_SYSCFG_ITLINE26 0x0000001AU /*!< Internal define for macro handling */
|
||||||
|
#define HAL_SYSCFG_ITLINE27 0x0000001BU /*!< Internal define for macro handling */
|
||||||
|
#define HAL_SYSCFG_ITLINE28 0x0000001CU /*!< Internal define for macro handling */
|
||||||
|
#define HAL_SYSCFG_ITLINE29 0x0000001DU /*!< Internal define for macro handling */
|
||||||
|
#define HAL_SYSCFG_ITLINE30 0x0000001EU /*!< Internal define for macro handling */
|
||||||
|
#define HAL_SYSCFG_ITLINE31 0x0000001FU /*!< Internal define for macro handling */
|
||||||
|
|
||||||
|
#define HAL_ITLINE_WWDG ((HAL_SYSCFG_ITLINE0 << 0x18U) | SYSCFG_ITLINE0_SR_EWDG) /*!< WWDG has expired .... */
|
||||||
|
#if defined (PWR_PVD_SUPPORT)
|
||||||
|
#define HAL_ITLINE_PVDOUT ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_PVDOUT) /*!< Power voltage detection Interrupt .... */
|
||||||
|
#endif /* PWR_PVD_SUPPORT */
|
||||||
|
#if defined (PWR_PVM_SUPPORT)
|
||||||
|
#define HAL_ITLINE_PVMOUT ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_PVMOUT) /*!< Power voltage monitor Interrupt .... */
|
||||||
|
#endif /* PWR_PVM_SUPPORT */
|
||||||
|
#define HAL_ITLINE_RTC ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC) /*!< RTC -> exti[19] Interrupt */
|
||||||
|
#define HAL_ITLINE_TAMPER ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_TAMPER) /*!< TAMPER -> exti[21] interrupt .... */
|
||||||
|
#define HAL_ITLINE_FLASH_ECC ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ECC) /*!< Flash ECC Interrupt */
|
||||||
|
#define HAL_ITLINE_FLASH_ITF ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ITF) /*!< Flash ITF Interrupt */
|
||||||
|
#define HAL_ITLINE_CLK_CTRL ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CLK_CTRL) /*!< CLK Control Interrupt */
|
||||||
|
#if defined (CRS)
|
||||||
|
#define HAL_ITLINE_CRS ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CRS) /*!< CRS Interrupt */
|
||||||
|
#endif /*CRS */
|
||||||
|
#define HAL_ITLINE_EXTI0 ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI0) /*!< External Interrupt 0 */
|
||||||
|
#define HAL_ITLINE_EXTI1 ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI1) /*!< External Interrupt 1 */
|
||||||
|
#define HAL_ITLINE_EXTI2 ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI2) /*!< External Interrupt 2 */
|
||||||
|
#define HAL_ITLINE_EXTI3 ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI3) /*!< External Interrupt 3 */
|
||||||
|
#define HAL_ITLINE_EXTI4 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI4) /*!< EXTI4 Interrupt */
|
||||||
|
#define HAL_ITLINE_EXTI5 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI5) /*!< EXTI5 Interrupt */
|
||||||
|
#define HAL_ITLINE_EXTI6 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI6) /*!< EXTI6 Interrupt */
|
||||||
|
#define HAL_ITLINE_EXTI7 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI7) /*!< EXTI7 Interrupt */
|
||||||
|
#define HAL_ITLINE_EXTI8 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI8) /*!< EXTI8 Interrupt */
|
||||||
|
#define HAL_ITLINE_EXTI9 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI9) /*!< EXTI9 Interrupt */
|
||||||
|
#define HAL_ITLINE_EXTI10 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI10) /*!< EXTI10 Interrupt */
|
||||||
|
#define HAL_ITLINE_EXTI11 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI11) /*!< EXTI11 Interrupt */
|
||||||
|
#define HAL_ITLINE_EXTI12 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI12) /*!< EXTI12 Interrupt */
|
||||||
|
#define HAL_ITLINE_EXTI13 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI13) /*!< EXTI13 Interrupt */
|
||||||
|
#define HAL_ITLINE_EXTI14 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI14) /*!< EXTI14 Interrupt */
|
||||||
|
#define HAL_ITLINE_EXTI15 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI15) /*!< EXTI15 Interrupt */
|
||||||
|
#if defined (UCPD1)
|
||||||
|
#define HAL_ITLINE_UCPD1 ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_UCPD1) /*!< UCPD1 Interrupt */
|
||||||
|
#endif /* UCPD1 */
|
||||||
|
#if defined (UCPD2)
|
||||||
|
#define HAL_ITLINE_UCPD2 ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_UCPD2) /*!< UCPD2 Interrupt */
|
||||||
|
#endif /* UCPD2 */
|
||||||
|
#if defined (STM32G0C1xx) || defined (STM32G0B1xx) || defined (STM32G0B0xx)
|
||||||
|
#define HAL_ITLINE_USB ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_USB) /*!< USB Interrupt */
|
||||||
|
#endif /* STM32G0C1xx) || STM32G0B1xx) || STM32G0B0xx */
|
||||||
|
#define HAL_ITLINE_DMA1_CH1 ((HAL_SYSCFG_ITLINE9 << 0x18U) | SYSCFG_ITLINE9_SR_DMA1_CH1) /*!< DMA1 Channel 1 Interrupt */
|
||||||
|
#define HAL_ITLINE_DMA1_CH2 ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH2) /*!< DMA1 Channel 2 Interrupt */
|
||||||
|
#define HAL_ITLINE_DMA1_CH3 ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH3) /*!< DMA1 Channel 3 Interrupt */
|
||||||
|
#define HAL_ITLINE_DMAMUX1 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMAMUX1) /*!< DMAMUX1 Interrupt */
|
||||||
|
#define HAL_ITLINE_DMA1_CH4 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH4) /*!< DMA1 Channel 4 Interrupt */
|
||||||
|
#define HAL_ITLINE_DMA1_CH5 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH5) /*!< DMA1 Channel 5 Interrupt */
|
||||||
|
#if defined(DMA1_Channel7)
|
||||||
|
#define HAL_ITLINE_DMA1_CH6 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH6) /*!< DMA1 Channel 6 Interrupt */
|
||||||
|
#define HAL_ITLINE_DMA1_CH7 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH7) /*!< DMA1 Channel 7 Interrupt */
|
||||||
|
#endif /* DMA1_Channel7 */
|
||||||
|
#if defined (DMA2)
|
||||||
|
#define HAL_ITLINE_DMA2_CH1 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH1) /*!< DMA2 Channel 1 Interrupt */
|
||||||
|
#define HAL_ITLINE_DMA2_CH2 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH2) /*!< DMA2 Channel 2 Interrupt */
|
||||||
|
#define HAL_ITLINE_DMA2_CH3 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH3) /*!< DMA2 Channel 3 Interrupt */
|
||||||
|
#define HAL_ITLINE_DMA2_CH4 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH4) /*!< DMA2 Channel 4 Interrupt */
|
||||||
|
#define HAL_ITLINE_DMA2_CH5 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH5) /*!< DMA2 Channel 5 Interrupt */
|
||||||
|
#endif /* DMA2 */
|
||||||
|
#define HAL_ITLINE_ADC ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_ADC) /*!< ADC Interrupt */
|
||||||
|
#if defined (COMP1)
|
||||||
|
#define HAL_ITLINE_COMP1 ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP1) /*!< COMP1 Interrupt -> exti[17] */
|
||||||
|
#endif /* COMP1 */
|
||||||
|
#if defined (COMP2)
|
||||||
|
#define HAL_ITLINE_COMP2 ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP2) /*!< COMP2 Interrupt -> exti[18] */
|
||||||
|
#endif /* COMP2 */
|
||||||
|
#if defined (COMP3)
|
||||||
|
#define HAL_ITLINE_COMP3 ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP3) /*!< COMP3 Interrupt -> exti[1x] */
|
||||||
|
#endif /* COMP3 */
|
||||||
|
#define HAL_ITLINE_TIM1_BRK ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_BRK) /*!< TIM1 BRK Interrupt */
|
||||||
|
#define HAL_ITLINE_TIM1_UPD ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_UPD) /*!< TIM1 UPD Interrupt */
|
||||||
|
#define HAL_ITLINE_TIM1_TRG ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_TRG) /*!< TIM1 TRG Interrupt */
|
||||||
|
#define HAL_ITLINE_TIM1_CCU ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_CCU) /*!< TIM1 CCU Interrupt */
|
||||||
|
#define HAL_ITLINE_TIM1_CC ((HAL_SYSCFG_ITLINE14 << 0x18U) | SYSCFG_ITLINE14_SR_TIM1_CC) /*!< TIM1 CC Interrupt */
|
||||||
|
#if defined (TIM2)
|
||||||
|
#define HAL_ITLINE_TIM2 ((HAL_SYSCFG_ITLINE15 << 0x18U) | SYSCFG_ITLINE15_SR_TIM2_GLB) /*!< TIM2 Interrupt */
|
||||||
|
#endif /* TIM2 */
|
||||||
|
#define HAL_ITLINE_TIM3 ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM3_GLB) /*!< TIM3 Interrupt */
|
||||||
|
#if defined (TIM4)
|
||||||
|
#define HAL_ITLINE_TIM4 ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM4_GLB) /*!< TIM4 Interrupt */
|
||||||
|
#endif /* TIM4 */
|
||||||
|
#if defined(TIM6)
|
||||||
|
#define HAL_ITLINE_TIM6 ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_TIM6_GLB) /*!< TIM6 Interrupt */
|
||||||
|
#endif /* TIM6 */
|
||||||
|
#if defined(DAC1)
|
||||||
|
#define HAL_ITLINE_DAC ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_DAC) /*!< DAC Interrupt */
|
||||||
|
#endif /* DAC1 */
|
||||||
|
#if defined(LPTIM1)
|
||||||
|
#define HAL_ITLINE_LPTIM1 ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_LPTIM1_GLB) /*!< LPTIM1 Interrupt -> exti[29] */
|
||||||
|
#endif /* LPTIM1 */
|
||||||
|
#if defined(TIM7)
|
||||||
|
#define HAL_ITLINE_TIM7 ((HAL_SYSCFG_ITLINE18 << 0x18U) | SYSCFG_ITLINE18_SR_TIM7_GLB) /*!< TIM7 Interrupt */
|
||||||
|
#endif /* TIM7 */
|
||||||
|
#if defined(LPTIM2)
|
||||||
|
#define HAL_ITLINE_LPTIM2 ((HAL_SYSCFG_ITLINE18 << 0x18U) | SYSCFG_ITLINE18_SR_LPTIM2_GLB) /*!< LPTIM2 Interrupt -> exti[30] */
|
||||||
|
#endif /* LPTIM2 */
|
||||||
|
#define HAL_ITLINE_TIM14 ((HAL_SYSCFG_ITLINE19 << 0x18U) | SYSCFG_ITLINE19_SR_TIM14_GLB) /*!< TIM14 Interrupt */
|
||||||
|
#if defined(TIM15)
|
||||||
|
#define HAL_ITLINE_TIM15 ((HAL_SYSCFG_ITLINE20 << 0x18U) | SYSCFG_ITLINE20_SR_TIM15_GLB) /*!< TIM15 Interrupt */
|
||||||
|
#endif /* TIM15 */
|
||||||
|
#define HAL_ITLINE_TIM16 ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_TIM16_GLB) /*!< TIM16 Interrupt */
|
||||||
|
#if defined (FDCAN1) || defined (FDCAN2)
|
||||||
|
#define HAL_ITLINE_FDCAN1_IT0 ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_FDCAN1_IT0) /*!< FDCAN1_IT0 Interrupt */
|
||||||
|
#define HAL_ITLINE_FDCAN2_IT0 ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_FDCAN2_IT0) /*!< FDCAN2_IT0 Interrupt */
|
||||||
|
#endif /* FDCAN1 || FDCAN2 */
|
||||||
|
#define HAL_ITLINE_TIM17 ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_TIM17_GLB) /*!< TIM17 Interrupt */
|
||||||
|
#if defined (FDCAN1) || defined (FDCAN2)
|
||||||
|
#define HAL_ITLINE_FDCAN1_IT1 ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_FDCAN1_IT1) /*!< FDCAN1_IT1 Interrupt */
|
||||||
|
#define HAL_ITLINE_FDCAN2_IT1 ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_FDCAN2_IT1) /*!< FDCAN2_IT1 Interrupt */
|
||||||
|
#endif /* FDCAN1 || FDCAN2 */
|
||||||
|
#define HAL_ITLINE_I2C1 ((HAL_SYSCFG_ITLINE23 << 0x18U) | SYSCFG_ITLINE23_SR_I2C1_GLB) /*!< I2C1 Interrupt -> exti[23] */
|
||||||
|
#define HAL_ITLINE_I2C2 ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C2_GLB) /*!< I2C2 Interrupt -> exti[24] */
|
||||||
|
#if defined (I2C3)
|
||||||
|
#define HAL_ITLINE_I2C3 ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C3_GLB) /*!< I2C3 Interrupt -> exti[22] */
|
||||||
|
#endif /* I2C3 */
|
||||||
|
#define HAL_ITLINE_SPI1 ((HAL_SYSCFG_ITLINE25 << 0x18U) | SYSCFG_ITLINE25_SR_SPI1) /*!< SPI1 Interrupt */
|
||||||
|
#define HAL_ITLINE_SPI2 ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE26_SR_SPI2) /*!< SPI2 Interrupt */
|
||||||
|
#if defined (SPI3)
|
||||||
|
#define HAL_ITLINE_SPI3 ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE26_SR_SPI3) /*!< SPI3 Interrupt */
|
||||||
|
#endif /* SPI3 */
|
||||||
|
#define HAL_ITLINE_USART1 ((HAL_SYSCFG_ITLINE27 << 0x18U) | SYSCFG_ITLINE27_SR_USART1_GLB) /*!< USART1 GLB Interrupt -> exti[25] */
|
||||||
|
#define HAL_ITLINE_USART2 ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_USART2_GLB) /*!< USART2 GLB Interrupt -> exti[26] */
|
||||||
|
#if defined (LPUART2)
|
||||||
|
#define HAL_ITLINE_LPUART2 ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_LPUART2_GLB) /*!< LPUART2 GLB Interrupt -> exti[26] */
|
||||||
|
#endif /* LPUART2 */
|
||||||
|
#if defined(USART3)
|
||||||
|
#define HAL_ITLINE_USART3 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART3_GLB) /*!< USART3 Interrupt .... */
|
||||||
|
#endif /* USART3 */
|
||||||
|
#if defined(USART4)
|
||||||
|
#define HAL_ITLINE_USART4 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART4_GLB) /*!< USART4 Interrupt .... */
|
||||||
|
#endif /* USART4 */
|
||||||
|
#if defined (LPUART1)
|
||||||
|
#define HAL_ITLINE_LPUART1 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_LPUART1_GLB) /*!< LPUART1 Interrupt -> exti[28]*/
|
||||||
|
#endif /* LPUART1 */
|
||||||
|
#if defined (USART5)
|
||||||
|
#define HAL_ITLINE_USART5 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART5_GLB) /*!< USART5 Interrupt .... */
|
||||||
|
#endif /* USART5 */
|
||||||
|
#if defined (USART6)
|
||||||
|
#define HAL_ITLINE_USART6 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART6_GLB) /*!< USART6 Interrupt .... */
|
||||||
|
#endif /* USART6 */
|
||||||
|
#if defined (CEC)
|
||||||
|
#define HAL_ITLINE_CEC ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_CEC) /*!< CEC Interrupt -> exti[27] */
|
||||||
|
#endif /* CEC */
|
||||||
|
#if defined (RNG)
|
||||||
|
#define HAL_ITLINE_RNG ((HAL_SYSCFG_ITLINE31 << 0x18U) | SYSCFG_ITLINE31_SR_RNG) /*!< RNG Interrupt */
|
||||||
|
#endif /* RNG */
|
||||||
|
#if defined (AES)
|
||||||
|
#define HAL_ITLINE_AES ((HAL_SYSCFG_ITLINE31 << 0x18U) | SYSCFG_ITLINE31_SR_AES) /*!< AES Interrupt */
|
||||||
|
#endif /* AES */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported macros -----------------------------------------------------------*/
|
||||||
|
/** @defgroup HAL_Exported_Macros HAL Exported Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DBG_Exported_Macros DBG Exported Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @brief Freeze and Unfreeze Peripherals in Debug mode
|
||||||
|
*/
|
||||||
|
#if defined(DBG_APB_FZ1_DBG_TIM2_STOP)
|
||||||
|
#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM2_STOP)
|
||||||
|
#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM2_STOP)
|
||||||
|
#endif /* DBG_APB_FZ1_DBG_TIM2_STOP */
|
||||||
|
|
||||||
|
#if defined(DBG_APB_FZ1_DBG_TIM3_STOP)
|
||||||
|
#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM3_STOP)
|
||||||
|
#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM3_STOP)
|
||||||
|
#endif /* DBG_APB_FZ1_DBG_TIM3_STOP */
|
||||||
|
|
||||||
|
#if defined(DBG_APB_FZ1_DBG_TIM4_STOP)
|
||||||
|
#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM4_STOP)
|
||||||
|
#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM4_STOP)
|
||||||
|
#endif /* DBG_APB_FZ1_DBG_TIM4_STOP */
|
||||||
|
|
||||||
|
#if defined(DBG_APB_FZ1_DBG_TIM6_STOP)
|
||||||
|
#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM6_STOP)
|
||||||
|
#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM6_STOP)
|
||||||
|
#endif /* DBG_APB_FZ1_DBG_TIM6_STOP */
|
||||||
|
|
||||||
|
#if defined(DBG_APB_FZ1_DBG_TIM7_STOP)
|
||||||
|
#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM7_STOP)
|
||||||
|
#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM7_STOP)
|
||||||
|
#endif /* DBG_APB_FZ1_DBG_TIM7_STOP */
|
||||||
|
|
||||||
|
#if defined(DBG_APB_FZ1_DBG_RTC_STOP)
|
||||||
|
#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_RTC_STOP)
|
||||||
|
#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_RTC_STOP)
|
||||||
|
#endif /* DBG_APB_FZ1_DBG_RTC_STOP */
|
||||||
|
|
||||||
|
#if defined(DBG_APB_FZ1_DBG_WWDG_STOP)
|
||||||
|
#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_WWDG_STOP)
|
||||||
|
#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_WWDG_STOP)
|
||||||
|
#endif /* DBG_APB_FZ1_DBG_WWDG_STOP */
|
||||||
|
|
||||||
|
#if defined(DBG_APB_FZ1_DBG_IWDG_STOP)
|
||||||
|
#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_IWDG_STOP)
|
||||||
|
#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_IWDG_STOP)
|
||||||
|
#endif /* DBG_APB_FZ1_DBG_IWDG_STOP */
|
||||||
|
|
||||||
|
#if defined(DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP)
|
||||||
|
#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP)
|
||||||
|
#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP)
|
||||||
|
#endif /* DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP */
|
||||||
|
|
||||||
|
#if defined(DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP)
|
||||||
|
#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP)
|
||||||
|
#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP)
|
||||||
|
#endif /* DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP */
|
||||||
|
|
||||||
|
#if defined(DBG_APB_FZ1_DBG_LPTIM1_STOP)
|
||||||
|
#define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM1_STOP)
|
||||||
|
#define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM1_STOP)
|
||||||
|
#endif /* DBG_APB_FZ1_DBG_LPTIM1_STOP */
|
||||||
|
|
||||||
|
#if defined(DBG_APB_FZ1_DBG_LPTIM2_STOP)
|
||||||
|
#define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM2_STOP)
|
||||||
|
#define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM2_STOP)
|
||||||
|
#endif /* DBG_APB_FZ1_DBG_LPTIM2_STOP */
|
||||||
|
|
||||||
|
#if defined(DBG_APB_FZ2_DBG_TIM1_STOP)
|
||||||
|
#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM1_STOP)
|
||||||
|
#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM1_STOP)
|
||||||
|
#endif /* DBG_APB_FZ2_DBG_TIM1_STOP */
|
||||||
|
|
||||||
|
#if defined(DBG_APB_FZ2_DBG_TIM14_STOP)
|
||||||
|
#define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM14_STOP)
|
||||||
|
#define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM14_STOP)
|
||||||
|
#endif /* DBG_APB_FZ2_DBG_TIM14_STOP */
|
||||||
|
|
||||||
|
#if defined(DBG_APB_FZ2_DBG_TIM15_STOP)
|
||||||
|
#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM15_STOP)
|
||||||
|
#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM15_STOP)
|
||||||
|
#endif /* DBG_APB_FZ2_DBG_TIM15_STOP */
|
||||||
|
|
||||||
|
#if defined(DBG_APB_FZ2_DBG_TIM16_STOP)
|
||||||
|
#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM16_STOP)
|
||||||
|
#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM16_STOP)
|
||||||
|
#endif /* DBG_APB_FZ2_DBG_TIM16_STOP */
|
||||||
|
|
||||||
|
#if defined(DBG_APB_FZ2_DBG_TIM17_STOP)
|
||||||
|
#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM17_STOP)
|
||||||
|
#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM17_STOP)
|
||||||
|
#endif /* DBG_APB_FZ2_DBG_TIM17_STOP */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief ISR wrapper check
|
||||||
|
* @note Allow to determine interrupt source per line.
|
||||||
|
*/
|
||||||
|
#define __HAL_GET_PENDING_IT(__SOURCE__) (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFF))
|
||||||
|
|
||||||
|
/** @brief Main Flash memory mapped at 0x00000000
|
||||||
|
*/
|
||||||
|
#define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)
|
||||||
|
|
||||||
|
/** @brief System Flash memory mapped at 0x00000000
|
||||||
|
*/
|
||||||
|
#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0)
|
||||||
|
|
||||||
|
/** @brief Embedded SRAM mapped at 0x00000000
|
||||||
|
*/
|
||||||
|
#define __HAL_SYSCFG_REMAPMEMORY_SRAM() \
|
||||||
|
MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, (SYSCFG_CFGR1_MEM_MODE_1|SYSCFG_CFGR1_MEM_MODE_0))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the boot mode as configured by user.
|
||||||
|
* @retval The boot mode as configured by user. The returned value can be one
|
||||||
|
* of the following values @ref SYSCFG_BootMode
|
||||||
|
*/
|
||||||
|
#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)
|
||||||
|
|
||||||
|
/** @brief SYSCFG Break ECC lock.
|
||||||
|
* Enable and lock the connection of Flash ECC error connection to TIM1 Break input.
|
||||||
|
* @note The selected configuration is locked and can be unlocked only by system reset.
|
||||||
|
*/
|
||||||
|
#define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
|
||||||
|
|
||||||
|
|
||||||
|
/** @brief SYSCFG Break Cortex-M0+ Lockup lock.
|
||||||
|
* Enables and locks the connection of Cortex-M0+ LOCKUP (Hardfault) output to TIM1/15/16/17 Break input
|
||||||
|
* @note The selected configuration is locked and can be unlocked only by system reset.
|
||||||
|
*/
|
||||||
|
#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
|
||||||
|
|
||||||
|
#if defined(SYSCFG_CFGR2_PVDL)
|
||||||
|
/** @brief SYSCFG Break PVD lock.
|
||||||
|
* Enables and locks the PVD connection with Timer1/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR register
|
||||||
|
* @note The selected configuration is locked and can be unlocked only by system reset
|
||||||
|
*/
|
||||||
|
#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
|
||||||
|
#endif /* SYSCFG_CFGR2_PVDL */
|
||||||
|
|
||||||
|
/** @brief SYSCFG Break SRAM PARITY lock
|
||||||
|
* Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/15/16/17
|
||||||
|
* @note The selected configuration is locked and can only be unlocked by system reset
|
||||||
|
*/
|
||||||
|
#define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() SET_BIT(SYSCFG->CFGR2,SYSCFG_CFGR2_SPL)
|
||||||
|
|
||||||
|
/** @brief Parity check on RAM disable macro
|
||||||
|
* @note Disabling the parity check on RAM locks the configuration bit.
|
||||||
|
* To re-enable the parity check on RAM perform a system reset.
|
||||||
|
*/
|
||||||
|
#define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (SYSCFG->CFGR2 |= SYSCFG_CFGR2_SPF)
|
||||||
|
|
||||||
|
/** @brief Set the PEF bit to clear the SRAM Parity Error Flag.
|
||||||
|
*/
|
||||||
|
#define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
|
||||||
|
|
||||||
|
/** @brief Fast-mode Plus driving capability enable/disable macros
|
||||||
|
* @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO
|
||||||
|
*/
|
||||||
|
#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
|
||||||
|
SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
|
||||||
|
}while(0U)
|
||||||
|
|
||||||
|
#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
|
||||||
|
CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
|
||||||
|
}while(0U)
|
||||||
|
|
||||||
|
#if defined(SYSCFG_CDEN_SUPPORT)
|
||||||
|
/** @brief Clamping Diode on specific pins enable/disable macros
|
||||||
|
* @param __PIN__ This parameter can be a combination of values @ref SYSCFG_ClampingDiode
|
||||||
|
*/
|
||||||
|
#define __HAL_SYSCFG_CLAMPINGDIODE_ENABLE(__PIN__) do {assert_param(IS_SYSCFG_CLAMPINGDIODE((__PIN__)));\
|
||||||
|
SET_BIT(SYSCFG->CFGR2, (__PIN__));\
|
||||||
|
}while(0U)
|
||||||
|
|
||||||
|
#define __HAL_SYSCFG_CLAMPINGDIODE_DISABLE(__PIN__) do {assert_param(IS_SYSCFG_CLAMPINGDIODE((__PIN__)));\
|
||||||
|
CLEAR_BIT(SYSCFG->CFGR2, (__PIN__));\
|
||||||
|
}while(0U)
|
||||||
|
#endif /* SYSCFG_CDEN_SUPPORT */
|
||||||
|
|
||||||
|
/** @brief ISR wrapper check
|
||||||
|
* @note Allow to determine interrupt source per line.
|
||||||
|
*/
|
||||||
|
#define __HAL_SYSCFG_GET_PENDING_IT(__SOURCE__) \
|
||||||
|
(SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFFU))
|
||||||
|
|
||||||
|
/** @brief selection of the modulation envelope signal macro, using bits [7:6] of SYSCFG_CFGR1 register
|
||||||
|
* @param __SOURCE__ This parameter can be a value of @ref HAL_IR_ENV_SEL
|
||||||
|
*/
|
||||||
|
#define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__) do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__)));\
|
||||||
|
CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD);\
|
||||||
|
SET_BIT(SYSCFG->CFGR1, (__SOURCE__));\
|
||||||
|
}while(0U)
|
||||||
|
|
||||||
|
#define __HAL_SYSCFG_GET_IRDA_ENV_SELECTION() ((SYSCFG->CFGR1) & 0x000000C0U)
|
||||||
|
|
||||||
|
/** @brief IROut Polarity Selection, using bit[5] of SYSCFG_CFGR1 register
|
||||||
|
* @param __SEL__ This parameter can be a value of @ref HAL_IR_POL_SEL
|
||||||
|
*/
|
||||||
|
#define __HAL_SYSCFG_IRDA_OUT_POLARITY_SELECTION(__SEL__) do { assert_param(IS_HAL_SYSCFG_IRDA_POL_SEL((__SEL__)));\
|
||||||
|
CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL);\
|
||||||
|
SET_BIT(SYSCFG->CFGR1,(__SEL__));\
|
||||||
|
}while(0U)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the IROut Polarity mode as configured by user.
|
||||||
|
* @retval The IROut polarity as configured by user. The returned value can be one
|
||||||
|
* of @ref HAL_IR_POL_SEL
|
||||||
|
*/
|
||||||
|
#define __HAL_SYSCFG_GET_POLARITY() READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL)
|
||||||
|
|
||||||
|
/** @brief Break input to TIM1/15/16/17 capability enable/disable macros
|
||||||
|
* @param __BREAK__ This parameter can be a value of @ref SYSCFG_Break
|
||||||
|
*/
|
||||||
|
#define __HAL_SYSCFG_BREAK_ENABLE(__BREAK__) do {assert_param(IS_SYSCFG_BREAK_CONFIG((__BREAK__)));\
|
||||||
|
SET_BIT(SYSCFG->CFGR2, (__BREAK__));\
|
||||||
|
}while(0U)
|
||||||
|
|
||||||
|
#define __HAL_SYSCFG_BREAK_DISABLE(__BREAK__) do {assert_param(IS_SYSCFG_BREAK_CONFIG((__BREAK__)));\
|
||||||
|
CLEAR_BIT(SYSCFG->CFGR2, (__BREAK__));\
|
||||||
|
}while(0U)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#if defined (PWR_PVD_SUPPORT)
|
||||||
|
#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_SP) || \
|
||||||
|
((__CONFIG__) == SYSCFG_BREAK_PVD) || \
|
||||||
|
((__CONFIG__) == SYSCFG_BREAK_ECC) || \
|
||||||
|
((__CONFIG__) == SYSCFG_BREAK_LOCKUP))
|
||||||
|
#else
|
||||||
|
#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_SP) || \
|
||||||
|
((__CONFIG__) == SYSCFG_BREAK_ECC) || \
|
||||||
|
((__CONFIG__) == SYSCFG_BREAK_LOCKUP))
|
||||||
|
#endif /* PWR_PVD_SUPPORT */
|
||||||
|
|
||||||
|
#if defined(SYSCFG_CDEN_SUPPORT)
|
||||||
|
#define IS_SYSCFG_CLAMPINGDIODE(__PIN__) ((((__PIN__) & SYSCFG_CDEN_PA1) == SYSCFG_CDEN_PA1) || \
|
||||||
|
(((__PIN__) & SYSCFG_CDEN_PA3) == SYSCFG_CDEN_PA3) || \
|
||||||
|
(((__PIN__) & SYSCFG_CDEN_PA5) == SYSCFG_CDEN_PA5) || \
|
||||||
|
(((__PIN__) & SYSCFG_CDEN_PA6) == SYSCFG_CDEN_PA6) || \
|
||||||
|
(((__PIN__) & SYSCFG_CDEN_PA13) == SYSCFG_CDEN_PA13) || \
|
||||||
|
(((__PIN__) & SYSCFG_CDEN_PB0) == SYSCFG_CDEN_PB0) || \
|
||||||
|
(((__PIN__) & SYSCFG_CDEN_PB1) == SYSCFG_CDEN_PB1) || \
|
||||||
|
(((__PIN__) & SYSCFG_CDEN_PB2) == SYSCFG_CDEN_PB2))
|
||||||
|
#endif /* SYSCFG_CDEN_SUPPORT */
|
||||||
|
|
||||||
|
#if defined (USART4)
|
||||||
|
#define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \
|
||||||
|
((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \
|
||||||
|
((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART4))
|
||||||
|
#else
|
||||||
|
#define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \
|
||||||
|
((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \
|
||||||
|
((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART2))
|
||||||
|
#endif /* USART4 */
|
||||||
|
#define IS_HAL_SYSCFG_IRDA_POL_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_POLARITY_NOT_INVERTED) || \
|
||||||
|
((SEL) == HAL_SYSCFG_IRDA_POLARITY_INVERTED))
|
||||||
|
|
||||||
|
#if defined (SYSCFG_CFGR1_UCPD1_STROBE) || defined (SYSCFG_CFGR1_UCPD2_STROBE)
|
||||||
|
#define IS_SYSCFG_DBATT_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_UCPD1_STROBE) || \
|
||||||
|
((__CONFIG__) == SYSCFG_UCPD2_STROBE) || \
|
||||||
|
((__CONFIG__) == (SYSCFG_UCPD1_STROBE | SYSCFG_UCPD2_STROBE)))
|
||||||
|
#endif /* SYSCFG_CFGR1_UCPD1_STROBE || SYSCFG_CFGR1_UCPD2_STROBE */
|
||||||
|
#if defined(VREFBUF)
|
||||||
|
#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
|
||||||
|
((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1))
|
||||||
|
|
||||||
|
#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
|
||||||
|
((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
|
||||||
|
|
||||||
|
#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
|
||||||
|
#endif /* VREFBUF */
|
||||||
|
|
||||||
|
#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PA9) == SYSCFG_FASTMODEPLUS_PA9) || \
|
||||||
|
(((__PIN__) & SYSCFG_FASTMODEPLUS_PA10) == SYSCFG_FASTMODEPLUS_PA10) || \
|
||||||
|
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
|
||||||
|
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
|
||||||
|
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
|
||||||
|
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
|
||||||
|
|
||||||
|
#define IS_HAL_REMAP_PIN(RMP) (((RMP) == SYSCFG_REMAP_PA11) || \
|
||||||
|
((RMP) == SYSCFG_REMAP_PA12) || \
|
||||||
|
((RMP) == (SYSCFG_REMAP_PA11 | SYSCFG_REMAP_PA12)))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup HAL_Private_Macros HAL Private Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
|
||||||
|
((FREQ) == HAL_TICK_FREQ_100HZ) || \
|
||||||
|
((FREQ) == HAL_TICK_FREQ_1KHZ))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @defgroup HAL_Exported_Functions HAL Exported Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup HAL_Exported_Functions_Group1 HAL Initialization and Configuration functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Initialization and Configuration functions ******************************/
|
||||||
|
HAL_StatusTypeDef HAL_Init(void);
|
||||||
|
HAL_StatusTypeDef HAL_DeInit(void);
|
||||||
|
void HAL_MspInit(void);
|
||||||
|
void HAL_MspDeInit(void);
|
||||||
|
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Peripheral Control functions ************************************************/
|
||||||
|
void HAL_IncTick(void);
|
||||||
|
void HAL_Delay(uint32_t Delay);
|
||||||
|
uint32_t HAL_GetTick(void);
|
||||||
|
uint32_t HAL_GetTickPrio(void);
|
||||||
|
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
|
||||||
|
HAL_TickFreqTypeDef HAL_GetTickFreq(void);
|
||||||
|
void HAL_SuspendTick(void);
|
||||||
|
void HAL_ResumeTick(void);
|
||||||
|
uint32_t HAL_GetHalVersion(void);
|
||||||
|
uint32_t HAL_GetREVID(void);
|
||||||
|
uint32_t HAL_GetDEVID(void);
|
||||||
|
uint32_t HAL_GetUIDw0(void);
|
||||||
|
uint32_t HAL_GetUIDw1(void);
|
||||||
|
uint32_t HAL_GetUIDw2(void);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup HAL_Exported_Functions_Group3 DBGMCU Control functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* DBGMCU Peripheral Control functions *****************************************/
|
||||||
|
void HAL_DBGMCU_EnableDBGStopMode(void);
|
||||||
|
void HAL_DBGMCU_DisableDBGStopMode(void);
|
||||||
|
void HAL_DBGMCU_EnableDBGStandbyMode(void);
|
||||||
|
void HAL_DBGMCU_DisableDBGStandbyMode(void);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported variables ---------------------------------------------------------*/
|
||||||
|
/** @addtogroup HAL_Exported_Variables
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
extern __IO uint32_t uwTick;
|
||||||
|
extern uint32_t uwTickPrio;
|
||||||
|
extern HAL_TickFreqTypeDef uwTickFreq;
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup HAL_Exported_Functions_Group4 SYSCFG configuration functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* SYSCFG Control functions ****************************************************/
|
||||||
|
|
||||||
|
#if defined(VREFBUF)
|
||||||
|
void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
|
||||||
|
void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
|
||||||
|
void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
|
||||||
|
HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
|
||||||
|
void HAL_SYSCFG_DisableVREFBUF(void);
|
||||||
|
#endif /* VREFBUF */
|
||||||
|
|
||||||
|
void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void);
|
||||||
|
void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void);
|
||||||
|
void HAL_SYSCFG_EnableRemap(uint32_t PinRemap);
|
||||||
|
void HAL_SYSCFG_DisableRemap(uint32_t PinRemap);
|
||||||
|
#if defined(SYSCFG_CDEN_SUPPORT)
|
||||||
|
void HAL_SYSCFG_EnableClampingDiode(uint32_t PinConfig);
|
||||||
|
void HAL_SYSCFG_DisableClampingDiode(uint32_t PinConfig);
|
||||||
|
#endif /* SYSCFG_CDEN_SUPPORT */
|
||||||
|
#if defined (SYSCFG_CFGR1_UCPD1_STROBE) || defined (SYSCFG_CFGR1_UCPD2_STROBE)
|
||||||
|
void HAL_SYSCFG_StrobeDBattpinsConfig(uint32_t ConfigDeadBattery);
|
||||||
|
#endif /* SYSCFG_CFGR1_UCPD1_STROBE || SYSCFG_CFGR1_UCPD2_STROBE */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* STM32G0xx_HAL_H */
|
||||||
|
|
||||||
|
|
||||||
385
Boot/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h
Normal file
385
Boot/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h
Normal file
@@ -0,0 +1,385 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32g0xx_hal_cortex.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @brief Header file of CORTEX HAL module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* Copyright (c) 2018 STMicroelectronics.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* This software is licensed under terms that can be found in the LICENSE file in
|
||||||
|
* the root directory of this software component.
|
||||||
|
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef STM32G0xx_HAL_CORTEX_H
|
||||||
|
#define STM32G0xx_HAL_CORTEX_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32g0xx_hal_def.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32G0xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CORTEX CORTEX
|
||||||
|
* @brief CORTEX HAL module driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if (__MPU_PRESENT == 1)
|
||||||
|
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
|
||||||
|
* @brief MPU Region initialization structure
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint8_t Enable; /*!< Specifies the status of the region.
|
||||||
|
This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
|
||||||
|
uint8_t Number; /*!< Specifies the number of the region to protect.
|
||||||
|
This parameter can be a value of @ref CORTEX_MPU_Region_Number */
|
||||||
|
uint32_t BaseAddress; /*!< Specifies the base address of the region to protect.
|
||||||
|
*/
|
||||||
|
uint8_t Size; /*!< Specifies the size of the region to protect.
|
||||||
|
This parameter can be a value of @ref CORTEX_MPU_Region_Size */
|
||||||
|
uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
|
||||||
|
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
|
||||||
|
uint8_t TypeExtField; /*!< Specifies the TEX field level.
|
||||||
|
This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
|
||||||
|
uint8_t AccessPermission; /*!< Specifies the region access permission type.
|
||||||
|
This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
|
||||||
|
uint8_t DisableExec; /*!< Specifies the instruction access status.
|
||||||
|
This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
|
||||||
|
uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
|
||||||
|
This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
|
||||||
|
uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
|
||||||
|
This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
|
||||||
|
uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
|
||||||
|
This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
|
||||||
|
} MPU_Region_InitTypeDef;
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
#endif /* __MPU_PRESENT */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
|
||||||
|
#define SYSTICK_CLKSOURCE_HCLK 0x00000004U
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if (__MPU_PRESENT == 1)
|
||||||
|
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U
|
||||||
|
#define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk)
|
||||||
|
#define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk)
|
||||||
|
#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define MPU_REGION_ENABLE ((uint8_t)0x01)
|
||||||
|
#define MPU_REGION_DISABLE ((uint8_t)0x00)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
|
||||||
|
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
|
||||||
|
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
|
||||||
|
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
|
||||||
|
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
|
||||||
|
#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
|
||||||
|
#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
|
||||||
|
#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
|
||||||
|
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
|
||||||
|
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
|
||||||
|
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
|
||||||
|
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
|
||||||
|
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
|
||||||
|
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
|
||||||
|
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
|
||||||
|
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
|
||||||
|
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
|
||||||
|
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
|
||||||
|
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
|
||||||
|
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
|
||||||
|
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
|
||||||
|
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
|
||||||
|
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
|
||||||
|
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
|
||||||
|
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
|
||||||
|
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
|
||||||
|
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
|
||||||
|
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
|
||||||
|
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
|
||||||
|
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
|
||||||
|
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
|
||||||
|
#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
|
||||||
|
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
|
||||||
|
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
|
||||||
|
#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
|
||||||
|
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
|
||||||
|
#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
|
||||||
|
#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
|
||||||
|
#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
|
||||||
|
#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
|
||||||
|
#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
|
||||||
|
#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
|
||||||
|
#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
#endif /* __MPU_PRESENT */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported macros -----------------------------------------------------------*/
|
||||||
|
/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions
|
||||||
|
* @brief Initialization and Configuration functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Initialization and Configuration functions *****************************/
|
||||||
|
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
|
||||||
|
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
|
||||||
|
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
|
||||||
|
void HAL_NVIC_SystemReset(void);
|
||||||
|
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
|
||||||
|
* @brief Cortex control functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Peripheral Control functions *************************************************/
|
||||||
|
uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn);
|
||||||
|
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
|
||||||
|
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
|
||||||
|
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
|
||||||
|
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
|
||||||
|
void HAL_SYSTICK_IRQHandler(void);
|
||||||
|
void HAL_SYSTICK_Callback(void);
|
||||||
|
|
||||||
|
#if (__MPU_PRESENT == 1U)
|
||||||
|
void HAL_MPU_Enable(uint32_t MPU_Control);
|
||||||
|
void HAL_MPU_Disable(void);
|
||||||
|
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
|
||||||
|
#endif /* __MPU_PRESENT */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private types -------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private constants ---------------------------------------------------------*/
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x4U)
|
||||||
|
|
||||||
|
#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn)
|
||||||
|
|
||||||
|
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
|
||||||
|
((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
|
||||||
|
|
||||||
|
#if (__MPU_PRESENT == 1)
|
||||||
|
#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
|
||||||
|
((STATE) == MPU_REGION_DISABLE))
|
||||||
|
|
||||||
|
#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
|
||||||
|
((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
|
||||||
|
|
||||||
|
#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
|
||||||
|
((STATE) == MPU_ACCESS_NOT_SHAREABLE))
|
||||||
|
|
||||||
|
#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
|
||||||
|
((STATE) == MPU_ACCESS_NOT_CACHEABLE))
|
||||||
|
|
||||||
|
#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
|
||||||
|
((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
|
||||||
|
|
||||||
|
#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
|
||||||
|
((TYPE) == MPU_TEX_LEVEL1) || \
|
||||||
|
((TYPE) == MPU_TEX_LEVEL2))
|
||||||
|
|
||||||
|
#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
|
||||||
|
((TYPE) == MPU_REGION_PRIV_RW) || \
|
||||||
|
((TYPE) == MPU_REGION_PRIV_RW_URO) || \
|
||||||
|
((TYPE) == MPU_REGION_FULL_ACCESS) || \
|
||||||
|
((TYPE) == MPU_REGION_PRIV_RO) || \
|
||||||
|
((TYPE) == MPU_REGION_PRIV_RO_URO))
|
||||||
|
|
||||||
|
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
|
||||||
|
((NUMBER) == MPU_REGION_NUMBER1) || \
|
||||||
|
((NUMBER) == MPU_REGION_NUMBER2) || \
|
||||||
|
((NUMBER) == MPU_REGION_NUMBER3) || \
|
||||||
|
((NUMBER) == MPU_REGION_NUMBER4) || \
|
||||||
|
((NUMBER) == MPU_REGION_NUMBER5) || \
|
||||||
|
((NUMBER) == MPU_REGION_NUMBER6) || \
|
||||||
|
((NUMBER) == MPU_REGION_NUMBER7))
|
||||||
|
|
||||||
|
#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_256B) || \
|
||||||
|
((SIZE) == MPU_REGION_SIZE_512B) || \
|
||||||
|
((SIZE) == MPU_REGION_SIZE_1KB) || \
|
||||||
|
((SIZE) == MPU_REGION_SIZE_2KB) || \
|
||||||
|
((SIZE) == MPU_REGION_SIZE_4KB) || \
|
||||||
|
((SIZE) == MPU_REGION_SIZE_8KB) || \
|
||||||
|
((SIZE) == MPU_REGION_SIZE_16KB) || \
|
||||||
|
((SIZE) == MPU_REGION_SIZE_32KB) || \
|
||||||
|
((SIZE) == MPU_REGION_SIZE_64KB) || \
|
||||||
|
((SIZE) == MPU_REGION_SIZE_128KB) || \
|
||||||
|
((SIZE) == MPU_REGION_SIZE_256KB) || \
|
||||||
|
((SIZE) == MPU_REGION_SIZE_512KB) || \
|
||||||
|
((SIZE) == MPU_REGION_SIZE_1MB) || \
|
||||||
|
((SIZE) == MPU_REGION_SIZE_2MB) || \
|
||||||
|
((SIZE) == MPU_REGION_SIZE_4MB) || \
|
||||||
|
((SIZE) == MPU_REGION_SIZE_8MB) || \
|
||||||
|
((SIZE) == MPU_REGION_SIZE_16MB) || \
|
||||||
|
((SIZE) == MPU_REGION_SIZE_32MB) || \
|
||||||
|
((SIZE) == MPU_REGION_SIZE_64MB) || \
|
||||||
|
((SIZE) == MPU_REGION_SIZE_128MB) || \
|
||||||
|
((SIZE) == MPU_REGION_SIZE_256MB) || \
|
||||||
|
((SIZE) == MPU_REGION_SIZE_512MB) || \
|
||||||
|
((SIZE) == MPU_REGION_SIZE_1GB) || \
|
||||||
|
((SIZE) == MPU_REGION_SIZE_2GB) || \
|
||||||
|
((SIZE) == MPU_REGION_SIZE_4GB))
|
||||||
|
|
||||||
|
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)
|
||||||
|
#endif /* __MPU_PRESENT */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private functions ---------------------------------------------------------*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* STM32G0xx_HAL_CORTEX_H */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
213
Boot/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h
Normal file
213
Boot/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h
Normal file
@@ -0,0 +1,213 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32g0xx_hal_def.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @brief This file contains HAL common defines, enumeration, macros and
|
||||||
|
* structures definitions.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* Copyright (c) 2018 STMicroelectronics.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* This software is licensed under terms that can be found in the LICENSE file
|
||||||
|
* in the root directory of this software component.
|
||||||
|
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef STM32G0xx_HAL_DEF
|
||||||
|
#define STM32G0xx_HAL_DEF
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32g0xx.h"
|
||||||
|
#include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */
|
||||||
|
#include <stddef.h>
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief HAL Status structures definition
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_OK = 0x00U,
|
||||||
|
HAL_ERROR = 0x01U,
|
||||||
|
HAL_BUSY = 0x02U,
|
||||||
|
HAL_TIMEOUT = 0x03U
|
||||||
|
} HAL_StatusTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief HAL Lock structures definition
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_UNLOCKED = 0x00U,
|
||||||
|
HAL_LOCKED = 0x01U
|
||||||
|
} HAL_LockTypeDef;
|
||||||
|
|
||||||
|
/* Exported macros -----------------------------------------------------------*/
|
||||||
|
|
||||||
|
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
|
||||||
|
|
||||||
|
#define HAL_MAX_DELAY 0xFFFFFFFFU
|
||||||
|
|
||||||
|
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
|
||||||
|
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
|
||||||
|
|
||||||
|
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
|
||||||
|
do{ \
|
||||||
|
(__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
|
||||||
|
(__DMA_HANDLE__).Parent = (__HANDLE__); \
|
||||||
|
} while(0U)
|
||||||
|
|
||||||
|
/** @brief Reset the Handles State field.
|
||||||
|
* @param __HANDLE__ specifies the Peripheral Handle.
|
||||||
|
* @note This macro can be used for the following purpose:
|
||||||
|
* - When the Handle is declared as local variable; before passing it as parameter
|
||||||
|
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
|
||||||
|
* to set to 0 the Handles "State" field.
|
||||||
|
* Otherwise, "State" field may have any random value and the first time the function
|
||||||
|
* HAL_PPP_Init() is called, the low level hardware initialization will be missed
|
||||||
|
* (i.e. HAL_PPP_MspInit() will not be executed).
|
||||||
|
* - When there is a need to reconfigure the low level hardware: instead of calling
|
||||||
|
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
|
||||||
|
* In this later function, when the Handles "State" field is set to 0, it will execute the function
|
||||||
|
* HAL_PPP_MspInit() which will reconfigure the low level hardware.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
|
||||||
|
|
||||||
|
#if (USE_RTOS == 1U)
|
||||||
|
/* Reserved for future use */
|
||||||
|
#error " USE_RTOS should be 0 in the current HAL release "
|
||||||
|
#else
|
||||||
|
#define __HAL_LOCK(__HANDLE__) \
|
||||||
|
do{ \
|
||||||
|
if((__HANDLE__)->Lock == HAL_LOCKED) \
|
||||||
|
{ \
|
||||||
|
return HAL_BUSY; \
|
||||||
|
} \
|
||||||
|
else \
|
||||||
|
{ \
|
||||||
|
(__HANDLE__)->Lock = HAL_LOCKED; \
|
||||||
|
} \
|
||||||
|
}while (0U)
|
||||||
|
|
||||||
|
#define __HAL_UNLOCK(__HANDLE__) \
|
||||||
|
do{ \
|
||||||
|
(__HANDLE__)->Lock = HAL_UNLOCKED; \
|
||||||
|
}while (0U)
|
||||||
|
#endif /* USE_RTOS */
|
||||||
|
|
||||||
|
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||||
|
#ifndef __weak
|
||||||
|
#define __weak __attribute__((weak))
|
||||||
|
#endif /* __weak */
|
||||||
|
#ifndef __packed
|
||||||
|
#define __packed __attribute__((packed))
|
||||||
|
#endif /* __packed */
|
||||||
|
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
|
||||||
|
#ifndef __weak
|
||||||
|
#define __weak __attribute__((weak))
|
||||||
|
#endif /* __weak */
|
||||||
|
#ifndef __packed
|
||||||
|
#define __packed __attribute__((__packed__))
|
||||||
|
#endif /* __packed */
|
||||||
|
#endif /* __GNUC__ */
|
||||||
|
|
||||||
|
|
||||||
|
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
|
||||||
|
/* GNU Compiler */
|
||||||
|
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
|
||||||
|
#ifndef __ALIGN_BEGIN
|
||||||
|
#define __ALIGN_BEGIN
|
||||||
|
#endif /* __ALIGN_BEGIN */
|
||||||
|
#ifndef __ALIGN_END
|
||||||
|
#define __ALIGN_END __attribute__ ((aligned (4)))
|
||||||
|
#endif /* __ALIGN_END */
|
||||||
|
#elif defined (__GNUC__) && !defined (__CC_ARM) /* GNU Compiler */
|
||||||
|
#ifndef __ALIGN_END
|
||||||
|
#define __ALIGN_END __attribute__ ((aligned (4U)))
|
||||||
|
#endif /* __ALIGN_END */
|
||||||
|
#ifndef __ALIGN_BEGIN
|
||||||
|
#define __ALIGN_BEGIN
|
||||||
|
#endif /* __ALIGN_BEGIN */
|
||||||
|
#else
|
||||||
|
#ifndef __ALIGN_END
|
||||||
|
#define __ALIGN_END
|
||||||
|
#endif /* __ALIGN_END */
|
||||||
|
#ifndef __ALIGN_BEGIN
|
||||||
|
/* ARM Compiler */
|
||||||
|
#if defined (__CC_ARM) /* ARM Compiler V5 */
|
||||||
|
#define __ALIGN_BEGIN __align(4U)
|
||||||
|
/* IAR Compiler */
|
||||||
|
#elif defined (__ICCARM__)
|
||||||
|
#define __ALIGN_BEGIN
|
||||||
|
#endif /* __CC_ARM */
|
||||||
|
#endif /* __ALIGN_BEGIN */
|
||||||
|
#endif /* __GNUC__ */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief __RAM_FUNC definition
|
||||||
|
*/
|
||||||
|
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
|
||||||
|
/* ARM Compiler V4/V5 and V6
|
||||||
|
--------------------------
|
||||||
|
RAM functions are defined using the toolchain options.
|
||||||
|
Functions that are executed in RAM should reside in a separate source module.
|
||||||
|
Using the 'Options for File' dialog you can simply change the 'Code / Const'
|
||||||
|
area of a module to a memory space in physical RAM.
|
||||||
|
Available memory areas are declared in the 'Target' tab of the 'Options for Target'
|
||||||
|
dialog.
|
||||||
|
*/
|
||||||
|
#define __RAM_FUNC
|
||||||
|
|
||||||
|
#elif defined ( __ICCARM__ )
|
||||||
|
/* ICCARM Compiler
|
||||||
|
---------------
|
||||||
|
RAM functions are defined using a specific toolchain keyword "__ramfunc".
|
||||||
|
*/
|
||||||
|
#define __RAM_FUNC __ramfunc
|
||||||
|
|
||||||
|
#elif defined ( __GNUC__ )
|
||||||
|
/* GNU Compiler
|
||||||
|
------------
|
||||||
|
RAM functions are defined using a specific toolchain attribute
|
||||||
|
"__attribute__((section(".RamFunc")))".
|
||||||
|
*/
|
||||||
|
#define __RAM_FUNC __attribute__((section(".RamFunc")))
|
||||||
|
|
||||||
|
#endif /* __CC_ARM || __ARMCC_VERSION */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief __NOINLINE definition
|
||||||
|
*/
|
||||||
|
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
|
||||||
|
/* ARM V4/V5 and V6 & GNU Compiler
|
||||||
|
-------------------------------
|
||||||
|
*/
|
||||||
|
#define __NOINLINE __attribute__ ( (noinline) )
|
||||||
|
|
||||||
|
#elif defined ( __ICCARM__ )
|
||||||
|
/* ICCARM Compiler
|
||||||
|
---------------
|
||||||
|
*/
|
||||||
|
#define __NOINLINE _Pragma("optimize = no_inline")
|
||||||
|
|
||||||
|
#endif /* __CC_ARM || __ARMCC_VERSION */
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* STM32G0xx_HAL_DEF */
|
||||||
|
|
||||||
|
|
||||||
803
Boot/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h
Normal file
803
Boot/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h
Normal file
@@ -0,0 +1,803 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32g0xx_hal_dma.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @brief Header file of DMA HAL module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* Copyright (c) 2018 STMicroelectronics.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* This software is licensed under terms that can be found in the LICENSE file
|
||||||
|
* in the root directory of this software component.
|
||||||
|
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef STM32G0xx_HAL_DMA_H
|
||||||
|
#define STM32G0xx_HAL_DMA_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32g0xx_hal_def.h"
|
||||||
|
#include "stm32g0xx_ll_dma.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32G0xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup DMA
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
/** @defgroup DMA_Exported_Types DMA Exported Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief DMA Configuration Structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t Request; /*!< Specifies the request selected for the specified channel.
|
||||||
|
This parameter can be a value of @ref DMA_request */
|
||||||
|
|
||||||
|
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
|
||||||
|
from memory to memory or from peripheral to memory.
|
||||||
|
This parameter can be a value of @ref DMA_Data_transfer_direction */
|
||||||
|
|
||||||
|
uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
|
||||||
|
This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
|
||||||
|
|
||||||
|
uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
|
||||||
|
This parameter can be a value of @ref DMA_Memory_incremented_mode */
|
||||||
|
|
||||||
|
uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
|
||||||
|
This parameter can be a value of @ref DMA_Peripheral_data_size */
|
||||||
|
|
||||||
|
uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
|
||||||
|
This parameter can be a value of @ref DMA_Memory_data_size */
|
||||||
|
|
||||||
|
uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
|
||||||
|
This parameter can be a value of @ref DMA_mode
|
||||||
|
@note The circular buffer mode cannot be used if the memory-to-memory
|
||||||
|
data transfer is configured on the selected Channel */
|
||||||
|
|
||||||
|
uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
|
||||||
|
This parameter can be a value of @ref DMA_Priority_level */
|
||||||
|
} DMA_InitTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief HAL DMA State structures definition
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
|
||||||
|
HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
|
||||||
|
HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
|
||||||
|
HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
|
||||||
|
} HAL_DMA_StateTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief HAL DMA Error Code structure definition
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
|
||||||
|
HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
|
||||||
|
} HAL_DMA_LevelCompleteTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief HAL DMA Callback ID structure definition
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
|
||||||
|
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
|
||||||
|
HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
|
||||||
|
HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
|
||||||
|
HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
|
||||||
|
|
||||||
|
} HAL_DMA_CallbackIDTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief DMA handle Structure definition
|
||||||
|
*/
|
||||||
|
typedef struct __DMA_HandleTypeDef
|
||||||
|
{
|
||||||
|
DMA_Channel_TypeDef *Instance; /*!< Register base address */
|
||||||
|
|
||||||
|
DMA_InitTypeDef Init; /*!< DMA communication parameters */
|
||||||
|
|
||||||
|
HAL_LockTypeDef Lock; /*!< DMA locking object */
|
||||||
|
|
||||||
|
__IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
|
||||||
|
|
||||||
|
void *Parent; /*!< Parent object state */
|
||||||
|
|
||||||
|
void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */
|
||||||
|
|
||||||
|
void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */
|
||||||
|
|
||||||
|
void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */
|
||||||
|
|
||||||
|
void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */
|
||||||
|
|
||||||
|
__IO uint32_t ErrorCode; /*!< DMA Error code */
|
||||||
|
|
||||||
|
#if defined(DMA2)
|
||||||
|
DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
|
||||||
|
|
||||||
|
#endif /* DMA2 */
|
||||||
|
uint32_t ChannelIndex; /*!< DMA Channel Index */
|
||||||
|
|
||||||
|
DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */
|
||||||
|
|
||||||
|
DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */
|
||||||
|
|
||||||
|
uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */
|
||||||
|
|
||||||
|
DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */
|
||||||
|
|
||||||
|
DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */
|
||||||
|
|
||||||
|
uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */
|
||||||
|
} DMA_HandleTypeDef;
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @defgroup DMA_Exported_Constants DMA Exported Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DMA_Error_Code DMA Error Code
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
|
||||||
|
#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
|
||||||
|
#define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */
|
||||||
|
#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
|
||||||
|
#define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */
|
||||||
|
#define HAL_DMA_ERROR_BUSY 0x00000080U /*!< DMA Busy error */
|
||||||
|
#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */
|
||||||
|
#define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */
|
||||||
|
#define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DMA_request DMA request
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define DMA_REQUEST_MEM2MEM LL_DMAMUX_REQ_MEM2MEM /*!< memory to memory transfer */
|
||||||
|
#define DMA_REQUEST_GENERATOR0 LL_DMAMUX_REQ_GENERATOR0 /*!< DMAMUX request generator 0 */
|
||||||
|
#define DMA_REQUEST_GENERATOR1 LL_DMAMUX_REQ_GENERATOR1 /*!< DMAMUX request generator 1 */
|
||||||
|
#define DMA_REQUEST_GENERATOR2 LL_DMAMUX_REQ_GENERATOR2 /*!< DMAMUX request generator 2 */
|
||||||
|
#define DMA_REQUEST_GENERATOR3 LL_DMAMUX_REQ_GENERATOR3 /*!< DMAMUX request generator 3 */
|
||||||
|
#define DMA_REQUEST_ADC1 LL_DMAMUX_REQ_ADC1 /*!< DMAMUX ADC1 request */
|
||||||
|
#if defined(AES)
|
||||||
|
#define DMA_REQUEST_AES_IN LL_DMAMUX_REQ_AES_IN /*!< DMAMUX AES_IN request */
|
||||||
|
#define DMA_REQUEST_AES_OUT LL_DMAMUX_REQ_AES_OUT /*!< DMAMUX AES_OUT request */
|
||||||
|
#endif /* AES */
|
||||||
|
#if defined(DAC1)
|
||||||
|
#define DMA_REQUEST_DAC1_CH1 LL_DMAMUX_REQ_DAC1_CH1 /*!< DMAMUX DAC_CH1 request */
|
||||||
|
#define DMA_REQUEST_DAC1_CH2 LL_DMAMUX_REQ_DAC1_CH2 /*!< DMAMUX DAC_CH2 request */
|
||||||
|
#endif /* DAC1 */
|
||||||
|
#define DMA_REQUEST_I2C1_RX LL_DMAMUX_REQ_I2C1_RX /*!< DMAMUX I2C1 RX request */
|
||||||
|
#define DMA_REQUEST_I2C1_TX LL_DMAMUX_REQ_I2C1_TX /*!< DMAMUX I2C1 TX request */
|
||||||
|
#define DMA_REQUEST_I2C2_RX LL_DMAMUX_REQ_I2C2_RX /*!< DMAMUX I2C2 RX request */
|
||||||
|
#define DMA_REQUEST_I2C2_TX LL_DMAMUX_REQ_I2C2_TX /*!< DMAMUX I2C2 TX request */
|
||||||
|
#if defined(LPUART1)
|
||||||
|
#define DMA_REQUEST_LPUART1_RX LL_DMAMUX_REQ_LPUART1_RX /*!< DMAMUX LPUART1 RX request */
|
||||||
|
#define DMA_REQUEST_LPUART1_TX LL_DMAMUX_REQ_LPUART1_TX /*!< DMAMUX LPUART1 TX request */
|
||||||
|
#endif /* LPUART1 */
|
||||||
|
#define DMA_REQUEST_SPI1_RX LL_DMAMUX_REQ_SPI1_RX /*!< DMAMUX SPI1 RX request */
|
||||||
|
#define DMA_REQUEST_SPI1_TX LL_DMAMUX_REQ_SPI1_TX /*!< DMAMUX SPI1 TX request */
|
||||||
|
#define DMA_REQUEST_SPI2_RX LL_DMAMUX_REQ_SPI2_RX /*!< DMAMUX SPI2 RX request */
|
||||||
|
#define DMA_REQUEST_SPI2_TX LL_DMAMUX_REQ_SPI2_TX /*!< DMAMUX SPI2 TX request */
|
||||||
|
#define DMA_REQUEST_TIM1_CH1 LL_DMAMUX_REQ_TIM1_CH1 /*!< DMAMUX TIM1 CH1 request */
|
||||||
|
#define DMA_REQUEST_TIM1_CH2 LL_DMAMUX_REQ_TIM1_CH2 /*!< DMAMUX TIM1 CH2 request */
|
||||||
|
#define DMA_REQUEST_TIM1_CH3 LL_DMAMUX_REQ_TIM1_CH3 /*!< DMAMUX TIM1 CH3 request */
|
||||||
|
#define DMA_REQUEST_TIM1_CH4 LL_DMAMUX_REQ_TIM1_CH4 /*!< DMAMUX TIM1 CH4 request */
|
||||||
|
#define DMA_REQUEST_TIM1_TRIG_COM LL_DMAMUX_REQ_TIM1_TRIG_COM /*!< DMAMUX TIM1 TRIG COM request */
|
||||||
|
#define DMA_REQUEST_TIM1_UP LL_DMAMUX_REQ_TIM1_UP /*!< DMAMUX TIM1 UP request */
|
||||||
|
#if defined(TIM2)
|
||||||
|
#define DMA_REQUEST_TIM2_CH1 LL_DMAMUX_REQ_TIM2_CH1 /*!< DMAMUX TIM2 CH1 request */
|
||||||
|
#define DMA_REQUEST_TIM2_CH2 LL_DMAMUX_REQ_TIM2_CH2 /*!< DMAMUX TIM2 CH2 request */
|
||||||
|
#define DMA_REQUEST_TIM2_CH3 LL_DMAMUX_REQ_TIM2_CH3 /*!< DMAMUX TIM2 CH3 request */
|
||||||
|
#define DMA_REQUEST_TIM2_CH4 LL_DMAMUX_REQ_TIM2_CH4 /*!< DMAMUX TIM2 CH4 request */
|
||||||
|
#define DMA_REQUEST_TIM2_TRIG LL_DMAMUX_REQ_TIM2_TRIG /*!< DMAMUX TIM2 TRIG request */
|
||||||
|
#define DMA_REQUEST_TIM2_UP LL_DMAMUX_REQ_TIM2_UP /*!< DMAMUX TIM2 UP request */
|
||||||
|
#endif /* TIM2 */
|
||||||
|
#define DMA_REQUEST_TIM3_CH1 LL_DMAMUX_REQ_TIM3_CH1 /*!< DMAMUX TIM3 CH1 request */
|
||||||
|
#define DMA_REQUEST_TIM3_CH2 LL_DMAMUX_REQ_TIM3_CH2 /*!< DMAMUX TIM3 CH2 request */
|
||||||
|
#define DMA_REQUEST_TIM3_CH3 LL_DMAMUX_REQ_TIM3_CH3 /*!< DMAMUX TIM3 CH3 request */
|
||||||
|
#define DMA_REQUEST_TIM3_CH4 LL_DMAMUX_REQ_TIM3_CH4 /*!< DMAMUX TIM3 CH4 request */
|
||||||
|
#define DMA_REQUEST_TIM3_TRIG LL_DMAMUX_REQ_TIM3_TRIG /*!< DMAMUX TIM3 TRIG request */
|
||||||
|
#define DMA_REQUEST_TIM3_UP LL_DMAMUX_REQ_TIM3_UP /*!< DMAMUX TIM3 UP request */
|
||||||
|
#if defined(TIM6)
|
||||||
|
#define DMA_REQUEST_TIM6_UP LL_DMAMUX_REQ_TIM6_UP /*!< DMAMUX TIM6 UP request */
|
||||||
|
#endif /* TIM6 */
|
||||||
|
#if defined(TIM7)
|
||||||
|
#define DMA_REQUEST_TIM7_UP LL_DMAMUX_REQ_TIM7_UP /*!< DMAMUX TIM7 UP request */
|
||||||
|
#endif /* TIM7 */
|
||||||
|
#if defined(TIM15)
|
||||||
|
#define DMA_REQUEST_TIM15_CH1 LL_DMAMUX_REQ_TIM15_CH1 /*!< DMAMUX TIM15 CH1 request */
|
||||||
|
#define DMA_REQUEST_TIM15_CH2 LL_DMAMUX_REQ_TIM15_CH2 /*!< DMAMUX TIM15 CH2 request */
|
||||||
|
#define DMA_REQUEST_TIM15_TRIG_COM LL_DMAMUX_REQ_TIM15_TRIG_COM /*!< DMAMUX TIM15 TRIG COM request */
|
||||||
|
#define DMA_REQUEST_TIM15_UP LL_DMAMUX_REQ_TIM15_UP /*!< DMAMUX TIM15 UP request */
|
||||||
|
#endif /* TIM15 */
|
||||||
|
#define DMA_REQUEST_TIM16_CH1 LL_DMAMUX_REQ_TIM16_CH1 /*!< DMAMUX TIM16 CH1 request */
|
||||||
|
#define DMA_REQUEST_TIM16_COM LL_DMAMUX_REQ_TIM16_COM /*!< DMAMUX TIM16 COM request */
|
||||||
|
#define DMA_REQUEST_TIM16_UP LL_DMAMUX_REQ_TIM16_UP /*!< DMAMUX TIM16 UP request */
|
||||||
|
#define DMA_REQUEST_TIM17_CH1 LL_DMAMUX_REQ_TIM17_CH1 /*!< DMAMUX TIM17 CH1 request */
|
||||||
|
#define DMA_REQUEST_TIM17_COM LL_DMAMUX_REQ_TIM17_COM /*!< DMAMUX TIM17 COM request */
|
||||||
|
#define DMA_REQUEST_TIM17_UP LL_DMAMUX_REQ_TIM17_UP /*!< DMAMUX TIM17 UP request */
|
||||||
|
#define DMA_REQUEST_USART1_RX LL_DMAMUX_REQ_USART1_RX /*!< DMAMUX USART1 RX request */
|
||||||
|
#define DMA_REQUEST_USART1_TX LL_DMAMUX_REQ_USART1_TX /*!< DMAMUX USART1 TX request */
|
||||||
|
#define DMA_REQUEST_USART2_RX LL_DMAMUX_REQ_USART2_RX /*!< DMAMUX USART2 RX request */
|
||||||
|
#define DMA_REQUEST_USART2_TX LL_DMAMUX_REQ_USART2_TX /*!< DMAMUX USART2 TX request */
|
||||||
|
#if defined(USART3)
|
||||||
|
#define DMA_REQUEST_USART3_RX LL_DMAMUX_REQ_USART3_RX /*!< DMAMUX USART3 RX request */
|
||||||
|
#define DMA_REQUEST_USART3_TX LL_DMAMUX_REQ_USART3_TX /*!< DMAMUX USART3 TX request */
|
||||||
|
#endif /* USART3 */
|
||||||
|
#if defined(USART4)
|
||||||
|
#define DMA_REQUEST_USART4_RX LL_DMAMUX_REQ_USART4_RX /*!< DMAMUX USART4 RX request */
|
||||||
|
#define DMA_REQUEST_USART4_TX LL_DMAMUX_REQ_USART4_TX /*!< DMAMUX USART4 TX request */
|
||||||
|
#endif /* USART4 */
|
||||||
|
#if defined(UCPD1)
|
||||||
|
#define DMA_REQUEST_UCPD1_RX LL_DMAMUX_REQ_UCPD1_RX /*!< DMAMUX UCPD1 RX request */
|
||||||
|
#define DMA_REQUEST_UCPD1_TX LL_DMAMUX_REQ_UCPD1_TX /*!< DMAMUX UCPD1 TX request */
|
||||||
|
#endif/* UCPD1 */
|
||||||
|
#if defined(UCPD2)
|
||||||
|
#define DMA_REQUEST_UCPD2_RX LL_DMAMUX_REQ_UCPD2_RX /*!< DMAMUX UCPD2 RX request */
|
||||||
|
#define DMA_REQUEST_UCPD2_TX LL_DMAMUX_REQ_UCPD2_TX /*!< DMAMUX UCPD2 TX request */
|
||||||
|
#endif /* UCPD2 */
|
||||||
|
|
||||||
|
#if defined(I2C3)
|
||||||
|
#define DMA_REQUEST_I2C3_RX LL_DMAMUX_REQ_I2C3_RX /*!< DMAMUX I2C3 RX request */
|
||||||
|
#define DMA_REQUEST_I2C3_TX LL_DMAMUX_REQ_I2C3_TX /*!< DMAMUX I2C3 TX request */
|
||||||
|
#endif /* I2C3 */
|
||||||
|
|
||||||
|
#if defined(LPUART2)
|
||||||
|
#define DMA_REQUEST_LPUART2_RX LL_DMAMUX_REQ_LPUART2_RX /*!< DMAMUX LPUART2 RX request */
|
||||||
|
#define DMA_REQUEST_LPUART2_TX LL_DMAMUX_REQ_LPUART2_TX /*!< DMAMUX LPUART2 TX request */
|
||||||
|
#endif /* LPUART2 */
|
||||||
|
|
||||||
|
#if defined(SPI3)
|
||||||
|
#define DMA_REQUEST_SPI3_RX LL_DMAMUX_REQ_SPI3_RX /*!< DMAMUX SPI3 RX request */
|
||||||
|
#define DMA_REQUEST_SPI3_TX LL_DMAMUX_REQ_SPI3_TX /*!< DMAMUX SPI3 TX request */
|
||||||
|
#endif /* SPI3 */
|
||||||
|
|
||||||
|
#if defined(TIM4)
|
||||||
|
#define DMA_REQUEST_TIM4_CH1 LL_DMAMUX_REQ_TIM4_CH1 /*!< DMAMUX TIM4 CH1 request */
|
||||||
|
#define DMA_REQUEST_TIM4_CH2 LL_DMAMUX_REQ_TIM4_CH2 /*!< DMAMUX TIM4 CH2 request */
|
||||||
|
#define DMA_REQUEST_TIM4_CH3 LL_DMAMUX_REQ_TIM4_CH3 /*!< DMAMUX TIM4 CH3 request */
|
||||||
|
#define DMA_REQUEST_TIM4_CH4 LL_DMAMUX_REQ_TIM4_CH4 /*!< DMAMUX TIM4 CH4 request */
|
||||||
|
#define DMA_REQUEST_TIM4_TRIG LL_DMAMUX_REQ_TIM4_TRIG /*!< DMAMUX TIM4 TRIG request */
|
||||||
|
#define DMA_REQUEST_TIM4_UP LL_DMAMUX_REQ_TIM4_UP /*!< DMAMUX TIM4 UP request */
|
||||||
|
#endif /* TIM4 */
|
||||||
|
|
||||||
|
#if defined(USART5)
|
||||||
|
#define DMA_REQUEST_USART5_RX LL_DMAMUX_REQ_USART5_RX /*!< DMAMUX USART5 RX request */
|
||||||
|
#define DMA_REQUEST_USART5_TX LL_DMAMUX_REQ_USART5_TX /*!< DMAMUX USART5 TX request */
|
||||||
|
#endif /* USART5 */
|
||||||
|
|
||||||
|
#if defined(USART6)
|
||||||
|
#define DMA_REQUEST_USART6_RX LL_DMAMUX_REQ_USART6_RX /*!< DMAMUX USART6 RX request */
|
||||||
|
#define DMA_REQUEST_USART6_TX LL_DMAMUX_REQ_USART6_TX /*!< DMAMUX USART6 TX request */
|
||||||
|
#endif /* USART6 */
|
||||||
|
|
||||||
|
|
||||||
|
#define DMA_MAX_REQUEST LL_DMAMUX_MAX_REQ
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define DMA_PERIPH_TO_MEMORY LL_DMA_DIRECTION_PERIPH_TO_MEMORY /*!< Peripheral to memory direction */
|
||||||
|
#define DMA_MEMORY_TO_PERIPH LL_DMA_DIRECTION_MEMORY_TO_PERIPH /*!< Memory to peripheral direction */
|
||||||
|
#define DMA_MEMORY_TO_MEMORY LL_DMA_DIRECTION_MEMORY_TO_MEMORY /*!< Memory to memory direction */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define DMA_PINC_ENABLE LL_DMA_PERIPH_INCREMENT /*!< Peripheral increment mode Enable */
|
||||||
|
#define DMA_PINC_DISABLE LL_DMA_PERIPH_NOINCREMENT /*!< Peripheral increment mode Disable */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define DMA_MINC_ENABLE LL_DMA_MEMORY_INCREMENT /*!< Memory increment mode Enable */
|
||||||
|
#define DMA_MINC_DISABLE LL_DMA_MEMORY_NOINCREMENT /*!< Memory increment mode Disable */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define DMA_PDATAALIGN_BYTE LL_DMA_PDATAALIGN_BYTE /*!< Peripheral data alignment : Byte */
|
||||||
|
#define DMA_PDATAALIGN_HALFWORD LL_DMA_PDATAALIGN_HALFWORD /*!< Peripheral data alignment : HalfWord */
|
||||||
|
#define DMA_PDATAALIGN_WORD LL_DMA_PDATAALIGN_WORD /*!< Peripheral data alignment : Word */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DMA_Memory_data_size DMA Memory data size
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define DMA_MDATAALIGN_BYTE LL_DMA_MDATAALIGN_BYTE /*!< Memory data alignment : Byte */
|
||||||
|
#define DMA_MDATAALIGN_HALFWORD LL_DMA_MDATAALIGN_HALFWORD /*!< Memory data alignment : HalfWord */
|
||||||
|
#define DMA_MDATAALIGN_WORD LL_DMA_MDATAALIGN_WORD /*!< Memory data alignment : Word */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DMA_mode DMA mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define DMA_NORMAL LL_DMA_MODE_NORMAL /*!< Normal mode */
|
||||||
|
#define DMA_CIRCULAR LL_DMA_MODE_CIRCULAR /*!< Circular mode */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DMA_Priority_level DMA Priority level
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define DMA_PRIORITY_LOW LL_DMA_PRIORITY_LOW /*!< Priority level : Low */
|
||||||
|
#define DMA_PRIORITY_MEDIUM LL_DMA_PRIORITY_MEDIUM /*!< Priority level : Medium */
|
||||||
|
#define DMA_PRIORITY_HIGH LL_DMA_PRIORITY_HIGH /*!< Priority level : High */
|
||||||
|
#define DMA_PRIORITY_VERY_HIGH LL_DMA_PRIORITY_VERYHIGH /*!< Priority level : Very_High */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define DMA_IT_TC DMA_CCR_TCIE /*!< Transfer Complete interrupt */
|
||||||
|
#define DMA_IT_HT DMA_CCR_HTIE /*!< Half Transfer Complete interrupt */
|
||||||
|
#define DMA_IT_TE DMA_CCR_TEIE /*!< Transfer Error interrupt */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DMA_flag_definitions DMA flag definitions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define DMA_FLAG_GI1 DMA_ISR_GIF1 /*!< Global Interrupt flag for Channel 1 */
|
||||||
|
#define DMA_FLAG_TC1 DMA_ISR_TCIF1 /*!< Transfer Complete flag for Channel 1 */
|
||||||
|
#define DMA_FLAG_HT1 DMA_ISR_HTIF1 /*!< Half Transfer flag for Channel 1 */
|
||||||
|
#define DMA_FLAG_TE1 DMA_ISR_TEIF1 /*!< Transfer Error flag for Channel 1 */
|
||||||
|
#define DMA_FLAG_GI2 DMA_ISR_GIF2 /*!< Global Interrupt flag for Channel 2 */
|
||||||
|
#define DMA_FLAG_TC2 DMA_ISR_TCIF2 /*!< Transfer Complete flag for Channel 2 */
|
||||||
|
#define DMA_FLAG_HT2 DMA_ISR_HTIF2 /*!< Half Transfer flag for Channel 2 */
|
||||||
|
#define DMA_FLAG_TE2 DMA_ISR_TEIF2 /*!< Transfer Error flag for Channel 2 */
|
||||||
|
#define DMA_FLAG_GI3 DMA_ISR_GIF3 /*!< Global Interrupt flag for Channel 3 */
|
||||||
|
#define DMA_FLAG_TC3 DMA_ISR_TCIF3 /*!< Transfer Complete flag for Channel 3 */
|
||||||
|
#define DMA_FLAG_HT3 DMA_ISR_HTIF3 /*!< Half Transfer flag for Channel 3 */
|
||||||
|
#define DMA_FLAG_TE3 DMA_ISR_TEIF3 /*!< Transfer Error flag for Channel 3 */
|
||||||
|
#define DMA_FLAG_GI4 DMA_ISR_GIF4 /*!< Global Interrupt flag for Channel 4 */
|
||||||
|
#define DMA_FLAG_TC4 DMA_ISR_TCIF4 /*!< Transfer Complete flag for Channel 4 */
|
||||||
|
#define DMA_FLAG_HT4 DMA_ISR_HTIF4 /*!< Half Transfer flag for Channel 4 */
|
||||||
|
#define DMA_FLAG_TE4 DMA_ISR_TEIF4 /*!< Transfer Error flag for Channel 4 */
|
||||||
|
#define DMA_FLAG_GI5 DMA_ISR_GIF5 /*!< Global Interrupt flag for Channel 5 */
|
||||||
|
#define DMA_FLAG_TC5 DMA_ISR_TCIF5 /*!< Transfer Complete flag for Channel 5 */
|
||||||
|
#define DMA_FLAG_HT5 DMA_ISR_HTIF5 /*!< Half Transfer flag for Channel 5 */
|
||||||
|
#define DMA_FLAG_TE5 DMA_ISR_TEIF5 /*!< Transfer Error for Channel 5 */
|
||||||
|
#if defined(DMA1_Channel6)
|
||||||
|
#define DMA_FLAG_GI6 DMA_ISR_GIF6 /*!< Global Interrupt flag for Channel 6 */
|
||||||
|
#define DMA_FLAG_TC6 DMA_ISR_TCIF6 /*!< Transfer Complete flag for Channel 6 */
|
||||||
|
#define DMA_FLAG_HT6 DMA_ISR_HTIF6 /*!< Half Transfer flag for Channel 6 */
|
||||||
|
#define DMA_FLAG_TE6 DMA_ISR_TEIF6 /*!< Transfer Error flag for Channel 6 */
|
||||||
|
#endif /* DMA1_Channel6 */
|
||||||
|
#if defined(DMA1_Channel7)
|
||||||
|
#define DMA_FLAG_GI7 DMA_ISR_GIF7 /*!< Global Interrupt flag for Channel 7 */
|
||||||
|
#define DMA_FLAG_TC7 DMA_ISR_TCIF7 /*!< Transfer Complete flag for Channel 7 */
|
||||||
|
#define DMA_FLAG_HT7 DMA_ISR_HTIF7 /*!< Half Transfer flag for Channel 7 */
|
||||||
|
#define DMA_FLAG_TE7 DMA_ISR_TEIF7 /*!< Transfer Error flag for Channel 7 */
|
||||||
|
#endif /* DMA1_Channel7 */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported macros -----------------------------------------------------------*/
|
||||||
|
/** @defgroup DMA_Exported_Macros DMA Exported Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @brief Reset DMA handle state
|
||||||
|
* @param __HANDLE__ DMA handle
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable the specified DMA Channel.
|
||||||
|
* @param __HANDLE__ DMA handle
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable the specified DMA Channel.
|
||||||
|
* @param __HANDLE__ DMA handle
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the current DMA Channel transfer complete flag.
|
||||||
|
* @param __HANDLE__ DMA handle
|
||||||
|
* @retval The specified transfer complete flag index.
|
||||||
|
*/
|
||||||
|
#if defined(DMA2)
|
||||||
|
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
|
||||||
|
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
|
||||||
|
DMA_FLAG_TC7)
|
||||||
|
#else /* DMA1 */
|
||||||
|
#if defined(DMA1_Channel7)
|
||||||
|
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
|
||||||
|
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
|
||||||
|
DMA_FLAG_TC7)
|
||||||
|
#else
|
||||||
|
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
|
||||||
|
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
|
||||||
|
DMA_FLAG_TC5)
|
||||||
|
#endif /* DMA1_Channel8 */
|
||||||
|
#endif /* DMA2 */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the current DMA Channel half transfer complete flag.
|
||||||
|
* @param __HANDLE__ DMA handle
|
||||||
|
* @retval The specified half transfer complete flag index.
|
||||||
|
*/
|
||||||
|
#if defined(DMA2)
|
||||||
|
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \
|
||||||
|
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
|
||||||
|
DMA_FLAG_HT7)
|
||||||
|
#else /* DMA1 */
|
||||||
|
#if defined(DMA1_Channel7)
|
||||||
|
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \
|
||||||
|
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
|
||||||
|
DMA_FLAG_HT7)
|
||||||
|
#else
|
||||||
|
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \
|
||||||
|
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
|
||||||
|
DMA_FLAG_HT5)
|
||||||
|
#endif /* DMA1_Channel8 */
|
||||||
|
#endif /* DMA2 */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the current DMA Channel transfer error flag.
|
||||||
|
* @param __HANDLE__ DMA handle
|
||||||
|
* @retval The specified transfer error flag index.
|
||||||
|
*/
|
||||||
|
#if defined(DMA2)
|
||||||
|
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \
|
||||||
|
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
|
||||||
|
DMA_FLAG_TE7)
|
||||||
|
#else /* DMA1 */
|
||||||
|
#if defined(DMA1_Channel7)
|
||||||
|
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \
|
||||||
|
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
|
||||||
|
DMA_FLAG_TE7)
|
||||||
|
#else
|
||||||
|
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \
|
||||||
|
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
|
||||||
|
DMA_FLAG_TE5)
|
||||||
|
#endif /* DMA1_Channel8 */
|
||||||
|
#endif /* DMA2 */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Return the current DMA Channel Global interrupt flag.
|
||||||
|
* @param __HANDLE__ DMA handle
|
||||||
|
* @retval The specified transfer error flag index.
|
||||||
|
*/
|
||||||
|
#if defined(DMA2)
|
||||||
|
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \
|
||||||
|
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GI1 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GI1 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GI2 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GI2 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GI3 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GI3 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GI4 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GI4 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GI5 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_GI5 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GI6 :\
|
||||||
|
DMA_FLAG_GI7)
|
||||||
|
#else /* DMA1 */
|
||||||
|
#if defined(DMA1_Channel7)
|
||||||
|
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \
|
||||||
|
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GI1 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GI2 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GI3 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GI4 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GI5 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GI6 :\
|
||||||
|
DMA_FLAG_GI7)
|
||||||
|
#else
|
||||||
|
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \
|
||||||
|
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GI1 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GI2 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GI3 :\
|
||||||
|
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GI4 :\
|
||||||
|
DMA_FLAG_GI5)
|
||||||
|
#endif /* DMA1_Channel8 */
|
||||||
|
#endif /* DMA2 */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the DMA Channel pending flags.
|
||||||
|
* @param __HANDLE__ DMA handle
|
||||||
|
* @param __FLAG__ Get the specified flag.
|
||||||
|
* This parameter can be any combination of the following values:
|
||||||
|
* @arg DMA_FLAG_TCx: Transfer complete flag
|
||||||
|
* @arg DMA_FLAG_HTx: Half transfer complete flag
|
||||||
|
* @arg DMA_FLAG_TEx: Transfer error flag
|
||||||
|
* @arg DMA_FLAG_GIx: Global interrupt flag
|
||||||
|
* Where x can be 1 to max Channel supported by the product to select the DMA Channel flag.
|
||||||
|
* @retval The state of FLAG (SET or RESET).
|
||||||
|
*/
|
||||||
|
#if defined(DMA2)
|
||||||
|
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
|
||||||
|
(DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
|
||||||
|
#else /* DMA1 */
|
||||||
|
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
|
||||||
|
#endif /* DMA2 */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear the DMA Channel pending flags.
|
||||||
|
* @param __HANDLE__ DMA handle
|
||||||
|
* @param __FLAG__ specifies the flag to clear.
|
||||||
|
* This parameter can be any combination of the following values:
|
||||||
|
* @arg DMA_FLAG_TCx: Transfer complete flag
|
||||||
|
* @arg DMA_FLAG_HTx: Half transfer complete flag
|
||||||
|
* @arg DMA_FLAG_TEx: Transfer error flag
|
||||||
|
* @arg DMA_FLAG_GIx: Global interrupt flag
|
||||||
|
* Where x can be 1 to max Channel supported by the product to select the DMA Channel flag.
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#if defined(DMA2)
|
||||||
|
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
|
||||||
|
(DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
|
||||||
|
#else /* DMA1 */
|
||||||
|
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR |= (__FLAG__))
|
||||||
|
#endif /* DMA2 */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable the specified DMA Channel interrupts.
|
||||||
|
* @param __HANDLE__ DMA handle
|
||||||
|
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
|
||||||
|
* This parameter can be any combination of the following values:
|
||||||
|
* @arg DMA_IT_TC: Transfer complete interrupt mask
|
||||||
|
* @arg DMA_IT_HT: Half transfer complete interrupt mask
|
||||||
|
* @arg DMA_IT_TE: Transfer error interrupt mask
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable the specified DMA Channel interrupts.
|
||||||
|
* @param __HANDLE__ DMA handle
|
||||||
|
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
|
||||||
|
* This parameter can be any combination of the following values:
|
||||||
|
* @arg DMA_IT_TC: Transfer complete interrupt mask
|
||||||
|
* @arg DMA_IT_HT: Half transfer complete interrupt mask
|
||||||
|
* @arg DMA_IT_TE: Transfer error interrupt mask
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check whether the specified DMA Channel interrupt is enabled or disabled.
|
||||||
|
* @param __HANDLE__ DMA handle
|
||||||
|
* @param __INTERRUPT__ specifies the DMA interrupt source to check.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg DMA_IT_TC: Transfer complete interrupt mask
|
||||||
|
* @arg DMA_IT_HT: Half transfer complete interrupt mask
|
||||||
|
* @arg DMA_IT_TE: Transfer error interrupt mask
|
||||||
|
* @retval The state of DMA_IT (SET or RESET).
|
||||||
|
*/
|
||||||
|
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Returns the number of remaining data units in the current DMA Channel transfer.
|
||||||
|
* @param __HANDLE__ DMA handle
|
||||||
|
* @retval The number of remaining data units in the current DMA Channel transfer.
|
||||||
|
*/
|
||||||
|
#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Include DMA HAL Extension module */
|
||||||
|
#include "stm32g0xx_hal_dma_ex.h"
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @addtogroup DMA_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup DMA_Exported_Functions_Group1
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Initialization and de-initialization functions *****************************/
|
||||||
|
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
|
||||||
|
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup DMA_Exported_Functions_Group2
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* IO operation functions *****************************************************/
|
||||||
|
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
||||||
|
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress,
|
||||||
|
uint32_t DataLength);
|
||||||
|
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
|
||||||
|
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
|
||||||
|
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel,
|
||||||
|
uint32_t Timeout);
|
||||||
|
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
|
||||||
|
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
|
||||||
|
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup DMA_Exported_Functions_Group3
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Peripheral State and Error functions ***************************************/
|
||||||
|
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
|
||||||
|
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
/** @defgroup DMA_Private_Macros DMA Private Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
|
||||||
|
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
|
||||||
|
((DIRECTION) == DMA_MEMORY_TO_MEMORY))
|
||||||
|
|
||||||
|
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < DMA_CNDTR_NDT))
|
||||||
|
|
||||||
|
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
|
||||||
|
((STATE) == DMA_PINC_DISABLE))
|
||||||
|
|
||||||
|
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
|
||||||
|
((STATE) == DMA_MINC_DISABLE))
|
||||||
|
|
||||||
|
#define IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_MAX_REQUEST)
|
||||||
|
|
||||||
|
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
|
||||||
|
((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
|
||||||
|
((SIZE) == DMA_PDATAALIGN_WORD))
|
||||||
|
|
||||||
|
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
|
||||||
|
((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
|
||||||
|
((SIZE) == DMA_MDATAALIGN_WORD ))
|
||||||
|
|
||||||
|
#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
|
||||||
|
((MODE) == DMA_CIRCULAR))
|
||||||
|
|
||||||
|
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
|
||||||
|
((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
|
||||||
|
((PRIORITY) == DMA_PRIORITY_HIGH) || \
|
||||||
|
((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private functions ---------------------------------------------------------*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* STM32G0xx_HAL_DMA_H */
|
||||||
|
|
||||||
278
Boot/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h
Normal file
278
Boot/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h
Normal file
@@ -0,0 +1,278 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32g0xx_hal_dma_ex.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @brief Header file of DMA HAL extension module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* Copyright (c) 2018 STMicroelectronics.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* This software is licensed under terms that can be found in the LICENSE file
|
||||||
|
* in the root directory of this software component.
|
||||||
|
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef STM32G0xx_HAL_DMA_EX_H
|
||||||
|
#define STM32G0xx_HAL_DMA_EX_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32g0xx_hal_def.h"
|
||||||
|
#include "stm32g0xx_ll_dmamux.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32G0xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup DMAEx
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief HAL DMAMUX Synchronization configuration structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t SyncSignalID; /*!< Specifies the synchronization signal gating the DMA request in periodic mode.
|
||||||
|
This parameter can be a value of @ref DMAEx_DMAMUX_SyncSignalID_selection */
|
||||||
|
|
||||||
|
uint32_t SyncPolarity; /*!< Specifies the polarity of the signal on which the DMA request is synchronized.
|
||||||
|
This parameter can be a value of @ref DMAEx_DMAMUX_SyncPolarity_selection */
|
||||||
|
|
||||||
|
FunctionalState SyncEnable; /*!< Specifies if the synchronization shall be enabled or disabled
|
||||||
|
This parameter can take the value ENABLE or DISABLE */
|
||||||
|
|
||||||
|
FunctionalState EventEnable; /*!< Specifies if an event shall be generated once the RequestNumber is reached.
|
||||||
|
This parameter can take the value ENABLE or DISABLE */
|
||||||
|
|
||||||
|
uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event
|
||||||
|
This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
|
||||||
|
|
||||||
|
|
||||||
|
} HAL_DMA_MuxSyncConfigTypeDef;
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief HAL DMAMUX request generator parameters structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request generator
|
||||||
|
This parameter can be a value of @ref DMAEx_DMAMUX_SignalGeneratorID_selection */
|
||||||
|
|
||||||
|
uint32_t Polarity; /*!< Specifies the polarity of the signal on which the request is generated.
|
||||||
|
This parameter can be a value of @ref DMAEx_DMAMUX_RequestGeneneratorPolarity_selection */
|
||||||
|
|
||||||
|
uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be generated after a signal event
|
||||||
|
This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
|
||||||
|
|
||||||
|
} HAL_DMA_MuxRequestGeneratorConfigTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DMAEx_DMAMUX_SyncSignalID_selection DMAMUX SyncSignalID selection
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define HAL_DMAMUX1_SYNC_EXTI0 LL_DMAMUX_SYNC_EXTI_LINE0 /*!< Synchronization signal from EXTI Line0 */
|
||||||
|
#define HAL_DMAMUX1_SYNC_EXTI1 LL_DMAMUX_SYNC_EXTI_LINE1 /*!< Synchronization signal from EXTI Line1 */
|
||||||
|
#define HAL_DMAMUX1_SYNC_EXTI2 LL_DMAMUX_SYNC_EXTI_LINE2 /*!< Synchronization signal from EXTI Line2 */
|
||||||
|
#define HAL_DMAMUX1_SYNC_EXTI3 LL_DMAMUX_SYNC_EXTI_LINE3 /*!< Synchronization signal from EXTI Line3 */
|
||||||
|
#define HAL_DMAMUX1_SYNC_EXTI4 LL_DMAMUX_SYNC_EXTI_LINE4 /*!< Synchronization signal from EXTI Line4 */
|
||||||
|
#define HAL_DMAMUX1_SYNC_EXTI5 LL_DMAMUX_SYNC_EXTI_LINE5 /*!< Synchronization signal from EXTI Line5 */
|
||||||
|
#define HAL_DMAMUX1_SYNC_EXTI6 LL_DMAMUX_SYNC_EXTI_LINE6 /*!< Synchronization signal from EXTI Line6 */
|
||||||
|
#define HAL_DMAMUX1_SYNC_EXTI7 LL_DMAMUX_SYNC_EXTI_LINE7 /*!< Synchronization signal from EXTI Line7 */
|
||||||
|
#define HAL_DMAMUX1_SYNC_EXTI8 LL_DMAMUX_SYNC_EXTI_LINE8 /*!< Synchronization signal from EXTI Line8 */
|
||||||
|
#define HAL_DMAMUX1_SYNC_EXTI9 LL_DMAMUX_SYNC_EXTI_LINE9 /*!< Synchronization signal from EXTI Line9 */
|
||||||
|
#define HAL_DMAMUX1_SYNC_EXTI10 LL_DMAMUX_SYNC_EXTI_LINE10 /*!< Synchronization signal from EXTI Line10 */
|
||||||
|
#define HAL_DMAMUX1_SYNC_EXTI11 LL_DMAMUX_SYNC_EXTI_LINE11 /*!< Synchronization signal from EXTI Line11 */
|
||||||
|
#define HAL_DMAMUX1_SYNC_EXTI12 LL_DMAMUX_SYNC_EXTI_LINE12 /*!< Synchronization signal from EXTI Line12 */
|
||||||
|
#define HAL_DMAMUX1_SYNC_EXTI13 LL_DMAMUX_SYNC_EXTI_LINE13 /*!< Synchronization signal from EXTI Line1 3 */
|
||||||
|
#define HAL_DMAMUX1_SYNC_EXTI14 LL_DMAMUX_SYNC_EXTI_LINE14 /*!< Synchronization signal from EXTI Line1 4 */
|
||||||
|
#define HAL_DMAMUX1_SYNC_EXTI15 LL_DMAMUX_SYNC_EXTI_LINE15 /*!< Synchronization signal from EXTI Line1 5 */
|
||||||
|
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT LL_DMAMUX_SYNC_DMAMUX_CH0 /*!< Synchronization signal from DMAMUX channel0 Event */
|
||||||
|
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT LL_DMAMUX_SYNC_DMAMUX_CH1 /*!< Synchronization signal from DMAMUX channel1 Event */
|
||||||
|
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT LL_DMAMUX_SYNC_DMAMUX_CH2 /*!< Synchronization signal from DMAMUX channel2 Event */
|
||||||
|
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT LL_DMAMUX_SYNC_DMAMUX_CH3 /*!< Synchronization signal from DMAMUX channel3 Event */
|
||||||
|
#if defined(LPTIM1)
|
||||||
|
#define HAL_DMAMUX1_SYNC_LPTIM1_OUT LL_DMAMUX_SYNC_LPTIM1_OUT /*!< Synchronization signal from LPTIM1 Output */
|
||||||
|
#endif /* LPTIM1 */
|
||||||
|
#if defined(LPTIM2)
|
||||||
|
#define HAL_DMAMUX1_SYNC_LPTIM2_OUT LL_DMAMUX_SYNC_LPTIM2_OUT /*!< Synchronization signal from LPTIM2 Output */
|
||||||
|
#endif /* LPTIM2 */
|
||||||
|
#define HAL_DMAMUX1_SYNC_TIM14_OC LL_DMAMUX_SYNC_TIM14_OC /*!< Synchronization signal from TIM14 OC */
|
||||||
|
|
||||||
|
#define HAL_DMAMUX1_MAX_SYNC HAL_DMAMUX1_SYNC_TIM14_OC
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DMAEx_DMAMUX_SyncPolarity_selection DMAMUX SyncPolarity selection
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define HAL_DMAMUX_SYNC_NO_EVENT LL_DMAMUX_SYNC_NO_EVENT /*!< block synchronization events */
|
||||||
|
#define HAL_DMAMUX_SYNC_RISING LL_DMAMUX_SYNC_POL_RISING /*!< synchronize with rising edge events */
|
||||||
|
#define HAL_DMAMUX_SYNC_FALLING LL_DMAMUX_SYNC_POL_FALLING /*!< synchronize with falling edge events */
|
||||||
|
#define HAL_DMAMUX_SYNC_RISING_FALLING LL_DMAMUX_SYNC_POL_RISING_FALLING /*!< synchronize with rising and falling edge events */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DMAEx_DMAMUX_SignalGeneratorID_selection DMAMUX SignalGeneratorID selection
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define HAL_DMAMUX1_REQ_GEN_EXTI0 LL_DMAMUX_REQ_GEN_EXTI_LINE0 /*!< Request signal generation from EXTI Line0 */
|
||||||
|
#define HAL_DMAMUX1_REQ_GEN_EXTI1 LL_DMAMUX_REQ_GEN_EXTI_LINE1 /*!< Request signal generation from EXTI Line1 */
|
||||||
|
#define HAL_DMAMUX1_REQ_GEN_EXTI2 LL_DMAMUX_REQ_GEN_EXTI_LINE2 /*!< Request signal generation from EXTI Line2 */
|
||||||
|
#define HAL_DMAMUX1_REQ_GEN_EXTI3 LL_DMAMUX_REQ_GEN_EXTI_LINE3 /*!< Request signal generation from EXTI Line3 */
|
||||||
|
#define HAL_DMAMUX1_REQ_GEN_EXTI4 LL_DMAMUX_REQ_GEN_EXTI_LINE4 /*!< Request signal generation from EXTI Line4 */
|
||||||
|
#define HAL_DMAMUX1_REQ_GEN_EXTI5 LL_DMAMUX_REQ_GEN_EXTI_LINE5 /*!< Request signal generation from EXTI Line5 */
|
||||||
|
#define HAL_DMAMUX1_REQ_GEN_EXTI6 LL_DMAMUX_REQ_GEN_EXTI_LINE6 /*!< Request signal generation from EXTI Line6 */
|
||||||
|
#define HAL_DMAMUX1_REQ_GEN_EXTI7 LL_DMAMUX_REQ_GEN_EXTI_LINE7 /*!< Request signal generation from EXTI Line7 */
|
||||||
|
#define HAL_DMAMUX1_REQ_GEN_EXTI8 LL_DMAMUX_REQ_GEN_EXTI_LINE8 /*!< Request signal generation from EXTI Line8 */
|
||||||
|
#define HAL_DMAMUX1_REQ_GEN_EXTI9 LL_DMAMUX_REQ_GEN_EXTI_LINE9 /*!< Request signal generation from EXTI Line9 */
|
||||||
|
#define HAL_DMAMUX1_REQ_GEN_EXTI10 LL_DMAMUX_REQ_GEN_EXTI_LINE10 /*!< Request signal generation from EXTI Line10 */
|
||||||
|
#define HAL_DMAMUX1_REQ_GEN_EXTI11 LL_DMAMUX_REQ_GEN_EXTI_LINE11 /*!< Request signal generation from EXTI Line11 */
|
||||||
|
#define HAL_DMAMUX1_REQ_GEN_EXTI12 LL_DMAMUX_REQ_GEN_EXTI_LINE12 /*!< Request signal generation from EXTI Line12 */
|
||||||
|
#define HAL_DMAMUX1_REQ_GEN_EXTI13 LL_DMAMUX_REQ_GEN_EXTI_LINE13 /*!< Request signal generation from EXTI Line13 */
|
||||||
|
#define HAL_DMAMUX1_REQ_GEN_EXTI14 LL_DMAMUX_REQ_GEN_EXTI_LINE14 /*!< Request signal generation from EXTI Line14 */
|
||||||
|
#define HAL_DMAMUX1_REQ_GEN_EXTI15 LL_DMAMUX_REQ_GEN_EXTI_LINE15 /*!< Request signal generation from EXTI Line15 */
|
||||||
|
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH0 /*!< Request signal generation from DMAMUX channel0 Event */
|
||||||
|
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH1 /*!< Request signal generation from DMAMUX channel1 Event */
|
||||||
|
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH2 /*!< Request signal generation from DMAMUX channel2 Event */
|
||||||
|
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH3 /*!< Request signal generation from DMAMUX channel3 Event */
|
||||||
|
#if defined(LPTIM1)
|
||||||
|
#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT LL_DMAMUX_REQ_GEN_LPTIM1_OUT /*!< Request signal generation from LPTIM1 Output */
|
||||||
|
#endif /* LPTIM1 */
|
||||||
|
#if defined(LPTIM2)
|
||||||
|
#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT LL_DMAMUX_REQ_GEN_LPTIM2_OUT /*!< Request signal generation from LPTIM2 Output */
|
||||||
|
#endif /* LPTIM2 */
|
||||||
|
#define HAL_DMAMUX1_REQ_GEN_TIM14_OC LL_DMAMUX_REQ_GEN_TIM14_OC /*!< Request signal generation from TIM14 OC */
|
||||||
|
|
||||||
|
#define HAL_DMAMUX1_MAX_REQ_GEN HAL_DMAMUX1_REQ_GEN_TIM14_OC
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX RequestGeneneratorPolarity selection
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define HAL_DMAMUX_REQ_GEN_NO_EVENT LL_DMAMUX_REQ_GEN_NO_EVENT /*!< block request generator events */
|
||||||
|
#define HAL_DMAMUX_REQ_GEN_RISING LL_DMAMUX_REQ_GEN_POL_RISING /*!< generate request on rising edge events */
|
||||||
|
#define HAL_DMAMUX_REQ_GEN_FALLING LL_DMAMUX_REQ_GEN_POL_FALLING /*!< generate request on falling edge events */
|
||||||
|
#define HAL_DMAMUX_REQ_GEN_RISING_FALLING LL_DMAMUX_REQ_GEN_POL_RISING_FALLING /*!< generate request on rising and falling edge events */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @addtogroup DMAEx_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* IO operation functions *****************************************************/
|
||||||
|
/** @addtogroup DMAEx_Exported_Functions_Group1
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* ------------------------- REQUEST -----------------------------------------*/
|
||||||
|
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma,
|
||||||
|
HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
|
||||||
|
HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
|
||||||
|
HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
|
||||||
|
/* -------------------------------------------------------------------------- */
|
||||||
|
|
||||||
|
/* ------------------------- SYNCHRO -----------------------------------------*/
|
||||||
|
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig);
|
||||||
|
/* -------------------------------------------------------------------------- */
|
||||||
|
|
||||||
|
void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
/** @defgroup DMAEx_Private_Macros DMAEx Private Macros
|
||||||
|
* @brief DMAEx private macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) (((SIGNAL_ID) == HAL_DMAMUX1_SYNC_EXTI0) || \
|
||||||
|
(((SIGNAL_ID) >= HAL_DMAMUX1_SYNC_EXTI1) && \
|
||||||
|
((SIGNAL_ID) <= HAL_DMAMUX1_MAX_SYNC)))
|
||||||
|
|
||||||
|
#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
|
||||||
|
|
||||||
|
#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \
|
||||||
|
((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \
|
||||||
|
((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || \
|
||||||
|
((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))
|
||||||
|
|
||||||
|
#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE))
|
||||||
|
|
||||||
|
#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \
|
||||||
|
((EVENT) == ENABLE))
|
||||||
|
|
||||||
|
#define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) (((SIGNAL_ID) == HAL_DMAMUX1_REQ_GEN_EXTI0) || \
|
||||||
|
(((SIGNAL_ID) >= HAL_DMAMUX1_REQ_GEN_EXTI1) && \
|
||||||
|
((SIGNAL_ID) <= HAL_DMAMUX1_MAX_REQ_GEN)))
|
||||||
|
|
||||||
|
#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
|
||||||
|
|
||||||
|
#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT)|| \
|
||||||
|
((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING) || \
|
||||||
|
((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \
|
||||||
|
((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* STM32G0xx_HAL_DMA_EX_H */
|
||||||
|
|
||||||
387
Boot/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h
Normal file
387
Boot/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h
Normal file
@@ -0,0 +1,387 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32g0xx_hal_exti.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @brief Header file of EXTI HAL module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* Copyright (c) 2018 STMicroelectronics.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* This software is licensed under terms that can be found in the LICENSE file
|
||||||
|
* in the root directory of this software component.
|
||||||
|
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef STM32G0xx_HAL_EXTI_H
|
||||||
|
#define STM32G0xx_HAL_EXTI_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32g0xx_hal_def.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32G0xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI EXTI
|
||||||
|
* @brief EXTI HAL module driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_Exported_Types EXTI Exported Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_EXTI_COMMON_CB_ID = 0x00U,
|
||||||
|
HAL_EXTI_RISING_CB_ID = 0x01U,
|
||||||
|
HAL_EXTI_FALLING_CB_ID = 0x02U,
|
||||||
|
} EXTI_CallbackIDTypeDef;
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief EXTI Handle structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t Line; /*!< Exti line number */
|
||||||
|
void (* RisingCallback)(void); /*!< Exti rising callback */
|
||||||
|
void (* FallingCallback)(void); /*!< Exti falling callback */
|
||||||
|
} EXTI_HandleTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief EXTI Configuration structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t Line; /*!< The Exti line to be configured. This parameter
|
||||||
|
can be a value of @ref EXTI_Line */
|
||||||
|
uint32_t Mode; /*!< The Exit Mode to be configured for a core.
|
||||||
|
This parameter can be a combination of @ref EXTI_Mode */
|
||||||
|
uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
|
||||||
|
can be a value of @ref EXTI_Trigger */
|
||||||
|
uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
|
||||||
|
This parameter is only possible for line 0 to 15. It
|
||||||
|
can be a value of @ref EXTI_GPIOSel */
|
||||||
|
} EXTI_ConfigTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_Line EXTI Line
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | 0x00u)
|
||||||
|
#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | 0x01u)
|
||||||
|
#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | 0x02u)
|
||||||
|
#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | 0x03u)
|
||||||
|
#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | 0x04u)
|
||||||
|
#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | 0x05u)
|
||||||
|
#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | 0x06u)
|
||||||
|
#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | 0x07u)
|
||||||
|
#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | 0x08u)
|
||||||
|
#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | 0x09u)
|
||||||
|
#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | 0x0Au)
|
||||||
|
#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | 0x0Bu)
|
||||||
|
#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | 0x0Cu)
|
||||||
|
#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | 0x0Du)
|
||||||
|
#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | 0x0Eu)
|
||||||
|
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | 0x0Fu)
|
||||||
|
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10u)
|
||||||
|
#if defined(COMP1)
|
||||||
|
#define EXTI_LINE_17 (EXTI_CONFIG | EXTI_REG1 | 0x11u)
|
||||||
|
#else
|
||||||
|
#define EXTI_LINE_17 (EXTI_RESERVED | EXTI_REG1 | 0x11u)
|
||||||
|
#endif /* COMP1 */
|
||||||
|
#if defined(COMP2)
|
||||||
|
#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | 0x12u)
|
||||||
|
#else
|
||||||
|
#define EXTI_LINE_18 (EXTI_RESERVED | EXTI_REG1 | 0x12u)
|
||||||
|
#endif /* COMP2 */
|
||||||
|
#define EXTI_LINE_19 (EXTI_DIRECT | EXTI_REG1 | 0x13u)
|
||||||
|
#if defined(COMP3)
|
||||||
|
#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | 0x14u)
|
||||||
|
#else
|
||||||
|
#define EXTI_LINE_20 (EXTI_RESERVED | EXTI_REG1 | 0x14u)
|
||||||
|
#endif /* COMP3 */
|
||||||
|
#define EXTI_LINE_21 (EXTI_DIRECT | EXTI_REG1 | 0x15u)
|
||||||
|
#if defined(RCC_CCIPR_I2C2SEL)
|
||||||
|
#define EXTI_LINE_22 (EXTI_DIRECT | EXTI_REG1 | 0x16u)
|
||||||
|
#else
|
||||||
|
#define EXTI_LINE_22 (EXTI_RESERVED | EXTI_REG1 | 0x16u)
|
||||||
|
#endif /* RCC_CCIPR_I2C2SEL */
|
||||||
|
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17u)
|
||||||
|
#if defined(RCC_CCIPR_USART3SEL)
|
||||||
|
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18u)
|
||||||
|
#else
|
||||||
|
#define EXTI_LINE_24 (EXTI_RESERVED | EXTI_REG1 | 0x18u)
|
||||||
|
#endif /* RCC_CCIPR_USART3SEL */
|
||||||
|
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19u)
|
||||||
|
#if defined(RCC_CCIPR_USART2SEL)
|
||||||
|
#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | 0x1Au)
|
||||||
|
#else
|
||||||
|
#define EXTI_LINE_26 (EXTI_RESERVED | EXTI_REG1 | 0x1Au)
|
||||||
|
#endif /* RCC_CCIPR_USART2SEL */
|
||||||
|
#if defined(CEC)
|
||||||
|
#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | 0x1Bu)
|
||||||
|
#else
|
||||||
|
#define EXTI_LINE_27 (EXTI_RESERVED | EXTI_REG1 | 0x1Bu)
|
||||||
|
#endif /* CEC */
|
||||||
|
#if defined(LPUART1)
|
||||||
|
#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1Cu)
|
||||||
|
#else
|
||||||
|
#define EXTI_LINE_28 (EXTI_RESERVED | EXTI_REG1 | 0x1Cu)
|
||||||
|
#endif /* LPUART1 */
|
||||||
|
#if defined(LPTIM1)
|
||||||
|
#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | 0x1Du)
|
||||||
|
#else
|
||||||
|
#define EXTI_LINE_29 (EXTI_RESERVED | EXTI_REG1 | 0x1Du)
|
||||||
|
#endif /* LPTIM1 */
|
||||||
|
#if defined(LPTIM2)
|
||||||
|
#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | 0x1Eu)
|
||||||
|
#else
|
||||||
|
#define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1Eu)
|
||||||
|
#endif /* LPTIM2 */
|
||||||
|
#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | 0x1Fu)
|
||||||
|
#if defined(UCPD1)
|
||||||
|
#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | 0x00u)
|
||||||
|
#else
|
||||||
|
#define EXTI_LINE_32 (EXTI_RESERVED | EXTI_REG2 | 0x00u)
|
||||||
|
#endif /* UCPD1 */
|
||||||
|
#if defined(UCPD2)
|
||||||
|
#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | 0x01u)
|
||||||
|
#else
|
||||||
|
#define EXTI_LINE_33 (EXTI_RESERVED | EXTI_REG2 | 0x01u)
|
||||||
|
#endif /* UCPD2 */
|
||||||
|
#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
|
||||||
|
#define EXTI_LINE_34 (EXTI_CONFIG | EXTI_REG2 | 0x02u)
|
||||||
|
#else
|
||||||
|
#define EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u)
|
||||||
|
#endif /* STM32G0C1xx || STM32G0B1xx */
|
||||||
|
#if defined(LPUART2)
|
||||||
|
#define EXTI_LINE_35 (EXTI_DIRECT | EXTI_REG2 | 0x03u)
|
||||||
|
#else
|
||||||
|
#define EXTI_LINE_35 (EXTI_RESERVED | EXTI_REG2 | 0x03u)
|
||||||
|
#endif /* LPUART2 */
|
||||||
|
#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
|
||||||
|
#define EXTI_LINE_36 (EXTI_DIRECT | EXTI_REG2 | 0x04u)
|
||||||
|
#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_Mode EXTI Mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define EXTI_MODE_NONE 0x00000000u
|
||||||
|
#define EXTI_MODE_INTERRUPT 0x00000001u
|
||||||
|
#define EXTI_MODE_EVENT 0x00000002u
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_Trigger EXTI Trigger
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define EXTI_TRIGGER_NONE 0x00000000u
|
||||||
|
#define EXTI_TRIGGER_RISING 0x00000001u
|
||||||
|
#define EXTI_TRIGGER_FALLING 0x00000002u
|
||||||
|
#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_GPIOSel EXTI GPIOSel
|
||||||
|
* @brief
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define EXTI_GPIOA 0x00000000u
|
||||||
|
#define EXTI_GPIOB 0x00000001u
|
||||||
|
#define EXTI_GPIOC 0x00000002u
|
||||||
|
#define EXTI_GPIOD 0x00000003u
|
||||||
|
#if defined(GPIOE)
|
||||||
|
#define EXTI_GPIOE 0x00000004u
|
||||||
|
#endif /* GPIOE */
|
||||||
|
#define EXTI_GPIOF 0x00000005u
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private constants --------------------------------------------------------*/
|
||||||
|
/** @defgroup EXTI_Private_Constants EXTI Private Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @brief EXTI Line property definition
|
||||||
|
*/
|
||||||
|
#define EXTI_PROPERTY_SHIFT 24u
|
||||||
|
#define EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT)
|
||||||
|
#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
|
||||||
|
#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
|
||||||
|
#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
|
||||||
|
#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief EXTI Register and bit usage
|
||||||
|
*/
|
||||||
|
#define EXTI_REG_SHIFT 16u
|
||||||
|
#define EXTI_REG1 (0x00uL << EXTI_REG_SHIFT)
|
||||||
|
#define EXTI_REG2 (0x01uL << EXTI_REG_SHIFT)
|
||||||
|
#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2)
|
||||||
|
#define EXTI_PIN_MASK 0x0000001Fu
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief EXTI Mask for interrupt & event mode
|
||||||
|
*/
|
||||||
|
#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief EXTI Mask for trigger possibilities
|
||||||
|
*/
|
||||||
|
#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief EXTI Line number
|
||||||
|
*/
|
||||||
|
#if defined(STM32G0C1xx) || defined(STM32G0B1xx)
|
||||||
|
#define EXTI_LINE_NB 37uL
|
||||||
|
#elif defined(STM32G0B0xx)
|
||||||
|
#define EXTI_LINE_NB 37uL
|
||||||
|
#elif defined(STM32G081xx) || defined(STM32G071xx)
|
||||||
|
#define EXTI_LINE_NB 34uL
|
||||||
|
#elif defined(STM32G070xx)
|
||||||
|
#define EXTI_LINE_NB 34uL
|
||||||
|
#elif defined(STM32G041xx) || defined(STM32G031xx)
|
||||||
|
#define EXTI_LINE_NB 32uL
|
||||||
|
#else
|
||||||
|
#define EXTI_LINE_NB 32uL
|
||||||
|
#endif /* STM32G0C1xx || STM32G0B1xx */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
/** @defgroup EXTI_Private_Macros EXTI Private Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \
|
||||||
|
((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
|
||||||
|
(((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
|
||||||
|
(((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
|
||||||
|
(((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \
|
||||||
|
(((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))))
|
||||||
|
|
||||||
|
#define IS_EXTI_MODE(__MODE__) ((((__MODE__) & EXTI_MODE_MASK) != 0x00u) && \
|
||||||
|
(((__MODE__) & ~EXTI_MODE_MASK) == 0x00u))
|
||||||
|
|
||||||
|
#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
|
||||||
|
|
||||||
|
#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) (((__EXTI_LINE__) == EXTI_TRIGGER_RISING) || \
|
||||||
|
((__EXTI_LINE__) == EXTI_TRIGGER_FALLING))
|
||||||
|
|
||||||
|
#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)
|
||||||
|
|
||||||
|
#if defined(GPIOE)
|
||||||
|
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
|
||||||
|
((__PORT__) == EXTI_GPIOB) || \
|
||||||
|
((__PORT__) == EXTI_GPIOC) || \
|
||||||
|
((__PORT__) == EXTI_GPIOD) || \
|
||||||
|
((__PORT__) == EXTI_GPIOE) || \
|
||||||
|
((__PORT__) == EXTI_GPIOF))
|
||||||
|
#else
|
||||||
|
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
|
||||||
|
((__PORT__) == EXTI_GPIOB) || \
|
||||||
|
((__PORT__) == EXTI_GPIOC) || \
|
||||||
|
((__PORT__) == EXTI_GPIOD) || \
|
||||||
|
((__PORT__) == EXTI_GPIOF))
|
||||||
|
#endif /* GPIOE */
|
||||||
|
|
||||||
|
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
|
||||||
|
* @brief EXTI Exported Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
|
||||||
|
* @brief Configuration functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Configuration functions ****************************************************/
|
||||||
|
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
|
||||||
|
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
|
||||||
|
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
|
||||||
|
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
|
||||||
|
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
|
||||||
|
* @brief IO operation functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* IO operation functions *****************************************************/
|
||||||
|
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
|
||||||
|
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
|
||||||
|
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
|
||||||
|
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* STM32G0xx_HAL_EXTI_H */
|
||||||
|
|
||||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user