diff --git a/.cproject b/.cproject
index 1b5f1a5..c46e7bd 100644
--- a/.cproject
+++ b/.cproject
@@ -21,7 +21,7 @@
@@ -99,7 +100,7 @@
diff --git a/.idea/runConfigurations/OCD_Boot.xml b/.idea/runConfigurations/OCD_Boot.xml
index 7f176db..fbac330 100644
--- a/.idea/runConfigurations/OCD_Boot.xml
+++ b/.idea/runConfigurations/OCD_Boot.xml
@@ -1,5 +1,5 @@
-
+
diff --git a/.idea/runConfigurations/OCD_mainprog.xml b/.idea/runConfigurations/OCD_mainprog.xml
index 7dc6755..b486e4d 100644
--- a/.idea/runConfigurations/OCD_mainprog.xml
+++ b/.idea/runConfigurations/OCD_mainprog.xml
@@ -1,5 +1,5 @@
-
+
diff --git a/App/app.c b/App/app.cpp
similarity index 89%
rename from App/app.c
rename to App/app.cpp
index 224ad84..61f06ab 100644
--- a/App/app.c
+++ b/App/app.cpp
@@ -29,9 +29,13 @@
/****************************************************************************************
* Include files
****************************************************************************************/
-#include "header.h" /* generic header */
+extern "C" {
+ #include "header.h" /* generic header */
+}
+#include "uart_bridge.hpp"
+UartBridge bridge(true, USART1, USART2, 9600, 9600);
/************************************************************************************//**
** \brief Initializes the user program application. Should be called once during
** software program initialization.
@@ -45,7 +49,10 @@ void AppInit(void)
/* Initialize the led driver. */
LedInit();
/* initialize the bootloader interface */
+ bridge.init();
+/*
BootComInit();
+*/
} /*** end of AppInit ***/
@@ -57,11 +64,13 @@ void AppInit(void)
****************************************************************************************/
void AppTask(void)
{
- /* Toggle LED with a fixed frequency. */
- LedToggle();
/* check for bootloader activation request */
+/*
BootComCheckActivationRequest();
+*/
} /*** end of AppTask ***/
/*********************************** end of app.c **************************************/
+
+//////////// FINALLY NEED TO UNCOMMENT BootComCheckActivationRequest and BootComInit for success firmwaare update from HOST
\ No newline at end of file
diff --git a/App/boot.c b/App/boot.c
index 6854dd6..590d2ff 100644
--- a/App/boot.c
+++ b/App/boot.c
@@ -115,7 +115,7 @@ static unsigned char Rs232ReceiveByte(unsigned char *data);
static void BootComRs232Init(void)
{
/* Configure UART peripheral. */
- rs232Handle.Instance = USART2;
+ rs232Handle.Instance = USART1;
rs232Handle.Init.BaudRate = BOOT_COM_RS232_BAUDRATE;
rs232Handle.Init.WordLength = UART_WORDLENGTH_8B;
rs232Handle.Init.StopBits = UART_STOPBITS_1;
diff --git a/Boot/App/blt_conf.h b/Boot/App/blt_conf.h
index 8cd73ed..b763798 100644
--- a/Boot/App/blt_conf.h
+++ b/Boot/App/blt_conf.h
@@ -67,7 +67,7 @@
/** \brief Enable/disable UART transport layer. */
#define BOOT_COM_RS232_ENABLE (1)
/** \brief Configure the desired communication speed. */
-#define BOOT_COM_RS232_BAUDRATE (57600)
+#define BOOT_COM_RS232_BAUDRATE (9600)
/** \brief Configure number of bytes in the target->host data packet. */
#define BOOT_COM_RS232_TX_MAX_DATA (129)
/** \brief Configure number of bytes in the host->target data packet. */
diff --git a/CMakeLists.txt b/CMakeLists.txt
index 0ea5528..9ed62e8 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -1,4 +1,26 @@
cmake_minimum_required(VERSION 3.23)
+set(CMAKE_SYSTEM_NAME Generic)
+set(CMAKE_SYSTEM_VERSION 1)
+set(CMAKE_C_COMPILER arm-none-eabi-gcc)
+set(CMAKE_CXX_STANDARD 17)
+set(CMAKE_CXX_COMPILER arm-none-eabi-g++)
+set(CMAKE_ASM_COMPILER arm-none-eabi-gcc)
+set(CMAKE_AR arm-none-eabi-ar)
+set(CMAKE_OBJCOPY arm-none-eabi-objcopy)
+set(CMAKE_OBJDUMP arm-none-eabi-objdump)
+set(SIZE arm-none-eabi-size)
+set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY)
+if (BOOT)
+ project(reader-boot C CXX ASM)
+else()
+ project(reader-main-prog C CXX ASM)
+endif()
+
+set(CORTEX-M 0)
+set(COMPILE_OPTIONS -mcpu=cortex-m${CORTEX-M} -mthumb -mthumb-interwork -ffunction-sections -fdata-sections -fno-common -fmessage-length=0 $<$:-fno-rtti>)
+set(LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/STM32G070CBTX_FLASH.ld)
+set(LINK_OPTIONS -Wl,-gc-sections,--print-memory-usage,-Map=${PROJECT_BINARY_DIR}/${PROJECT_NAME}.map -mcpu=cortex-m${CORTEX-M} -mthumb -mthumb-interwork -T ${LINKER_SCRIPT} -specs=nano.specs -specs=nosys.specs)
+
if(GTEST)
@@ -37,18 +59,7 @@ else()
endif()
math(EXPR LEN_ADDRESS "${FLASH_MAIN_ADDRESS} + ${LEN_OFFSET}" OUTPUT_FORMAT HEXADECIMAL)
add_compile_definitions("PAGE_SIZE=0x0800")
- set(CMAKE_SYSTEM_NAME Generic)
- set(CMAKE_SYSTEM_VERSION 1)
- set(CMAKE_C_COMPILER arm-none-eabi-gcc)
- set(CMAKE_CXX_COMPILER arm-none-eabi-g++)
- set(CMAKE_ASM_COMPILER arm-none-eabi-gcc)
- set(CMAKE_AR arm-none-eabi-ar)
- set(CMAKE_OBJCOPY arm-none-eabi-objcopy)
- set(CMAKE_OBJDUMP arm-none-eabi-objdump)
- set(SIZE arm-none-eabi-size)
- set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY)
- add_compile_options(-mcpu=cortex-m0 -mthumb -mthumb-interwork )
- add_compile_options(-ffunction-sections -fdata-sections -fno-common -fmessage-length=0)
+
#PAGE SIZE FOR F0 Series with 256KB Flash 0x0800 For 128Kb Flash 0x0400
# uncomment to mitigate c++17 absolute addresses warnings
@@ -85,9 +96,6 @@ else()
add_compile_definitions("BOOT_FLASH_VECTOR_TABLE_CS_OFFSET=${LEN_OFFSET}" "LEN_ADDRESS=${LEN_ADDRESS}")
add_definitions(-DDEBUG -DUSE_FULL_LL_DRIVER -DUSE_HAL_DRIVER -DSTM32G070xx)
- project(reader-boot C CXX ASM)
- add_compile_options(-mcpu=cortex-m0 -mthumb -mthumb-interwork)
- add_compile_options(-ffunction-sections -fdata-sections -fno-common -fmessage-length=0)
include_directories(Boot/Core/Inc Drivers/STM32G0xx_HAL_Driver/Inc Drivers/STM32G0xx_HAL_Driver/Inc/Legacy Drivers/CMSIS/Device/ST/STM32G0xx/Include Drivers/CMSIS/Include Boot/App)
include_directories(Boot/loader)
@@ -97,12 +105,9 @@ else()
list(FILTER SOURCES EXCLUDE REGEX "IAR\\/.*.[c|h]$")
list(FILTER SOURCES EXCLUDE REGEX "Keil\\/.*.[c|h]$")
set(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/Boot/STM32G070CBTX_FLASH.ld)
-
- add_link_options(-Wl,-gc-sections,--print-memory-usage,-Map=${PROJECT_BINARY_DIR}/${PROJECT_NAME}.map)
- add_link_options(-mcpu=cortex-m0 -mthumb -mthumb-interwork)
- add_link_options(-T ${LINKER_SCRIPT})
-
add_executable(${PROJECT_NAME}.elf ${SOURCES} )
+ target_compile_options(${PROJECT_NAME}.elf PUBLIC ${COMPILE_OPTIONS})
+ target_link_options(${PROJECT_NAME}.elf PUBLIC ${LINK_OPTIONS})
set(HEX_FILE ${PROJECT_BINARY_DIR}/${PROJECT_NAME}.hex)
set(BIN_FILE ${PROJECT_BINARY_DIR}/${PROJECT_NAME}.bin)
add_custom_command(TARGET ${PROJECT_NAME}.elf PRE_BUILD
@@ -116,7 +121,6 @@ else()
else()
- project(reader-main-prog C CXX ASM)
include_directories(Core/Inc Drivers/STM32G0xx_HAL_Driver/Inc Drivers/STM32G0xx_HAL_Driver/Inc/Legacy Drivers/CMSIS/Device/ST/STM32G0xx/Include Drivers/CMSIS/Include Core/Interfaces Core/Interfaces/Templates App)
@@ -127,12 +131,9 @@ else()
set(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/STM32G070CBTX_FLASH.ld)
-
- add_link_options(-Wl,-gc-sections,--print-memory-usage,-Map=${PROJECT_BINARY_DIR}/${PROJECT_NAME}.map)
- add_link_options(-mcpu=cortex-m0 -mthumb -mthumb-interwork )
- add_link_options(-T ${LINKER_SCRIPT})
-
add_executable(${PROJECT_NAME}.elf ${SOURCES} ${LINKER_SCRIPT})
+ target_compile_options(${PROJECT_NAME}.elf PUBLIC ${COMPILE_OPTIONS})
+ target_link_options(${PROJECT_NAME}.elf PUBLIC ${LINK_OPTIONS})
set(HEX_FILE ${PROJECT_BINARY_DIR}/${PROJECT_NAME}.hex)
set(BIN_FILE ${PROJECT_BINARY_DIR}/${PROJECT_NAME}.bin)
set(HEX_FILE_SRECORD_WITH_LEN_AND_CRC ${PROJECT_BINARY_DIR}/${PROJECT_NAME}_SRECORD.hex)
diff --git a/Core/Inc/circular_buffer.hpp b/Core/Inc/circular_buffer.hpp
new file mode 100644
index 0000000..3a4f06d
--- /dev/null
+++ b/Core/Inc/circular_buffer.hpp
@@ -0,0 +1,83 @@
+//===================================================================
+// File: circular_buffer.cpp
+//
+// Desc: A Circular Buffer implementation in C++.
+//
+// Copyright © 2019 Edwin Cloud. All rights reserved.
+//
+//===================================================================
+
+//-------------------------------------------------------------------
+// Includes
+//-------------------------------------------------------------------
+#include
+#include
+
+//-------------------------------------------------------------------
+// Circular_Buffer (Class)
+// We will implement the buffer with a templated class so
+// the buffer can be a buffer of specified type.
+//-------------------------------------------------------------------
+template class Circular_Buffer {
+private:
+ //---------------------------------------------------------------
+ // Circular_Buffer - Private Member Variables
+ //---------------------------------------------------------------
+
+ std::unique_ptr buffer; // using a smart pointer is safer (and we don't
+ // have to implement a destructor)
+ size_t head = 0; // size_t is an unsigned long
+ size_t tail = 0;
+ size_t max_size;
+ T empty_item; // we will use this to clear data
+public:
+ //---------------------------------------------------------------
+ // Circular_Buffer - Public Methods
+ //---------------------------------------------------------------
+
+ // Create a new Circular_Buffer.
+ Circular_Buffer(size_t max_size)
+ : buffer(std::unique_ptr(new T[max_size])), max_size(max_size){};
+
+ // Add an item to this circular buffer.
+ void enqueue(T item) {
+
+ // insert item at back of buffer
+ buffer[tail] = item;
+
+ // increment tail
+ tail = (tail + 1) % max_size;
+ }
+
+ // Remove an item from this circular buffer and return it.
+ T dequeue() {
+
+ T item = buffer[head];
+
+ // set item at head to be empty
+ T empty;
+ buffer[head] = empty_item;
+
+ // move head foward
+ head = (head + 1) % max_size;
+
+ // return item
+ return item;
+ }
+
+ // Return the item at the front of this circular buffer.
+ T front() { return buffer[head]; }
+
+ // Return true if this circular buffer is empty, and false otherwise.
+ bool is_empty() { return head == tail; }
+
+ // Return true if this circular buffer is full, and false otherwise.
+ bool is_full() { return tail == (head - 1) % max_size; }
+
+ // Return the size of this circular buffer.
+ size_t size() {
+ if (tail >= head)
+ return tail - head;
+ return max_size - head - tail;
+ }
+};
\ No newline at end of file
diff --git a/Core/Inc/main.h b/Core/Inc/main.h
index 6fbc937..2c6f3ec 100644
--- a/Core/Inc/main.h
+++ b/Core/Inc/main.h
@@ -58,7 +58,13 @@ void Error_Handler(void);
/* USER CODE END EFP */
/* Private defines -----------------------------------------------------------*/
-void MX_USART2_UART_Init(void);
+#define LIGHTING_EN_Pin GPIO_PIN_4
+#define LIGHTING_EN_GPIO_Port GPIOA
+#define READER_EN_Pin GPIO_PIN_5
+#define READER_EN_GPIO_Port GPIOA
+#define ZUMMER_PINOUT_Pin GPIO_PIN_5
+#define ZUMMER_PINOUT_GPIO_Port GPIOB
+
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
@@ -68,5 +74,3 @@ void MX_USART2_UART_Init(void);
#endif
#endif /* __MAIN_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Core/Inc/stm32g0xx_hal_conf.h b/Core/Inc/stm32g0xx_hal_conf.h
index 0fdd915..8e3b1d7 100644
--- a/Core/Inc/stm32g0xx_hal_conf.h
+++ b/Core/Inc/stm32g0xx_hal_conf.h
@@ -1,3 +1,4 @@
+/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32g0xx_hal_conf.h
@@ -6,16 +7,16 @@
******************************************************************************
* @attention
*
- * © Copyright (c) 2018 STMicroelectronics.
- * All rights reserved. *uart1Buf;
+ Circular_Buffer *uart2Buf;
+ bool isTurnOn() const;
+ void setIsTurnOn(bool isTurnOn);
+ static volatile uint8_t dataFromUart1;
+ static volatile uint8_t dataFromUart2;
+ void init(void);
+private:
+
+protected:
+ void uartInit(UART_HandleTypeDef* huart);
+ bool turnOn;
+ static UART_HandleTypeDef uart1Handle, uart2Handle;
+public:
+ UART_HandleTypeDef* getHuart1() ;
+
+ UART_HandleTypeDef* getHuart2() ;
+
+protected:
+ USART_TypeDef *uart1, *uart2;
+
+};
+
+#endif //READER_MAIN_PROG_UART_BRIDGE_HPP
diff --git a/Core/Src/circular_buffer.cpp b/Core/Src/circular_buffer.cpp
new file mode 100644
index 0000000..e69de29
diff --git a/Core/Src/main.c b/Core/Src/main.c
deleted file mode 100644
index dba43bd..0000000
--- a/Core/Src/main.c
+++ /dev/null
@@ -1,284 +0,0 @@
-/* USER CODE BEGIN Header */
-/**
- ******************************************************************************
- * @file : main.c
- * @brief : Main program body
- ******************************************************************************
- * @attention
- *
- * © Copyright (c) 2020 STMicroelectronics.
- * All rights reserved. © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved. (1024);
+ UartBridge::uart2Buf = new Circular_Buffer(1024);
+ uart1Handle.Instance = uart1;
+ uart1Handle.Init.BaudRate = baudRate1;
+ uart1Handle.Init.WordLength = UART_WORDLENGTH_8B;
+ uart1Handle.Init.StopBits = UART_STOPBITS_1;
+ uart1Handle.Init.Parity = UART_PARITY_NONE;
+ uart1Handle.Init.Mode = UART_MODE_TX_RX;
+ uart1Handle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+ uart1Handle.Init.OverSampling = UART_OVERSAMPLING_16;
+ uart1Handle.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+ uart1Handle.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+ uart1Handle.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+ uart2Handle = uart1Handle;
+ uart2Handle.Instance = uart2;
+ uart2Handle.Init.BaudRate = baudRate2;
+}
+
+bool UartBridge::isTurnOn() const {
+ return turnOn;
+}
+
+void UartBridge::setIsTurnOn(bool isTurnOn) {
+ UartBridge::turnOn = isTurnOn;
+}
+
+void UartBridge::uartInit(UART_HandleTypeDef *huart) {
+ if (HAL_UART_Init(huart) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ if (HAL_UARTEx_SetTxFifoThreshold(huart, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ if (HAL_UARTEx_SetRxFifoThreshold(huart, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+ {
+ Error_Handler();
+ }
+ if (HAL_UARTEx_DisableFifoMode(huart) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+}
+
+UART_HandleTypeDef* UartBridge::getHuart1() {
+ return &uart1Handle;
+}
+
+UART_HandleTypeDef* UartBridge::getHuart2() {
+ return &uart2Handle;
+}
+
+void UartBridge::init(void) {
+ uartInit(&uart1Handle);
+ uartInit(&uart2Handle);
+ HAL_UART_Receive_IT(&uart1Handle, (uint8_t*)&dataFromUart1, 1);
+ HAL_UART_Receive_IT(&uart2Handle, (uint8_t*)&dataFromUart2, 1);
+}
+
+
+
+extern "C" void USART1_IRQHandler(void)
+{
+ /* USER CODE BEGIN USART1_IRQn 0 */
+
+ /* USER CODE END USART1_IRQn 0 */
+ HAL_UART_IRQHandler(bridgePnt->getHuart1());
+ /* USER CODE BEGIN USART1_IRQn 1 */
+
+ /* USER CODE END USART1_IRQn 1 */
+}
+
+/**
+ * @brief This function handles USART2 global interrupt / USART2 wake-up interrupt through EXTI line 26.
+ */
+void USART2_IRQHandler(void)
+{
+ /* USER CODE BEGIN USART2_IRQn 0 */
+
+ /* USER CODE END USART2_IRQn 0 */
+ HAL_UART_IRQHandler(bridgePnt->getHuart2());
+ /* USER CODE BEGIN USART2_IRQn 1 */
+
+ /* USER CODE END USART2_IRQn 1 */
+}
diff --git a/STM32G070CBTX_FLASH.ld b/STM32G070CBTX_FLASH.ld
index 6431f93..9ad0170 100644
--- a/STM32G070CBTX_FLASH.ld
+++ b/STM32G070CBTX_FLASH.ld
@@ -39,8 +39,8 @@ INCLUDE memory_map.inc
/* Highest address of the user mode stack */
_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
-_Min_Heap_Size = 0x200; /* required amount of heap */
-_Min_Stack_Size = 0x400; /* required amount of stack */
+_Min_Heap_Size = 0x1000; /* required amount of heap */
+_Min_Stack_Size = 0x1000; /* required amount of stack */
/* Memories definition */
MEMORY
diff --git a/gm60.ioc b/gm60.ioc
index ef5731d..a0eb183 100644
--- a/gm60.ioc
+++ b/gm60.ioc
@@ -67,6 +67,8 @@ PA2.Mode=Asynchronous
PA2.Signal=USART2_TX
PA3.Mode=Asynchronous
PA3.Signal=USART2_RX
+PA4.GPIOParameters=GPIO_Label
+PA4.GPIO_Label=LIGHTING_EN
PA4.Locked=true
PA4.Signal=GPIO_Output
PA5.GPIOParameters=GPIO_Label
diff --git a/stm32g070.svd b/stm32g070.svd
new file mode 100644
index 0000000..9f4995e
--- /dev/null
+++ b/stm32g070.svd
@@ -0,0 +1,21537 @@
+
+ STM32G070
+ 1.4
+ STM32G070
+
+ CM0
+ r0p1
+ little
+ true
+ false
+ 2
+ false
+
+ 8
+ 32
+ 0x20
+ 0x0
+ 0xFFFFFFFF
+
+
+ IWDG
+ Independent watchdog
+ IWDG
+ 0x40003000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ KR
+ KR
+ Key register
+ 0x0
+ 0x20
+ write-only
+ 0x00000000
+
+
+ KEY
+ Key value (write only, read
+ 0x0000)
+ 0
+ 16
+
+
+
+
+ PR
+ PR
+ Prescaler register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PR
+ Prescaler divider
+ 0
+ 3
+
+
+
+
+ RLR
+ RLR
+ Reload register
+ 0x8
+ 0x20
+ read-write
+ 0x00000FFF
+
+
+ RL
+ Watchdog counter reload
+ value
+ 0
+ 12
+
+
+
+
+ SR
+ SR
+ Status register
+ 0xC
+ 0x20
+ read-only
+ 0x00000000
+
+
+ WVU
+ Watchdog counter window value
+ update
+ 2
+ 1
+
+
+ RVU
+ Watchdog counter reload value
+ update
+ 1
+ 1
+
+
+ PVU
+ Watchdog prescaler value
+ update
+ 0
+ 1
+
+
+
+
+ WINR
+ WINR
+ Window register
+ 0x10
+ 0x20
+ read-write
+ 0x00000FFF
+
+
+ WIN
+ Watchdog counter window
+ value
+ 0
+ 12
+
+
+
+
+ HWCFGR
+ HWCFGR
+ hardware configuration
+ register
+ 0x3F0
+ 0x20
+ read-write
+ 0x00000071
+
+
+ WINDOW
+ Support of Window function
+ 0
+ 4
+
+
+ PR_DEFAULT
+ Prescaler default value
+ 4
+ 4
+
+
+
+
+ VERR
+ VERR
+ EXTI IP Version register
+ 0x3F4
+ 0x20
+ read-only
+ 0x00000023
+
+
+ MINREV
+ Minor Revision number
+ 0
+ 4
+
+
+ MAJREV
+ Major Revision number
+ 4
+ 4
+
+
+
+
+ IPIDR
+ IPIDR
+ EXTI Identification register
+ 0x3F8
+ 0x20
+ read-only
+ 0x00120041
+
+
+ IPID
+ IP Identification
+ 0
+ 32
+
+
+
+
+ SIDR
+ SIDR
+ EXTI Size ID register
+ 0x3FC
+ 0x20
+ read-only
+ 0xA3C5DD01
+
+
+ SID
+ Size Identification
+ 0
+ 32
+
+
+
+
+
+
+ WWDG
+ System window watchdog
+ WWDG
+ 0x40002C00
+
+ 0x0
+ 0x400
+ registers
+
+
+ WWDG
+ Window watchdog interrupt
+ 0
+
+
+
+ CR
+ CR
+ Control register
+ 0x0
+ 0x20
+ read-write
+ 0x0000007F
+
+
+ WDGA
+ Activation bit
+ 7
+ 1
+
+
+ T
+ 7-bit counter (MSB to LSB)
+ 0
+ 7
+
+
+
+
+ CFR
+ CFR
+ Configuration register
+ 0x4
+ 0x20
+ read-write
+ 0x0000007F
+
+
+ WDGTB
+ Timer base
+ 11
+ 3
+
+
+ EWI
+ Early wakeup interrupt
+ 9
+ 1
+
+
+ W
+ 7-bit window value
+ 0
+ 7
+
+
+
+
+ SR
+ SR
+ Status register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EWIF
+ Early wakeup interrupt
+ flag
+ 0
+ 1
+
+
+
+
+
+
+ FLASH
+ Flash
+ Flash
+ 0x40022000
+
+ 0x0
+ 0x400
+ registers
+
+
+ FLASH
+ Flash global interrupt
+ 3
+
+
+
+ ACR
+ ACR
+ Access control register
+ 0x0
+ 0x20
+ read-write
+ 0x00000600
+
+
+ LATENCY
+ Latency
+ 0
+ 3
+
+
+ PRFTEN
+ Prefetch enable
+ 8
+ 1
+
+
+ ICEN
+ Instruction cache enable
+ 9
+ 1
+
+
+ ICRST
+ Instruction cache reset
+ 11
+ 1
+
+
+ EMPTY
+ Flash User area empty
+ 16
+ 1
+
+
+ DBG_SWEN
+ Debug access software
+ enable
+ 18
+ 1
+
+
+
+
+ KEYR
+ KEYR
+ Flash key register
+ 0x8
+ 0x20
+ write-only
+ 0x00000000
+
+
+ KEYR
+ KEYR
+ 0
+ 32
+
+
+
+
+ OPTKEYR
+ OPTKEYR
+ Option byte key register
+ 0xC
+ 0x20
+ write-only
+ 0x00000000
+
+
+ OPTKEYR
+ Option byte key
+ 0
+ 32
+
+
+
+
+ SR
+ SR
+ Status register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EOP
+ End of operation
+ 0
+ 1
+
+
+ OPERR
+ Operation error
+ 1
+ 1
+
+
+ PROGERR
+ Programming error
+ 3
+ 1
+
+
+ WRPERR
+ Write protected error
+ 4
+ 1
+
+
+ PGAERR
+ Programming alignment
+ error
+ 5
+ 1
+
+
+ SIZERR
+ Size error
+ 6
+ 1
+
+
+ PGSERR
+ Programming sequence error
+ 7
+ 1
+
+
+ MISERR
+ Fast programming data miss
+ error
+ 8
+ 1
+
+
+ FASTERR
+ Fast programming error
+ 9
+ 1
+
+
+ RDERR
+ PCROP read error
+ 14
+ 1
+
+
+ OPTVERR
+ Option and Engineering bits loading
+ validity error
+ 15
+ 1
+
+
+ BSY
+ Busy
+ 16
+ 1
+
+
+ CFGBSY
+ Programming or erase configuration
+ busy.
+ 18
+ 1
+
+
+
+
+ CR
+ CR
+ Flash control register
+ 0x14
+ 0x20
+ read-write
+ 0xC0000000
+
+
+ PG
+ Programming
+ 0
+ 1
+
+
+ PER
+ Page erase
+ 1
+ 1
+
+
+ MER
+ Mass erase
+ 2
+ 1
+
+
+ PNB
+ Page number
+ 3
+ 6
+
+
+ STRT
+ Start
+ 16
+ 1
+
+
+ OPTSTRT
+ Options modification start
+ 17
+ 1
+
+
+ FSTPG
+ Fast programming
+ 18
+ 1
+
+
+ EOPIE
+ End of operation interrupt
+ enable
+ 24
+ 1
+
+
+ ERRIE
+ Error interrupt enable
+ 25
+ 1
+
+
+ RDERRIE
+ PCROP read error interrupt
+ enable
+ 26
+ 1
+
+
+ OBL_LAUNCH
+ Force the option byte
+ loading
+ 27
+ 1
+
+
+ SEC_PROT
+ Securable memory area protection
+ enable
+ 28
+ 1
+
+
+ OPTLOCK
+ Options Lock
+ 30
+ 1
+
+
+ LOCK
+ FLASH_CR Lock
+ 31
+ 1
+
+
+
+
+ ECCR
+ ECCR
+ Flash ECC register
+ 0x18
+ 0x20
+ 0x00000000
+
+
+ ADDR_ECC
+ ECC fail address
+ 0
+ 14
+ read-only
+
+
+ SYSF_ECC
+ ECC fail for Corrected ECC Error or
+ Double ECC Error in info block
+ 20
+ 1
+ read-only
+
+
+ ECCIE
+ ECC correction interrupt
+ enable
+ 24
+ 1
+ read-write
+
+
+ ECCC
+ ECC correction
+ 30
+ 1
+ read-write
+
+
+ ECCD
+ ECC detection
+ 31
+ 1
+ read-write
+
+
+
+
+ OPTR
+ OPTR
+ Flash option register
+ 0x20
+ 0x20
+ read-write
+ 0xF0000000
+
+
+ RDP
+ Read protection level
+ 0
+ 8
+
+
+ BOREN
+ BOR reset Level
+ 8
+ 1
+
+
+ BORF_LEV
+ These bits contain the VDD supply level
+ threshold that activates the reset
+ 9
+ 2
+
+
+ BORR_LEV
+ These bits contain the VDD supply level
+ threshold that releases the reset.
+ 11
+ 2
+
+
+ nRST_STOP
+ nRST_STOP
+ 13
+ 1
+
+
+ nRST_STDBY
+ nRST_STDBY
+ 14
+ 1
+
+
+ nRSTS_HDW
+ nRSTS_HDW
+ 15
+ 1
+
+
+ IDWG_SW
+ Independent watchdog
+ selection
+ 16
+ 1
+
+
+ IWDG_STOP
+ Independent watchdog counter freeze in
+ Stop mode
+ 17
+ 1
+
+
+ IWDG_STDBY
+ Independent watchdog counter freeze in
+ Standby mode
+ 18
+ 1
+
+
+ WWDG_SW
+ Window watchdog selection
+ 19
+ 1
+
+
+ RAM_PARITY_CHECK
+ SRAM parity check control
+ 22
+ 1
+
+
+ nBOOT_SEL
+ nBOOT_SEL
+ 24
+ 1
+
+
+ nBOOT1
+ Boot configuration
+ 25
+ 1
+
+
+ nBOOT0
+ nBOOT0 option bit
+ 26
+ 1
+
+
+ NRST_MODE
+ NRST_MODE
+ 27
+ 2
+
+
+ IRHEN
+ Internal reset holder enable
+ bit
+ 29
+ 1
+
+
+
+
+ PCROP1ASR
+ PCROP1ASR
+ Flash PCROP zone A Start address
+ register
+ 0x24
+ 0x20
+ read-only
+ 0xF0000000
+
+
+ PCROP1A_STRT
+ PCROP1A area start offset
+ 0
+ 8
+
+
+
+
+ PCROP1AER
+ PCROP1AER
+ Flash PCROP zone A End address
+ register
+ 0x28
+ 0x20
+ read-only
+ 0xF0000000
+
+
+ PCROP1A_END
+ PCROP1A area end offset
+ 0
+ 8
+
+
+ PCROP_RDP
+ PCROP area preserved when RDP level
+ decreased
+ 31
+ 1
+
+
+
+
+ WRP1AR
+ WRP1AR
+ Flash WRP area A address
+ register
+ 0x2C
+ 0x20
+ read-only
+ 0xF0000000
+
+
+ WRP1A_STRT
+ WRP area A start offset
+ 0
+ 6
+
+
+ WRP1A_END
+ WRP area A end offset
+ 16
+ 6
+
+
+
+
+ WRP1BR
+ WRP1BR
+ Flash WRP area B address
+ register
+ 0x30
+ 0x20
+ read-only
+ 0xF0000000
+
+
+ WRP1B_STRT
+ WRP area B start offset
+ 0
+ 6
+
+
+ WRP1B_END
+ WRP area B end offset
+ 16
+ 6
+
+
+
+
+ PCROP1BSR
+ PCROP1BSR
+ Flash PCROP zone B Start address
+ register
+ 0x34
+ 0x20
+ read-only
+ 0xF0000000
+
+
+ PCROP1B_STRT
+ PCROP1B area start offset
+ 0
+ 8
+
+
+
+
+ PCROP1BER
+ PCROP1BER
+ Flash PCROP zone B End address
+ register
+ 0x38
+ 0x20
+ read-only
+ 0xF0000000
+
+
+ PCROP1B_END
+ PCROP1B area end offset
+ 0
+ 8
+
+
+
+
+ SECR
+ SECR
+ Flash Security register
+ 0x80
+ 0x20
+ read-only
+ 0xF0000000
+
+
+ SEC_SIZE
+ Securable memory area size
+ 0
+ 7
+
+
+ BOOT_LOCK
+ used to force boot from user
+ area
+ 16
+ 1
+
+
+
+
+
+
+ DBG
+ Debug support
+ DBG
+ 0x40015800
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ IDCODE
+ IDCODE
+ MCU Device ID Code Register
+ 0x0
+ 0x20
+ read-only
+ 0x0
+
+
+ DEV_ID
+ Device Identifier
+ 0
+ 16
+
+
+ REV_ID
+ Revision Identifier
+ 16
+ 16
+
+
+
+
+ CR
+ CR
+ Debug MCU Configuration
+ Register
+ 0x4
+ 0x20
+ read-write
+ 0x0
+
+
+ DBG_STOP
+ Debug Stop Mode
+ 1
+ 1
+
+
+ DBG_STANDBY
+ Debug Standby Mode
+ 2
+ 1
+
+
+
+
+ APB_FZ1
+ APB_FZ1
+ DBG APB freeze register 1
+ 0x8
+ 0x20
+ read-write
+ 0x0
+
+
+ DBG_TIMER2_STOP
+ Debug Timer 2 stopped when Core is
+ halted
+ 0
+ 1
+
+
+ DBG_TIM3_STOP
+ TIM3 counter stopped when core is
+ halted
+ 1
+ 1
+
+
+ DBG_TIMER6_STOP
+ Debug Timer 6 stopped when Core is
+ halted
+ 4
+ 1
+
+
+ DBG_TIM7_STOP
+ TIM7 counter stopped when core is
+ halted
+ 5
+ 1
+
+
+ DBG_RTC_STOP
+ Debug RTC stopped when Core is
+ halted
+ 10
+ 1
+
+
+ DBG_WWDG_STOP
+ Debug Window Wachdog stopped when Core
+ is halted
+ 11
+ 1
+
+
+ DBG_IWDG_STOP
+ Debug Independent Wachdog stopped when
+ Core is halted
+ 12
+ 1
+
+
+ DBG_I2C1_STOP
+ I2C1 SMBUS timeout mode stopped when
+ core is halted
+ 21
+ 1
+
+
+ DBG_LPTIM2_STOP
+ Clocking of LPTIMER2 counter when the
+ core is halted
+ 30
+ 1
+
+
+ DBG_LPTIM1_STOP
+ Clocking of LPTIMER1 counter when the
+ core is halted
+ 31
+ 1
+
+
+
+
+ APB_FZ2
+ APB_FZ2
+ DBG APB freeze register 2
+ 0xC
+ 0x20
+ read-write
+ 0x0
+
+
+ DBG_TIM1_STOP
+ DBG_TIM1_STOP
+ 11
+ 1
+
+
+ DBG_TIM14_STOP
+ DBG_TIM14_STOP
+ 15
+ 1
+
+
+ DBG_TIM15_STOP
+ DBG_TIM15_STOP
+ 16
+ 1
+
+
+ DBG_TIM16_STOP
+ DBG_TIM16_STOP
+ 17
+ 1
+
+
+ DBG_TIM17_STOP
+ DBG_TIM17_STOP
+ 18
+ 1
+
+
+
+
+
+
+ RCC
+ Reset and clock control
+ RCC
+ 0x40021000
+
+ 0x0
+ 0x400
+ registers
+
+
+ RCC
+ RCC global interrupt
+ 4
+
+
+
+ CR
+ CR
+ Clock control register
+ 0x0
+ 0x20
+ read-write
+ 0x00000063
+
+
+ HSION
+ HSI16 clock enable
+ 8
+ 1
+
+
+ HSIKERON
+ HSI16 always enable for peripheral
+ kernels
+ 9
+ 1
+
+
+ HSIRDY
+ HSI16 clock ready flag
+ 10
+ 1
+
+
+ HSIDIV
+ HSI16 clock division
+ factor
+ 11
+ 3
+
+
+ HSEON
+ HSE clock enable
+ 16
+ 1
+
+
+ HSERDY
+ HSE clock ready flag
+ 17
+ 1
+
+
+ HSEBYP
+ HSE crystal oscillator
+ bypass
+ 18
+ 1
+
+
+ CSSON
+ Clock security system
+ enable
+ 19
+ 1
+
+
+ PLLON
+ PLL enable
+ 24
+ 1
+
+
+ PLLRDY
+ PLL clock ready flag
+ 25
+ 1
+
+
+
+
+ ICSCR
+ ICSCR
+ Internal clock sources calibration
+ register
+ 0x4
+ 0x20
+ 0x10000000
+
+
+ HSICAL
+ HSI16 clock calibration
+ 0
+ 8
+ read-only
+
+
+ HSITRIM
+ HSI16 clock trimming
+ 8
+ 7
+ read-write
+
+
+
+
+ CFGR
+ CFGR
+ Clock configuration register
+ 0x8
+ 0x20
+ 0x00000000
+
+
+ MCOPRE
+ Microcontroller clock output
+ prescaler
+ 28
+ 3
+ read-only
+
+
+ MCOSEL
+ Microcontroller clock
+ output
+ 24
+ 3
+ read-write
+
+
+ PPRE
+ APB prescaler
+ 12
+ 3
+ read-write
+
+
+ HPRE
+ AHB prescaler
+ 8
+ 4
+ read-write
+
+
+ SWS
+ System clock switch status
+ 3
+ 3
+ read-only
+
+
+ SW
+ System clock switch
+ 0
+ 3
+ read-write
+
+
+
+
+ PLLSYSCFGR
+ PLLSYSCFGR
+ PLL configuration register
+ 0xC
+ 0x20
+ read-write
+ 0x00001000
+
+
+ PLLSRC
+ PLL input clock source
+ 0
+ 2
+
+
+ PLLM
+ Division factor M of the PLL input clock
+ divider
+ 4
+ 3
+
+
+ PLLN
+ PLL frequency multiplication factor
+ N
+ 8
+ 7
+
+
+ PLLPEN
+ PLLPCLK clock output
+ enable
+ 16
+ 1
+
+
+ PLLP
+ PLL VCO division factor P for PLLPCLK
+ clock output
+ 17
+ 5
+
+
+ PLLQEN
+ PLLQCLK clock output
+ enable
+ 24
+ 1
+
+
+ PLLQ
+ PLL VCO division factor Q for PLLQCLK
+ clock output
+ 25
+ 3
+
+
+ PLLREN
+ PLLRCLK clock output
+ enable
+ 28
+ 1
+
+
+ PLLR
+ PLL VCO division factor R for PLLRCLK
+ clock output
+ 29
+ 3
+
+
+
+
+ CIER
+ CIER
+ Clock interrupt enable
+ register
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LSIRDYIE
+ LSI ready interrupt enable
+ 0
+ 1
+
+
+ LSERDYIE
+ LSE ready interrupt enable
+ 1
+ 1
+
+
+ HSIRDYIE
+ HSI ready interrupt enable
+ 3
+ 1
+
+
+ HSERDYIE
+ HSE ready interrupt enable
+ 4
+ 1
+
+
+ PLLSYSRDYIE
+ PLL ready interrupt enable
+ 5
+ 1
+
+
+
+
+ CIFR
+ CIFR
+ Clock interrupt flag register
+ 0x1C
+ 0x20
+ read-only
+ 0x00000000
+
+
+ LSIRDYF
+ LSI ready interrupt flag
+ 0
+ 1
+
+
+ LSERDYF
+ LSE ready interrupt flag
+ 1
+ 1
+
+
+ HSIRDYF
+ HSI ready interrupt flag
+ 3
+ 1
+
+
+ HSERDYF
+ HSE ready interrupt flag
+ 4
+ 1
+
+
+ PLLSYSRDYF
+ PLL ready interrupt flag
+ 5
+ 1
+
+
+ CSSF
+ Clock security system interrupt
+ flag
+ 8
+ 1
+
+
+ LSECSSF
+ LSE Clock security system interrupt
+ flag
+ 9
+ 1
+
+
+
+
+ CICR
+ CICR
+ Clock interrupt clear register
+ 0x20
+ 0x20
+ write-only
+ 0x00000000
+
+
+ LSIRDYC
+ LSI ready interrupt clear
+ 0
+ 1
+
+
+ LSERDYC
+ LSE ready interrupt clear
+ 1
+ 1
+
+
+ HSIRDYC
+ HSI ready interrupt clear
+ 3
+ 1
+
+
+ HSERDYC
+ HSE ready interrupt clear
+ 4
+ 1
+
+
+ PLLSYSRDYC
+ PLL ready interrupt clear
+ 5
+ 1
+
+
+ CSSC
+ Clock security system interrupt
+ clear
+ 8
+ 1
+
+
+ LSECSSC
+ LSE Clock security system interrupt
+ clear
+ 9
+ 1
+
+
+
+
+ AHBRSTR
+ AHBRSTR
+ AHB peripheral reset register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DMARST
+ DMA1 reset
+ 0
+ 1
+
+
+ FLASHRST
+ FLITF reset
+ 8
+ 1
+
+
+ CRCRST
+ CRC reset
+ 12
+ 1
+
+
+
+
+ IOPRSTR
+ IOPRSTR
+ GPIO reset register
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IOPARST
+ I/O port A reset
+ 0
+ 1
+
+
+ IOPBRST
+ I/O port B reset
+ 1
+ 1
+
+
+ IOPCRST
+ I/O port C reset
+ 2
+ 1
+
+
+ IOPDRST
+ I/O port D reset
+ 3
+ 1
+
+
+ IOPFRST
+ I/O port F reset
+ 5
+ 1
+
+
+
+
+ APBRSTR1
+ APBRSTR1
+ APB peripheral reset register
+ 1
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TIM3RST
+ TIM3 timer reset
+ 1
+ 1
+
+
+ TIM6RST
+ TIM6 timer reset
+ 4
+ 1
+
+
+ TIM7RST
+ TIM7 timer reset
+ 5
+ 1
+
+
+ SPI2RST
+ SPI2 reset
+ 14
+ 1
+
+
+ USART2RST
+ USART2 reset
+ 17
+ 1
+
+
+ USART3RST
+ USART3 reset
+ 18
+ 1
+
+
+ USART4RST
+ USART4 reset
+ 19
+ 1
+
+
+ I2C1RST
+ I2C1 reset
+ 21
+ 1
+
+
+ I2C2RST
+ I2C2 reset
+ 22
+ 1
+
+
+ DBGRST
+ Debug support reset
+ 27
+ 1
+
+
+ PWRRST
+ Power interface reset
+ 28
+ 1
+
+
+
+
+ APBRSTR2
+ APBRSTR2
+ APB peripheral reset register
+ 2
+ 0x30
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SYSCFGRST
+ SYSCFG, COMP and VREFBUF
+ reset
+ 0
+ 1
+
+
+ TIM1RST
+ TIM1 timer reset
+ 11
+ 1
+
+
+ SPI1RST
+ SPI1 reset
+ 12
+ 1
+
+
+ USART1RST
+ USART1 reset
+ 14
+ 1
+
+
+ TIM14RST
+ TIM14 timer reset
+ 15
+ 1
+
+
+ TIM15RST
+ TIM15 timer reset
+ 16
+ 1
+
+
+ TIM16RST
+ TIM16 timer reset
+ 17
+ 1
+
+
+ TIM17RST
+ TIM17 timer reset
+ 18
+ 1
+
+
+ ADCRST
+ ADC reset
+ 20
+ 1
+
+
+
+
+ IOPENR
+ IOPENR
+ GPIO clock enable register
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IOPAEN
+ I/O port A clock enable
+ 0
+ 1
+
+
+ IOPBEN
+ I/O port B clock enable
+ 1
+ 1
+
+
+ IOPCEN
+ I/O port C clock enable
+ 2
+ 1
+
+
+ IOPDEN
+ I/O port D clock enable
+ 3
+ 1
+
+
+ IOPFEN
+ I/O port F clock enable
+ 5
+ 1
+
+
+
+
+ AHBENR
+ AHBENR
+ AHB peripheral clock enable
+ register
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DMAEN
+ DMA clock enable
+ 0
+ 1
+
+
+ FLASHEN
+ Flash memory interface clock
+ enable
+ 8
+ 1
+
+
+ CRCEN
+ CRC clock enable
+ 12
+ 1
+
+
+
+
+ APBENR1
+ APBENR1
+ APB peripheral clock enable register
+ 1
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TIM3EN
+ TIM3 timer clock enable
+ 1
+ 1
+
+
+ TIM6EN
+ TIM6 timer clock enable
+ 4
+ 1
+
+
+ TIM7EN
+ TIM7 timer clock enable
+ 5
+ 1
+
+
+ RTCAPBEN
+ RTC APB clock enable
+ 10
+ 1
+
+
+ WWDGEN
+ WWDG clock enable
+ 11
+ 1
+
+
+ SPI2EN
+ SPI2 clock enable
+ 14
+ 1
+
+
+ USART2EN
+ USART2 clock enable
+ 17
+ 1
+
+
+ USART3EN
+ USART3 clock enable
+ 18
+ 1
+
+
+ USART4EN
+ USART4 clock enable
+ 19
+ 1
+
+
+ I2C1EN
+ I2C1 clock enable
+ 21
+ 1
+
+
+ I2C2EN
+ I2C2 clock enable
+ 22
+ 1
+
+
+ DBGEN
+ Debug support clock enable
+ 27
+ 1
+
+
+ PWREN
+ Power interface clock
+ enable
+ 28
+ 1
+
+
+
+
+ APBENR2
+ APBENR2
+ APB peripheral clock enable register
+ 2
+ 0x40
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SYSCFGEN
+ SYSCFG, COMP and VREFBUF clock
+ enable
+ 0
+ 1
+
+
+ TIM1EN
+ TIM1 timer clock enable
+ 11
+ 1
+
+
+ SPI1EN
+ SPI1 clock enable
+ 12
+ 1
+
+
+ USART1EN
+ USART1 clock enable
+ 14
+ 1
+
+
+ TIM14EN
+ TIM14 timer clock enable
+ 15
+ 1
+
+
+ TIM15EN
+ TIM15 timer clock enable
+ 16
+ 1
+
+
+ TIM16EN
+ TIM16 timer clock enable
+ 17
+ 1
+
+
+ TIM17EN
+ TIM16 timer clock enable
+ 18
+ 1
+
+
+ ADCEN
+ ADC clock enable
+ 20
+ 1
+
+
+
+
+ IOPSMENR
+ IOPSMENR
+ GPIO in Sleep mode clock enable
+ register
+ 0x44
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IOPASMEN
+ I/O port A clock enable during Sleep
+ mode
+ 0
+ 1
+
+
+ IOPBSMEN
+ I/O port B clock enable during Sleep
+ mode
+ 1
+ 1
+
+
+ IOPCSMEN
+ I/O port C clock enable during Sleep
+ mode
+ 2
+ 1
+
+
+ IOPDSMEN
+ I/O port D clock enable during Sleep
+ mode
+ 3
+ 1
+
+
+ IOPFSMEN
+ I/O port F clock enable during Sleep
+ mode
+ 5
+ 1
+
+
+
+
+ AHBSMENR
+ AHBSMENR
+ AHB peripheral clock enable in Sleep mode
+ register
+ 0x48
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DMASMEN
+ DMA clock enable during Sleep
+ mode
+ 0
+ 1
+
+
+ FLASHSMEN
+ Flash memory interface clock enable
+ during Sleep mode
+ 8
+ 1
+
+
+ SRAMSMEN
+ SRAM clock enable during Sleep
+ mode
+ 9
+ 1
+
+
+ CRCSMEN
+ CRC clock enable during Sleep
+ mode
+ 12
+ 1
+
+
+
+
+ APBSMENR1
+ APBSMENR1
+ APB peripheral clock enable in Sleep mode
+ register 1
+ 0x4C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TIM3SMEN
+ TIM3 timer clock enable during Sleep
+ mode
+ 1
+ 1
+
+
+ TIM6SMEN
+ TIM6 timer clock enable during Sleep
+ mode
+ 4
+ 1
+
+
+ TIM7SMEN
+ TIM7 timer clock enable during Sleep
+ mode
+ 5
+ 1
+
+
+ RTCAPBSMEN
+ RTC APB clock enable during Sleep
+ mode
+ 10
+ 1
+
+
+ WWDGSMEN
+ WWDG clock enable during Sleep
+ mode
+ 11
+ 1
+
+
+ SPI2SMEN
+ SPI2 clock enable during Sleep
+ mode
+ 14
+ 1
+
+
+ USART2SMEN
+ USART2 clock enable during Sleep
+ mode
+ 17
+ 1
+
+
+ USART3SMEN
+ USART3 clock enable during Sleep
+ mode
+ 18
+ 1
+
+
+ USART4SMEN
+ USART4 clock enable during Sleep
+ mode
+ 19
+ 1
+
+
+ I2C1SMEN
+ I2C1 clock enable during Sleep
+ mode
+ 21
+ 1
+
+
+ I2C2SMEN
+ I2C2 clock enable during Sleep
+ mode
+ 22
+ 1
+
+
+ DBGSMEN
+ Debug support clock enable during Sleep
+ mode
+ 27
+ 1
+
+
+ PWRSMEN
+ Power interface clock enable during
+ Sleep mode
+ 28
+ 1
+
+
+
+
+ APBSMENR2
+ APBSMENR2
+ APB peripheral clock enable in Sleep mode
+ register 2
+ 0x50
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SYSCFGSMEN
+ SYSCFG, COMP and VREFBUF clock enable
+ during Sleep mode
+ 0
+ 1
+
+
+ TIM1SMEN
+ TIM1 timer clock enable during Sleep
+ mode
+ 11
+ 1
+
+
+ SPI1SMEN
+ SPI1 clock enable during Sleep
+ mode
+ 12
+ 1
+
+
+ USART1SMEN
+ USART1 clock enable during Sleep
+ mode
+ 14
+ 1
+
+
+ TIM14SMEN
+ TIM14 timer clock enable during Sleep
+ mode
+ 15
+ 1
+
+
+ TIM15SMEN
+ TIM15 timer clock enable during Sleep
+ mode
+ 16
+ 1
+
+
+ TIM16SMEN
+ TIM16 timer clock enable during Sleep
+ mode
+ 17
+ 1
+
+
+ TIM17SMEN
+ TIM16 timer clock enable during Sleep
+ mode
+ 18
+ 1
+
+
+ ADCSMEN
+ ADC clock enable during Sleep
+ mode
+ 20
+ 1
+
+
+
+
+ CCIPR
+ CCIPR
+ Peripherals independent clock configuration
+ register
+ 0x54
+ 0x20
+ read-write
+ 0x00000000
+
+
+ USART1SEL
+ USART1 clock source
+ selection
+ 0
+ 2
+
+
+ USART2SEL
+ USART2 clock source
+ selection
+ 2
+ 2
+
+
+ I2C1SEL
+ I2C1 clock source
+ selection
+ 12
+ 2
+
+
+ I2S2SEL
+ I2S1 clock source
+ selection
+ 14
+ 2
+
+
+ TIM1SEL
+ TIM1 clock source
+ selection
+ 22
+ 1
+
+
+ TIM15SEL
+ TIM15 clock source
+ selection
+ 24
+ 1
+
+
+ ADCSEL
+ ADCs clock source
+ selection
+ 30
+ 2
+
+
+
+
+ BDCR
+ BDCR
+ RTC domain control register
+ 0x5C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LSEON
+ LSE oscillator enable
+ 0
+ 1
+
+
+ LSERDY
+ LSE oscillator ready
+ 1
+ 1
+
+
+ LSEBYP
+ LSE oscillator bypass
+ 2
+ 1
+
+
+ LSEDRV
+ LSE oscillator drive
+ capability
+ 3
+ 2
+
+
+ LSECSSON
+ CSS on LSE enable
+ 5
+ 1
+
+
+ LSECSSD
+ CSS on LSE failure
+ Detection
+ 6
+ 1
+
+
+ RTCSEL
+ RTC clock source selection
+ 8
+ 2
+
+
+ RTCEN
+ RTC clock enable
+ 15
+ 1
+
+
+ BDRST
+ RTC domain software reset
+ 16
+ 1
+
+
+ LSCOEN
+ Low-speed clock output (LSCO)
+ enable
+ 24
+ 1
+
+
+ LSCOSEL
+ Low-speed clock output
+ selection
+ 25
+ 1
+
+
+
+
+ CSR
+ CSR
+ Control/status register
+ 0x60
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LSION
+ LSI oscillator enable
+ 0
+ 1
+
+
+ LSIRDY
+ LSI oscillator ready
+ 1
+ 1
+
+
+ RMVF
+ Remove reset flags
+ 23
+ 1
+
+
+ OBLRSTF
+ Option byte loader reset
+ flag
+ 25
+ 1
+
+
+ PINRSTF
+ Pin reset flag
+ 26
+ 1
+
+
+ PWRRSTF
+ BOR or POR/PDR flag
+ 27
+ 1
+
+
+ SFTRSTF
+ Software reset flag
+ 28
+ 1
+
+
+ IWDGRSTF
+ Independent window watchdog reset
+ flag
+ 29
+ 1
+
+
+ WWDGRSTF
+ Window watchdog reset flag
+ 30
+ 1
+
+
+ LPWRRSTF
+ Low-power reset flag
+ 31
+ 1
+
+
+
+
+
+
+ PWR
+ Power control
+ PWR
+ 0x40007000
+
+ 0x0
+ 0x400
+ registers
+
+
+ PVD
+ Power voltage detector interrupt
+ 1
+
+
+
+ CR1
+ CR1
+ Power control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x00000200
+
+
+ LPR
+ Low-power run
+ 14
+ 1
+
+
+ VOS
+ Voltage scaling range
+ selection
+ 9
+ 2
+
+
+ DBP
+ Disable backup domain write
+ protection
+ 8
+ 1
+
+
+ FPD_LPSLP
+ Flash memory powered down during
+ Low-power sleep mode
+ 5
+ 1
+
+
+ FPD_LPRUN
+ Flash memory powered down during
+ Low-power run mode
+ 4
+ 1
+
+
+ FPD_STOP
+ Flash memory powered down during Stop
+ mode
+ 3
+ 1
+
+
+ LPMS
+ Low-power mode selection
+ 0
+ 3
+
+
+
+
+ CR2
+ CR2
+ Power control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PVDE
+ Power voltage detector
+ enable
+ 0
+ 1
+
+
+ PVDFT
+ Power voltage detector falling threshold
+ selection
+ 1
+ 3
+
+
+ PVDRT
+ Power voltage detector rising threshold
+ selection
+ 4
+ 3
+
+
+
+
+ CR3
+ CR3
+ Power control register 3
+ 0x8
+ 0x20
+ read-write
+ 0X00008000
+
+
+ EWUP1
+ Enable Wakeup pin WKUP1
+ 0
+ 1
+
+
+ EWUP2
+ Enable Wakeup pin WKUP2
+ 1
+ 1
+
+
+ EWUP4
+ Enable Wakeup pin WKUP4
+ 3
+ 1
+
+
+ EWUP5
+ Enable WKUP5 wakeup pin
+ 4
+ 1
+
+
+ EWUP6
+ Enable WKUP6 wakeup pin
+ 5
+ 1
+
+
+ RRS
+ SRAM retention in Standby
+ mode
+ 8
+ 1
+
+
+ ULPEN
+ Enable the periodical sampling mode for
+ PDR detection
+ 9
+ 1
+
+
+ APC
+ Apply pull-up and pull-down
+ configuration
+ 10
+ 1
+
+
+ EIWUL
+ Enable internal wakeup
+ line
+ 15
+ 1
+
+
+
+
+ CR4
+ CR4
+ Power control register 4
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ WP1
+ Wakeup pin WKUP1 polarity
+ 0
+ 1
+
+
+ WP2
+ Wakeup pin WKUP2 polarity
+ 1
+ 1
+
+
+ WP4
+ Wakeup pin WKUP4 polarity
+ 3
+ 1
+
+
+ WP5
+ Wakeup pin WKUP5 polarity
+ 4
+ 1
+
+
+ WP6
+ WKUP6 wakeup pin polarity
+ 5
+ 1
+
+
+ VBE
+ VBAT battery charging
+ enable
+ 8
+ 1
+
+
+ VBRS
+ VBAT battery charging resistor
+ selection
+ 9
+ 1
+
+
+
+
+ SR1
+ SR1
+ Power status register 1
+ 0x10
+ 0x20
+ read-only
+ 0x00000000
+
+
+ WUF1
+ Wakeup flag 1
+ 0
+ 1
+
+
+ WUF2
+ Wakeup flag 2
+ 1
+ 1
+
+
+ WUF4
+ Wakeup flag 4
+ 3
+ 1
+
+
+ WUF5
+ Wakeup flag 5
+ 4
+ 1
+
+
+ WUF6
+ Wakeup flag 6
+ 5
+ 1
+
+
+ SBF
+ Standby flag
+ 8
+ 1
+
+
+ WUFI
+ Wakeup flag internal
+ 15
+ 1
+
+
+
+
+ SR2
+ SR2
+ Power status register 2
+ 0x14
+ 0x20
+ read-only
+ 0x00000000
+
+
+ PVDO
+ Power voltage detector
+ output
+ 11
+ 1
+
+
+ VOSF
+ Voltage scaling flag
+ 10
+ 1
+
+
+ REGLPF
+ Low-power regulator flag
+ 9
+ 1
+
+
+ REGLPS
+ Low-power regulator
+ started
+ 8
+ 1
+
+
+ FLASH_RDY
+ Flash ready flag
+ 7
+ 1
+
+
+
+
+ SCR
+ SCR
+ Power status clear register
+ 0x18
+ 0x20
+ write-only
+ 0x00000000
+
+
+ CSBF
+ Clear standby flag
+ 8
+ 1
+
+
+ CWUF6
+ Clear wakeup flag 6
+ 5
+ 1
+
+
+ CWUF5
+ Clear wakeup flag 5
+ 4
+ 1
+
+
+ CWUF4
+ Clear wakeup flag 4
+ 3
+ 1
+
+
+ CWUF2
+ Clear wakeup flag 2
+ 1
+ 1
+
+
+ CWUF1
+ Clear wakeup flag 1
+ 0
+ 1
+
+
+
+
+ PUCRA
+ PUCRA
+ Power Port A pull-up control
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PU15
+ Port A pull-up bit y
+ (y=0..15)
+ 15
+ 1
+
+
+ PU14
+ Port A pull-up bit y
+ (y=0..15)
+ 14
+ 1
+
+
+ PU13
+ Port A pull-up bit y
+ (y=0..15)
+ 13
+ 1
+
+
+ PU12
+ Port A pull-up bit y
+ (y=0..15)
+ 12
+ 1
+
+
+ PU11
+ Port A pull-up bit y
+ (y=0..15)
+ 11
+ 1
+
+
+ PU10
+ Port A pull-up bit y
+ (y=0..15)
+ 10
+ 1
+
+
+ PU9
+ Port A pull-up bit y
+ (y=0..15)
+ 9
+ 1
+
+
+ PU8
+ Port A pull-up bit y
+ (y=0..15)
+ 8
+ 1
+
+
+ PU7
+ Port A pull-up bit y
+ (y=0..15)
+ 7
+ 1
+
+
+ PU6
+ Port A pull-up bit y
+ (y=0..15)
+ 6
+ 1
+
+
+ PU5
+ Port A pull-up bit y
+ (y=0..15)
+ 5
+ 1
+
+
+ PU4
+ Port A pull-up bit y
+ (y=0..15)
+ 4
+ 1
+
+
+ PU3
+ Port A pull-up bit y
+ (y=0..15)
+ 3
+ 1
+
+
+ PU2
+ Port A pull-up bit y
+ (y=0..15)
+ 2
+ 1
+
+
+ PU1
+ Port A pull-up bit y
+ (y=0..15)
+ 1
+ 1
+
+
+ PU0
+ Port A pull-up bit y
+ (y=0..15)
+ 0
+ 1
+
+
+
+
+ PDCRA
+ PDCRA
+ Power Port A pull-down control
+ register
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PD15
+ Port A pull-down bit y
+ (y=0..15)
+ 15
+ 1
+
+
+ PD14
+ Port A pull-down bit y
+ (y=0..15)
+ 14
+ 1
+
+
+ PD13
+ Port A pull-down bit y
+ (y=0..15)
+ 13
+ 1
+
+
+ PD12
+ Port A pull-down bit y
+ (y=0..15)
+ 12
+ 1
+
+
+ PD11
+ Port A pull-down bit y
+ (y=0..15)
+ 11
+ 1
+
+
+ PD10
+ Port A pull-down bit y
+ (y=0..15)
+ 10
+ 1
+
+
+ PD9
+ Port A pull-down bit y
+ (y=0..15)
+ 9
+ 1
+
+
+ PD8
+ Port A pull-down bit y
+ (y=0..15)
+ 8
+ 1
+
+
+ PD7
+ Port A pull-down bit y
+ (y=0..15)
+ 7
+ 1
+
+
+ PD6
+ Port A pull-down bit y
+ (y=0..15)
+ 6
+ 1
+
+
+ PD5
+ Port A pull-down bit y
+ (y=0..15)
+ 5
+ 1
+
+
+ PD4
+ Port A pull-down bit y
+ (y=0..15)
+ 4
+ 1
+
+
+ PD3
+ Port A pull-down bit y
+ (y=0..15)
+ 3
+ 1
+
+
+ PD2
+ Port A pull-down bit y
+ (y=0..15)
+ 2
+ 1
+
+
+ PD1
+ Port A pull-down bit y
+ (y=0..15)
+ 1
+ 1
+
+
+ PD0
+ Port A pull-down bit y
+ (y=0..15)
+ 0
+ 1
+
+
+
+
+ PUCRB
+ PUCRB
+ Power Port B pull-up control
+ register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PU15
+ Port B pull-up bit y
+ (y=0..15)
+ 15
+ 1
+
+
+ PU14
+ Port B pull-up bit y
+ (y=0..15)
+ 14
+ 1
+
+
+ PU13
+ Port B pull-up bit y
+ (y=0..15)
+ 13
+ 1
+
+
+ PU12
+ Port B pull-up bit y
+ (y=0..15)
+ 12
+ 1
+
+
+ PU11
+ Port B pull-up bit y
+ (y=0..15)
+ 11
+ 1
+
+
+ PU10
+ Port B pull-up bit y
+ (y=0..15)
+ 10
+ 1
+
+
+ PU9
+ Port B pull-up bit y
+ (y=0..15)
+ 9
+ 1
+
+
+ PU8
+ Port B pull-up bit y
+ (y=0..15)
+ 8
+ 1
+
+
+ PU7
+ Port B pull-up bit y
+ (y=0..15)
+ 7
+ 1
+
+
+ PU6
+ Port B pull-up bit y
+ (y=0..15)
+ 6
+ 1
+
+
+ PU5
+ Port B pull-up bit y
+ (y=0..15)
+ 5
+ 1
+
+
+ PU4
+ Port B pull-up bit y
+ (y=0..15)
+ 4
+ 1
+
+
+ PU3
+ Port B pull-up bit y
+ (y=0..15)
+ 3
+ 1
+
+
+ PU2
+ Port B pull-up bit y
+ (y=0..15)
+ 2
+ 1
+
+
+ PU1
+ Port B pull-up bit y
+ (y=0..15)
+ 1
+ 1
+
+
+ PU0
+ Port B pull-up bit y
+ (y=0..15)
+ 0
+ 1
+
+
+
+
+ PDCRB
+ PDCRB
+ Power Port B pull-down control
+ register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PD15
+ Port B pull-down bit y
+ (y=0..15)
+ 15
+ 1
+
+
+ PD14
+ Port B pull-down bit y
+ (y=0..15)
+ 14
+ 1
+
+
+ PD13
+ Port B pull-down bit y
+ (y=0..15)
+ 13
+ 1
+
+
+ PD12
+ Port B pull-down bit y
+ (y=0..15)
+ 12
+ 1
+
+
+ PD11
+ Port B pull-down bit y
+ (y=0..15)
+ 11
+ 1
+
+
+ PD10
+ Port B pull-down bit y
+ (y=0..15)
+ 10
+ 1
+
+
+ PD9
+ Port B pull-down bit y
+ (y=0..15)
+ 9
+ 1
+
+
+ PD8
+ Port B pull-down bit y
+ (y=0..15)
+ 8
+ 1
+
+
+ PD7
+ Port B pull-down bit y
+ (y=0..15)
+ 7
+ 1
+
+
+ PD6
+ Port B pull-down bit y
+ (y=0..15)
+ 6
+ 1
+
+
+ PD5
+ Port B pull-down bit y
+ (y=0..15)
+ 5
+ 1
+
+
+ PD4
+ Port B pull-down bit y
+ (y=0..15)
+ 4
+ 1
+
+
+ PD3
+ Port B pull-down bit y
+ (y=0..15)
+ 3
+ 1
+
+
+ PD2
+ Port B pull-down bit y
+ (y=0..15)
+ 2
+ 1
+
+
+ PD1
+ Port B pull-down bit y
+ (y=0..15)
+ 1
+ 1
+
+
+ PD0
+ Port B pull-down bit y
+ (y=0..15)
+ 0
+ 1
+
+
+
+
+ PUCRC
+ PUCRC
+ Power Port C pull-up control
+ register
+ 0x30
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PU15
+ Port C pull-up bit y
+ (y=0..15)
+ 15
+ 1
+
+
+ PU14
+ Port C pull-up bit y
+ (y=0..15)
+ 14
+ 1
+
+
+ PU13
+ Port C pull-up bit y
+ (y=0..15)
+ 13
+ 1
+
+
+ PU12
+ Port C pull-up bit y
+ (y=0..15)
+ 12
+ 1
+
+
+ PU11
+ Port C pull-up bit y
+ (y=0..15)
+ 11
+ 1
+
+
+ PU10
+ Port C pull-up bit y
+ (y=0..15)
+ 10
+ 1
+
+
+ PU9
+ Port C pull-up bit y
+ (y=0..15)
+ 9
+ 1
+
+
+ PU8
+ Port C pull-up bit y
+ (y=0..15)
+ 8
+ 1
+
+
+ PU7
+ Port C pull-up bit y
+ (y=0..15)
+ 7
+ 1
+
+
+ PU6
+ Port C pull-up bit y
+ (y=0..15)
+ 6
+ 1
+
+
+ PU5
+ Port C pull-up bit y
+ (y=0..15)
+ 5
+ 1
+
+
+ PU4
+ Port C pull-up bit y
+ (y=0..15)
+ 4
+ 1
+
+
+ PU3
+ Port C pull-up bit y
+ (y=0..15)
+ 3
+ 1
+
+
+ PU2
+ Port C pull-up bit y
+ (y=0..15)
+ 2
+ 1
+
+
+ PU1
+ Port C pull-up bit y
+ (y=0..15)
+ 1
+ 1
+
+
+ PU0
+ Port C pull-up bit y
+ (y=0..15)
+ 0
+ 1
+
+
+
+
+ PDCRC
+ PDCRC
+ Power Port C pull-down control
+ register
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PD15
+ Port C pull-down bit y
+ (y=0..15)
+ 15
+ 1
+
+
+ PD14
+ Port C pull-down bit y
+ (y=0..15)
+ 14
+ 1
+
+
+ PD13
+ Port C pull-down bit y
+ (y=0..15)
+ 13
+ 1
+
+
+ PD12
+ Port C pull-down bit y
+ (y=0..15)
+ 12
+ 1
+
+
+ PD11
+ Port C pull-down bit y
+ (y=0..15)
+ 11
+ 1
+
+
+ PD10
+ Port C pull-down bit y
+ (y=0..15)
+ 10
+ 1
+
+
+ PD9
+ Port C pull-down bit y
+ (y=0..15)
+ 9
+ 1
+
+
+ PD8
+ Port C pull-down bit y
+ (y=0..15)
+ 8
+ 1
+
+
+ PD7
+ Port C pull-down bit y
+ (y=0..15)
+ 7
+ 1
+
+
+ PD6
+ Port C pull-down bit y
+ (y=0..15)
+ 6
+ 1
+
+
+ PD5
+ Port C pull-down bit y
+ (y=0..15)
+ 5
+ 1
+
+
+ PD4
+ Port C pull-down bit y
+ (y=0..15)
+ 4
+ 1
+
+
+ PD3
+ Port C pull-down bit y
+ (y=0..15)
+ 3
+ 1
+
+
+ PD2
+ Port C pull-down bit y
+ (y=0..15)
+ 2
+ 1
+
+
+ PD1
+ Port C pull-down bit y
+ (y=0..15)
+ 1
+ 1
+
+
+ PD0
+ Port C pull-down bit y
+ (y=0..15)
+ 0
+ 1
+
+
+
+
+ PUCRD
+ PUCRD
+ Power Port D pull-up control
+ register
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PU9
+ Port D pull-up bit y
+ (y=0..15)
+ 9
+ 1
+
+
+ PU8
+ Port D pull-up bit y
+ (y=0..15)
+ 8
+ 1
+
+
+ PU6
+ Port D pull-up bit y
+ (y=0..15)
+ 6
+ 1
+
+
+ PU5
+ Port D pull-up bit y
+ (y=0..15)
+ 5
+ 1
+
+
+ PU4
+ Port D pull-up bit y
+ (y=0..15)
+ 4
+ 1
+
+
+ PU3
+ Port D pull-up bit y
+ (y=0..15)
+ 3
+ 1
+
+
+ PU2
+ Port D pull-up bit y
+ (y=0..15)
+ 2
+ 1
+
+
+ PU1
+ Port D pull-up bit y
+ (y=0..15)
+ 1
+ 1
+
+
+ PU0
+ Port D pull-up bit y
+ (y=0..15)
+ 0
+ 1
+
+
+
+
+ PDCRD
+ PDCRD
+ Power Port D pull-down control
+ register
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PD9
+ Port D pull-down bit y
+ (y=0..15)
+ 9
+ 1
+
+
+ PD8
+ Port D pull-down bit y
+ (y=0..15)
+ 8
+ 1
+
+
+ PD6
+ Port D pull-down bit y
+ (y=0..15)
+ 6
+ 1
+
+
+ PD5
+ Port D pull-down bit y
+ (y=0..15)
+ 5
+ 1
+
+
+ PD4
+ Port D pull-down bit y
+ (y=0..15)
+ 4
+ 1
+
+
+ PD3
+ Port D pull-down bit y
+ (y=0..15)
+ 3
+ 1
+
+
+ PD2
+ Port D pull-down bit y
+ (y=0..15)
+ 2
+ 1
+
+
+ PD1
+ Port D pull-down bit y
+ (y=0..15)
+ 1
+ 1
+
+
+ PD0
+ Port D pull-down bit y
+ (y=0..15)
+ 0
+ 1
+
+
+
+
+ PUCRF
+ PUCRF
+ Power Port F pull-up control
+ register
+ 0x48
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PU2
+ Port F pull-up bit y
+ (y=0..15)
+ 2
+ 1
+
+
+ PU1
+ Port F pull-up bit y
+ (y=0..15)
+ 1
+ 1
+
+
+ PU0
+ Port F pull-up bit y
+ (y=0..15)
+ 0
+ 1
+
+
+
+
+ PDCRF
+ PDCRF
+ Power Port F pull-down control
+ register
+ 0x4C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PD2
+ Port F pull-down bit y
+ (y=0..15)
+ 2
+ 1
+
+
+ PD1
+ Port F pull-down bit y
+ (y=0..15)
+ 1
+ 1
+
+
+ PD0
+ Port F pull-down bit y
+ (y=0..15)
+ 0
+ 1
+
+
+
+
+
+
+ DMA
+ DMA controller
+ DMA
+ 0x40020000
+
+ 0x0
+ 0x400
+ registers
+
+
+ DMA_Channel1
+ DMA channel 1 interrupt
+ 9
+
+
+ DMA_Channel2_3
+ DMA channel 2 & 3 interrupts
+ 10
+
+
+ 7 0x14 1,2,3,4,5,6,7 CH%s Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers 0x8
+ CR
+ CCR1
+ DMA channel x configuration
+ register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+ TCIE
+ Transfer complete interrupt
+ enable
+ 1
+ 1
+
+
+ HTIE
+ Half transfer interrupt
+ enable
+ 2
+ 1
+
+
+ TEIE
+ Transfer error interrupt
+ enable
+ 3
+ 1
+
+
+ DIR
+ Data transfer direction
+ 4
+ 1
+
+
+ CIRC
+ Circular mode
+ 5
+ 1
+
+
+ PINC
+ Peripheral increment mode
+ 6
+ 1
+
+
+ MINC
+ Memory increment mode
+ 7
+ 1
+
+
+ PSIZE
+ Peripheral size
+ 8
+ 2
+
+
+ MSIZE
+ Memory size
+ 10
+ 2
+
+
+ PL
+ Channel priority level
+ 12
+ 2
+
+
+ MEM2MEM
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ NDTR
+ CNDTR1
+ DMA channel x number of data
+ register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NDT
+ Number of data to transfer
+ 0
+ 16
+
+
+
+
+ PAR
+ CPAR1
+ DMA channel x peripheral address
+ register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PA
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ MAR
+ CMAR1
+ DMA channel x memory address
+ register
+ 0xc
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MA
+ Memory address
+ 0
+ 32
+
+
+
+
+ ISR
+ ISR
+ low interrupt status register
+ 0x0
+ 0x20
+ read-only
+ 0x00000000
+
+
+ GIF0
+ Channel global interrupt
+ flag
+ 0
+ 1
+
+
+ TCIF1
+ Channel 1 transfer complete flag
+ 1
+ 1
+
+
+ HTIF2
+ Channel 2 half transfer flag
+ 2
+ 1
+
+
+ TEIF3
+ Channel 3 transfer error flag
+ 3
+ 1
+
+
+ GIF4
+ Channel 4 global interrupt flag
+ 4
+ 1
+
+
+ TCIF5
+ Channel 5 transfer complete flag
+ 5
+ 1
+
+
+ HTIF6
+ Channel 6 half transfer flag
+ 6
+ 1
+
+
+ TEIF7
+ Channel 7 transfer error flag
+ 7
+ 1
+
+
+ GIF8
+ Channel global interrupt
+ flag
+ 8
+ 1
+
+
+ TCIF9
+ Channel transfer complete
+ flag
+ 9
+ 1
+
+
+ HTIF10
+ Channel half transfer flag
+ 10
+ 1
+
+
+ TEIF11
+ Channel transfer error
+ flag
+ 11
+ 1
+
+
+ GIF12
+ Channel global interrupt
+ flag
+ 12
+ 1
+
+
+ TCIF13
+ Channel transfer complete
+ flag
+ 13
+ 1
+
+
+ HTIF14
+ Channel half transfer flag
+ 14
+ 1
+
+
+ TEIF15
+ Channel transfer error
+ flag
+ 15
+ 1
+
+
+ GIF16
+ Channel global interrupt
+ flag
+ 16
+ 1
+
+
+ TCIF17
+ Channel transfer complete
+ flag
+ 17
+ 1
+
+
+ HTIF18
+ Channel half transfer flag
+ 18
+ 1
+
+
+ TEIF19
+ Channel transfer error
+ flag
+ 19
+ 1
+
+
+ GIF20
+ Channel global interrupt
+ flag
+ 20
+ 1
+
+
+ TCIF21
+ Channel transfer complete
+ flag
+ 21
+ 1
+
+
+ HTIF22
+ Channel half transfer flag
+ 22
+ 1
+
+
+ TEIF23
+ Channel transfer error
+ flag
+ 23
+ 1
+
+
+ GIF24
+ Channel global interrupt
+ flag
+ 24
+ 1
+
+
+ TCIF25
+ Channel transfer complete
+ flag
+ 25
+ 1
+
+
+ HTIF26
+ Channel half transfer flag
+ 26
+ 1
+
+
+ TEIF27
+ Channel transfer error
+ flag
+ 27
+ 1
+
+
+
+
+ IFCR
+ IFCR
+ high interrupt status register
+ 0x4
+ 0x20
+ write-only
+ 0x00000000
+
+
+ CGIF1
+ Clear channel 1 global interrupt flag
+ 0
+ 1
+
+
+ CTCIF1
+ Clear channel 1 transfer complete flag
+ 1
+ 1
+
+
+ CHTIF2
+ Clear channel 2 half transfer flag
+ 2
+ 1
+
+
+ CTEIF3
+ Clear channel 3 transfer error flag
+ 3
+ 1
+
+
+ CGIF4
+ Clear channel 4 global interrupt flag
+ 4
+ 1
+
+
+ CTCIF5
+ Clear channel 5 transfer complete flag
+ 5
+ 1
+
+
+ CHTIF6
+ Clear channel 6 half transfer flag
+ 6
+ 1
+
+
+ CTEIF7
+ Clear channel 7 transfer error flag
+ 7
+ 1
+
+
+ CGIF8
+ Channel global interrupt
+ flag
+ 8
+ 1
+
+
+ CTCIF9
+ Channel transfer complete
+ flag
+ 9
+ 1
+
+
+ CHTIF10
+ Channel half transfer flag
+ 10
+ 1
+
+
+ CTEIF11
+ Channel transfer error
+ flag
+ 11
+ 1
+
+
+ CGIF12
+ Channel global interrupt
+ flag
+ 12
+ 1
+
+
+ CTCIF13
+ Channel transfer complete
+ flag
+ 13
+ 1
+
+
+ CHTIF14
+ Channel half transfer flag
+ 14
+ 1
+
+
+ CTEIF4
+ Clear channel 4 transfer error flag
+ 15
+ 1
+
+
+ CGIF16
+ Channel global interrupt
+ flag
+ 16
+ 1
+
+
+ CTCIF17
+ Channel transfer complete
+ flag
+ 17
+ 1
+
+
+ CHTIF18
+ Channel half transfer flag
+ 18
+ 1
+
+
+ CTEIF19
+ Channel transfer error
+ flag
+ 19
+ 1
+
+
+ CGIF20
+ Channel global interrupt
+ flag
+ 20
+ 1
+
+
+ CTCIF21
+ Channel transfer complete
+ flag
+ 21
+ 1
+
+
+ CHTIF22
+ Channel half transfer flag
+ 22
+ 1
+
+
+ CTEIF23
+ Channel transfer error
+ flag
+ 23
+ 1
+
+
+ CGIF24
+ Channel global interrupt
+ flag
+ 24
+ 1
+
+
+ CTCIF25
+ Channel transfer complete
+ flag
+ 25
+ 1
+
+
+ CHTIF26
+ Channel half transfer flag
+ 26
+ 1
+
+
+ CTEIF27
+ Channel transfer error
+ flag
+ 27
+ 1
+
+
+
+
+
+
+ DMAMUX
+ DMAMUX
+ DMAMUX
+ 0x40020800
+
+ 0x0
+ 0x400
+ registers
+
+
+ DMA_Channel4_5_6_7
+ DMA channel 4, 5, 6 & 7 and
+ DMAMUX
+ 11
+
+
+
+ C0CR
+ C0CR
+ DMAMux - DMA request line multiplexer
+ channel x control register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DMAREQ_ID
+ Input DMA request line
+ selected
+ 0
+ 8
+
+
+ SOIE
+ Interrupt enable at synchronization
+ event overrun
+ 8
+ 1
+
+
+ EGE
+ Event generation
+ enable/disable
+ 9
+ 1
+
+
+ SE
+ Synchronous operating mode
+ enable/disable
+ 16
+ 1
+
+
+ SPOL
+ Synchronization event type selector
+ Defines the synchronization event on the selected
+ synchronization input:
+ 17
+ 2
+
+
+ NBREQ
+ Number of DMA requests to forward
+ Defines the number of DMA requests forwarded before
+ output event is generated. In synchronous mode, it
+ also defines the number of DMA requests to forward
+ after a synchronization event, then stop forwarding.
+ The actual number of DMA requests forwarded is
+ NBREQ+1. Note: This field can only be written when
+ both SE and EGE bits are reset.
+ 19
+ 5
+
+
+ SYNC_ID
+ Synchronization input
+ selected
+ 24
+ 5
+
+
+
+
+ C1CR
+ C1CR
+ DMAMux - DMA request line multiplexer
+ channel x control register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DMAREQ_ID
+ Input DMA request line
+ selected
+ 0
+ 8
+
+
+ SOIE
+ Interrupt enable at synchronization
+ event overrun
+ 8
+ 1
+
+
+ EGE
+ Event generation
+ enable/disable
+ 9
+ 1
+
+
+ SE
+ Synchronous operating mode
+ enable/disable
+ 16
+ 1
+
+
+ SPOL
+ Synchronization event type selector
+ Defines the synchronization event on the selected
+ synchronization input:
+ 17
+ 2
+
+
+ NBREQ
+ Number of DMA requests to forward
+ Defines the number of DMA requests forwarded before
+ output event is generated. In synchronous mode, it
+ also defines the number of DMA requests to forward
+ after a synchronization event, then stop forwarding.
+ The actual number of DMA requests forwarded is
+ NBREQ+1. Note: This field can only be written when
+ both SE and EGE bits are reset.
+ 19
+ 5
+
+
+ SYNC_ID
+ Synchronization input
+ selected
+ 24
+ 5
+
+
+
+
+ C2CR
+ C2CR
+ DMAMux - DMA request line multiplexer
+ channel x control register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DMAREQ_ID
+ Input DMA request line
+ selected
+ 0
+ 8
+
+
+ SOIE
+ Interrupt enable at synchronization
+ event overrun
+ 8
+ 1
+
+
+ EGE
+ Event generation
+ enable/disable
+ 9
+ 1
+
+
+ SE
+ Synchronous operating mode
+ enable/disable
+ 16
+ 1
+
+
+ SPOL
+ Synchronization event type selector
+ Defines the synchronization event on the selected
+ synchronization input:
+ 17
+ 2
+
+
+ NBREQ
+ Number of DMA requests to forward
+ Defines the number of DMA requests forwarded before
+ output event is generated. In synchronous mode, it
+ also defines the number of DMA requests to forward
+ after a synchronization event, then stop forwarding.
+ The actual number of DMA requests forwarded is
+ NBREQ+1. Note: This field can only be written when
+ both SE and EGE bits are reset.
+ 19
+ 5
+
+
+ SYNC_ID
+ Synchronization input
+ selected
+ 24
+ 5
+
+
+
+
+ C3CR
+ C3CR
+ DMAMux - DMA request line multiplexer
+ channel x control register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DMAREQ_ID
+ Input DMA request line
+ selected
+ 0
+ 8
+
+
+ SOIE
+ Interrupt enable at synchronization
+ event overrun
+ 8
+ 1
+
+
+ EGE
+ Event generation
+ enable/disable
+ 9
+ 1
+
+
+ SE
+ Synchronous operating mode
+ enable/disable
+ 16
+ 1
+
+
+ SPOL
+ Synchronization event type selector
+ Defines the synchronization event on the selected
+ synchronization input:
+ 17
+ 2
+
+
+ NBREQ
+ Number of DMA requests to forward
+ Defines the number of DMA requests forwarded before
+ output event is generated. In synchronous mode, it
+ also defines the number of DMA requests to forward
+ after a synchronization event, then stop forwarding.
+ The actual number of DMA requests forwarded is
+ NBREQ+1. Note: This field can only be written when
+ both SE and EGE bits are reset.
+ 19
+ 5
+
+
+ SYNC_ID
+ Synchronization input
+ selected
+ 24
+ 5
+
+
+
+
+ C4CR
+ C4CR
+ DMAMux - DMA request line multiplexer
+ channel x control register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DMAREQ_ID
+ Input DMA request line
+ selected
+ 0
+ 8
+
+
+ SOIE
+ Interrupt enable at synchronization
+ event overrun
+ 8
+ 1
+
+
+ EGE
+ Event generation
+ enable/disable
+ 9
+ 1
+
+
+ SE
+ Synchronous operating mode
+ enable/disable
+ 16
+ 1
+
+
+ SPOL
+ Synchronization event type selector
+ Defines the synchronization event on the selected
+ synchronization input:
+ 17
+ 2
+
+
+ NBREQ
+ Number of DMA requests to forward
+ Defines the number of DMA requests forwarded before
+ output event is generated. In synchronous mode, it
+ also defines the number of DMA requests to forward
+ after a synchronization event, then stop forwarding.
+ The actual number of DMA requests forwarded is
+ NBREQ+1. Note: This field can only be written when
+ both SE and EGE bits are reset.
+ 19
+ 5
+
+
+ SYNC_ID
+ Synchronization input
+ selected
+ 24
+ 5
+
+
+
+
+ C5CR
+ C5CR
+ DMAMux - DMA request line multiplexer
+ channel x control register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DMAREQ_ID
+ Input DMA request line
+ selected
+ 0
+ 8
+
+
+ SOIE
+ Interrupt enable at synchronization
+ event overrun
+ 8
+ 1
+
+
+ EGE
+ Event generation
+ enable/disable
+ 9
+ 1
+
+
+ SE
+ Synchronous operating mode
+ enable/disable
+ 16
+ 1
+
+
+ SPOL
+ Synchronization event type selector
+ Defines the synchronization event on the selected
+ synchronization input:
+ 17
+ 2
+
+
+ NBREQ
+ Number of DMA requests to forward
+ Defines the number of DMA requests forwarded before
+ output event is generated. In synchronous mode, it
+ also defines the number of DMA requests to forward
+ after a synchronization event, then stop forwarding.
+ The actual number of DMA requests forwarded is
+ NBREQ+1. Note: This field can only be written when
+ both SE and EGE bits are reset.
+ 19
+ 5
+
+
+ SYNC_ID
+ Synchronization input
+ selected
+ 24
+ 5
+
+
+
+
+ C6CR
+ C6CR
+ DMAMux - DMA request line multiplexer
+ channel x control register
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DMAREQ_ID
+ Input DMA request line
+ selected
+ 0
+ 8
+
+
+ SOIE
+ Interrupt enable at synchronization
+ event overrun
+ 8
+ 1
+
+
+ EGE
+ Event generation
+ enable/disable
+ 9
+ 1
+
+
+ SE
+ Synchronous operating mode
+ enable/disable
+ 16
+ 1
+
+
+ SPOL
+ Synchronization event type selector
+ Defines the synchronization event on the selected
+ synchronization input:
+ 17
+ 2
+
+
+ NBREQ
+ Number of DMA requests to forward
+ Defines the number of DMA requests forwarded before
+ output event is generated. In synchronous mode, it
+ also defines the number of DMA requests to forward
+ after a synchronization event, then stop forwarding.
+ The actual number of DMA requests forwarded is
+ NBREQ+1. Note: This field can only be written when
+ both SE and EGE bits are reset.
+ 19
+ 5
+
+
+ SYNC_ID
+ Synchronization input
+ selected
+ 24
+ 5
+
+
+
+
+ RG0CR
+ RG0CR
+ DMAMux - DMA request generator channel x
+ control register
+ 0x100
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SIG_ID
+ DMA request trigger input
+ selected
+ 0
+ 5
+
+
+ OIE
+ Interrupt enable at trigger event
+ overrun
+ 8
+ 1
+
+
+ GE
+ DMA request generator channel
+ enable/disable
+ 16
+ 1
+
+
+ GPOL
+ DMA request generator trigger event type
+ selection Defines the trigger event on the selected
+ DMA request trigger input
+ 17
+ 2
+
+
+ GNBREQ
+ Number of DMA requests to generate
+ Defines the number of DMA requests generated after a
+ trigger event, then stop generating. The actual
+ number of generated DMA requests is GNBREQ+1. Note:
+ This field can only be written when GE bit is
+ reset.
+ 19
+ 5
+
+
+
+
+ RG1CR
+ RG1CR
+ DMAMux - DMA request generator channel x
+ control register
+ 0x104
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SIG_ID
+ DMA request trigger input
+ selected
+ 0
+ 5
+
+
+ OIE
+ Interrupt enable at trigger event
+ overrun
+ 8
+ 1
+
+
+ GE
+ DMA request generator channel
+ enable/disable
+ 16
+ 1
+
+
+ GPOL
+ DMA request generator trigger event type
+ selection Defines the trigger event on the selected
+ DMA request trigger input
+ 17
+ 2
+
+
+ GNBREQ
+ Number of DMA requests to generate
+ Defines the number of DMA requests generated after a
+ trigger event, then stop generating. The actual
+ number of generated DMA requests is GNBREQ+1. Note:
+ This field can only be written when GE bit is
+ reset.
+ 19
+ 5
+
+
+
+
+ RG2CR
+ RG2CR
+ DMAMux - DMA request generator channel x
+ control register
+ 0x108
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SIG_ID
+ DMA request trigger input
+ selected
+ 0
+ 5
+
+
+ OIE
+ Interrupt enable at trigger event
+ overrun
+ 8
+ 1
+
+
+ GE
+ DMA request generator channel
+ enable/disable
+ 16
+ 1
+
+
+ GPOL
+ DMA request generator trigger event type
+ selection Defines the trigger event on the selected
+ DMA request trigger input
+ 17
+ 2
+
+
+ GNBREQ
+ Number of DMA requests to generate
+ Defines the number of DMA requests generated after a
+ trigger event, then stop generating. The actual
+ number of generated DMA requests is GNBREQ+1. Note:
+ This field can only be written when GE bit is
+ reset.
+ 19
+ 5
+
+
+
+
+ RG3CR
+ RG3CR
+ DMAMux - DMA request generator channel x
+ control register
+ 0x10C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SIG_ID
+ DMA request trigger input
+ selected
+ 0
+ 5
+
+
+ OIE
+ Interrupt enable at trigger event
+ overrun
+ 8
+ 1
+
+
+ GE
+ DMA request generator channel
+ enable/disable
+ 16
+ 1
+
+
+ GPOL
+ DMA request generator trigger event type
+ selection Defines the trigger event on the selected
+ DMA request trigger input
+ 17
+ 2
+
+
+ GNBREQ
+ Number of DMA requests to generate
+ Defines the number of DMA requests generated after a
+ trigger event, then stop generating. The actual
+ number of generated DMA requests is GNBREQ+1. Note:
+ This field can only be written when GE bit is
+ reset.
+ 19
+ 5
+
+
+
+
+ RGSR
+ RGSR
+ DMAMux - DMA request generator status
+ register
+ 0x140
+ 0x20
+ read-only
+ 0x00000000
+
+
+ OF
+ Trigger event overrun flag The flag is
+ set when a trigger event occurs on DMA request
+ generator channel x, while the DMA request generator
+ counter value is lower than GNBREQ. The flag is
+ cleared by writing 1 to the corresponding COFx bit in
+ DMAMUX_RGCFR register.
+ 0
+ 4
+
+
+
+
+ RGCFR
+ RGCFR
+ DMAMux - DMA request generator clear flag
+ register
+ 0x144
+ 0x20
+ write-only
+ 0x00000000
+
+
+ COF
+ Clear trigger event overrun flag Upon
+ setting, this bit clears the corresponding overrun
+ flag OFx in the DMAMUX_RGCSR register.
+ 0
+ 4
+
+
+
+
+ CSR
+ CSR
+ DMAMUX request line multiplexer interrupt
+ channel status register
+ 0x80
+ 0x20
+ read-only
+ 0x00000000
+
+
+ SOF
+ Synchronization overrun event
+ flag
+ 0
+ 7
+
+
+
+
+ CFR
+ CFR
+ DMAMUX request line multiplexer interrupt
+ clear flag register
+ 0x84
+ 0x20
+ write-only
+ 0x00000000
+
+
+ CSOF
+ Clear synchronization overrun event
+ flag
+ 0
+ 7
+
+
+
+
+ SIDR
+ SIDR
+ DMAMUX size identification
+ register
+ 0x3FC
+ 0x20
+ read-only
+ 0xA3C5DD01
+
+
+ SID
+ Size identification
+ 0
+ 32
+
+
+
+
+ IPIDR
+ IPIDR
+ DMAMUX IP identification
+ register
+ 0x3F8
+ 0x20
+ read-only
+ 0x00100011
+
+
+ ID
+ IP identification
+ 0
+ 32
+
+
+
+
+ VERR
+ VERR
+ DMAMUX version register
+ 0x3F4
+ 0x20
+ read-only
+ 0x00000011
+
+
+ MINREV
+ Minor IP revision
+ 0
+ 4
+
+
+ MAJREV
+ Major IP revision
+ 4
+ 4
+
+
+
+
+ HWCFGR1
+ HWCFGR1
+ DMAMUX hardware configuration 1
+ register
+ 0x3F0
+ 0x20
+ read-only
+ 0x04173907
+
+
+ NUM_DMA_STREAMS
+ number of DMA request line multiplexer
+ (output) channels
+ 0
+ 8
+
+
+ NUM_DMA_PERIPH_REQ
+ number of DMA request lines from
+ peripherals
+ 8
+ 8
+
+
+ NUM_DMA_TRIG
+ number of synchronization
+ inputs
+ 16
+ 8
+
+
+ NUM_DMA_REQGEN
+ number of DMA request generator
+ channels
+ 24
+ 8
+
+
+
+
+ HWCFGR2
+ HWCFGR2
+ DMAMUX hardware configuration 2
+ register
+ 0x3EC
+ 0x20
+ read-only
+ 0x00000017
+
+
+ NUM_DMA_EXT_REQ
+ Number of DMA request trigger
+ inputs
+ 0
+ 8
+
+
+
+
+
+
+ GPIOA
+ General-purpose I/Os
+ GPIO
+ 0x50000000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ MODER
+ MODER
+ GPIO port mode register
+ 0x0
+ 0x20
+ read-write
+ 0xEBFFFFFF
+
+
+ MODER15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ MODER14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ MODER13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ MODER12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ MODER11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ MODER10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ MODER9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ MODER8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ MODER7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ MODER6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ MODER5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ MODER4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ MODER3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ MODER2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ MODER1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ MODER0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ OTYPER
+ OTYPER
+ GPIO port output type register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OT15
+ Port x configuration bits (y =
+ 0..15)
+ 15
+ 1
+
+
+ OT14
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 1
+
+
+ OT13
+ Port x configuration bits (y =
+ 0..15)
+ 13
+ 1
+
+
+ OT12
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 1
+
+
+ OT11
+ Port x configuration bits (y =
+ 0..15)
+ 11
+ 1
+
+
+ OT10
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 1
+
+
+ OT9
+ Port x configuration bits (y =
+ 0..15)
+ 9
+ 1
+
+
+ OT8
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 1
+
+
+ OT7
+ Port x configuration bits (y =
+ 0..15)
+ 7
+ 1
+
+
+ OT6
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 1
+
+
+ OT5
+ Port x configuration bits (y =
+ 0..15)
+ 5
+ 1
+
+
+ OT4
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 1
+
+
+ OT3
+ Port x configuration bits (y =
+ 0..15)
+ 3
+ 1
+
+
+ OT2
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 1
+
+
+ OT1
+ Port x configuration bits (y =
+ 0..15)
+ 1
+ 1
+
+
+ OT0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ OSPEEDR
+ OSPEEDR
+ GPIO port output speed
+ register
+ 0x8
+ 0x20
+ read-write
+ 0x0C000000
+
+
+ OSPEEDR15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ OSPEEDR14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ OSPEEDR13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ OSPEEDR12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ OSPEEDR11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ OSPEEDR10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ OSPEEDR9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ OSPEEDR8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ OSPEEDR7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ OSPEEDR6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ OSPEEDR5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ OSPEEDR4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ OSPEEDR3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ OSPEEDR2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ OSPEEDR1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ OSPEEDR0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ PUPDR
+ PUPDR
+ GPIO port pull-up/pull-down
+ register
+ 0xC
+ 0x20
+ read-write
+ 0x24000000
+
+
+ PUPDR15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ PUPDR14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ PUPDR13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ PUPDR12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ PUPDR11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ PUPDR10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ PUPDR9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ PUPDR8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ PUPDR7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ PUPDR6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ PUPDR5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ PUPDR4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ PUPDR3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ PUPDR2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ PUPDR1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ PUPDR0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ IDR
+ IDR
+ GPIO port input data register
+ 0x10
+ 0x20
+ read-only
+ 0x00000000
+
+
+ IDR15
+ Port input data (y =
+ 0..15)
+ 15
+ 1
+
+
+ IDR14
+ Port input data (y =
+ 0..15)
+ 14
+ 1
+
+
+ IDR13
+ Port input data (y =
+ 0..15)
+ 13
+ 1
+
+
+ IDR12
+ Port input data (y =
+ 0..15)
+ 12
+ 1
+
+
+ IDR11
+ Port input data (y =
+ 0..15)
+ 11
+ 1
+
+
+ IDR10
+ Port input data (y =
+ 0..15)
+ 10
+ 1
+
+
+ IDR9
+ Port input data (y =
+ 0..15)
+ 9
+ 1
+
+
+ IDR8
+ Port input data (y =
+ 0..15)
+ 8
+ 1
+
+
+ IDR7
+ Port input data (y =
+ 0..15)
+ 7
+ 1
+
+
+ IDR6
+ Port input data (y =
+ 0..15)
+ 6
+ 1
+
+
+ IDR5
+ Port input data (y =
+ 0..15)
+ 5
+ 1
+
+
+ IDR4
+ Port input data (y =
+ 0..15)
+ 4
+ 1
+
+
+ IDR3
+ Port input data (y =
+ 0..15)
+ 3
+ 1
+
+
+ IDR2
+ Port input data (y =
+ 0..15)
+ 2
+ 1
+
+
+ IDR1
+ Port input data (y =
+ 0..15)
+ 1
+ 1
+
+
+ IDR0
+ Port input data (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ ODR
+ ODR
+ GPIO port output data register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ODR15
+ Port output data (y =
+ 0..15)
+ 15
+ 1
+
+
+ ODR14
+ Port output data (y =
+ 0..15)
+ 14
+ 1
+
+
+ ODR13
+ Port output data (y =
+ 0..15)
+ 13
+ 1
+
+
+ ODR12
+ Port output data (y =
+ 0..15)
+ 12
+ 1
+
+
+ ODR11
+ Port output data (y =
+ 0..15)
+ 11
+ 1
+
+
+ ODR10
+ Port output data (y =
+ 0..15)
+ 10
+ 1
+
+
+ ODR9
+ Port output data (y =
+ 0..15)
+ 9
+ 1
+
+
+ ODR8
+ Port output data (y =
+ 0..15)
+ 8
+ 1
+
+
+ ODR7
+ Port output data (y =
+ 0..15)
+ 7
+ 1
+
+
+ ODR6
+ Port output data (y =
+ 0..15)
+ 6
+ 1
+
+
+ ODR5
+ Port output data (y =
+ 0..15)
+ 5
+ 1
+
+
+ ODR4
+ Port output data (y =
+ 0..15)
+ 4
+ 1
+
+
+ ODR3
+ Port output data (y =
+ 0..15)
+ 3
+ 1
+
+
+ ODR2
+ Port output data (y =
+ 0..15)
+ 2
+ 1
+
+
+ ODR1
+ Port output data (y =
+ 0..15)
+ 1
+ 1
+
+
+ ODR0
+ Port output data (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ BSRR
+ BSRR
+ GPIO port bit set/reset
+ register
+ 0x18
+ 0x20
+ write-only
+ 0x00000000
+
+
+ BR15
+ Port x reset bit y (y =
+ 0..15)
+ 31
+ 1
+
+
+ BR14
+ Port x reset bit y (y =
+ 0..15)
+ 30
+ 1
+
+
+ BR13
+ Port x reset bit y (y =
+ 0..15)
+ 29
+ 1
+
+
+ BR12
+ Port x reset bit y (y =
+ 0..15)
+ 28
+ 1
+
+
+ BR11
+ Port x reset bit y (y =
+ 0..15)
+ 27
+ 1
+
+
+ BR10
+ Port x reset bit y (y =
+ 0..15)
+ 26
+ 1
+
+
+ BR9
+ Port x reset bit y (y =
+ 0..15)
+ 25
+ 1
+
+
+ BR8
+ Port x reset bit y (y =
+ 0..15)
+ 24
+ 1
+
+
+ BR7
+ Port x reset bit y (y =
+ 0..15)
+ 23
+ 1
+
+
+ BR6
+ Port x reset bit y (y =
+ 0..15)
+ 22
+ 1
+
+
+ BR5
+ Port x reset bit y (y =
+ 0..15)
+ 21
+ 1
+
+
+ BR4
+ Port x reset bit y (y =
+ 0..15)
+ 20
+ 1
+
+
+ BR3
+ Port x reset bit y (y =
+ 0..15)
+ 19
+ 1
+
+
+ BR2
+ Port x reset bit y (y =
+ 0..15)
+ 18
+ 1
+
+
+ BR1
+ Port x reset bit y (y =
+ 0..15)
+ 17
+ 1
+
+
+ BR0
+ Port x set bit y (y=
+ 0..15)
+ 16
+ 1
+
+
+ BS15
+ Port x set bit y (y=
+ 0..15)
+ 15
+ 1
+
+
+ BS14
+ Port x set bit y (y=
+ 0..15)
+ 14
+ 1
+
+
+ BS13
+ Port x set bit y (y=
+ 0..15)
+ 13
+ 1
+
+
+ BS12
+ Port x set bit y (y=
+ 0..15)
+ 12
+ 1
+
+
+ BS11
+ Port x set bit y (y=
+ 0..15)
+ 11
+ 1
+
+
+ BS10
+ Port x set bit y (y=
+ 0..15)
+ 10
+ 1
+
+
+ BS9
+ Port x set bit y (y=
+ 0..15)
+ 9
+ 1
+
+
+ BS8
+ Port x set bit y (y=
+ 0..15)
+ 8
+ 1
+
+
+ BS7
+ Port x set bit y (y=
+ 0..15)
+ 7
+ 1
+
+
+ BS6
+ Port x set bit y (y=
+ 0..15)
+ 6
+ 1
+
+
+ BS5
+ Port x set bit y (y=
+ 0..15)
+ 5
+ 1
+
+
+ BS4
+ Port x set bit y (y=
+ 0..15)
+ 4
+ 1
+
+
+ BS3
+ Port x set bit y (y=
+ 0..15)
+ 3
+ 1
+
+
+ BS2
+ Port x set bit y (y=
+ 0..15)
+ 2
+ 1
+
+
+ BS1
+ Port x set bit y (y=
+ 0..15)
+ 1
+ 1
+
+
+ BS0
+ Port x set bit y (y=
+ 0..15)
+ 0
+ 1
+
+
+
+
+ LCKR
+ LCKR
+ GPIO port configuration lock
+ register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LCKK
+ Port x lock bit y (y=
+ 0..15)
+ 16
+ 1
+
+
+ LCK15
+ Port x lock bit y (y=
+ 0..15)
+ 15
+ 1
+
+
+ LCK14
+ Port x lock bit y (y=
+ 0..15)
+ 14
+ 1
+
+
+ LCK13
+ Port x lock bit y (y=
+ 0..15)
+ 13
+ 1
+
+
+ LCK12
+ Port x lock bit y (y=
+ 0..15)
+ 12
+ 1
+
+
+ LCK11
+ Port x lock bit y (y=
+ 0..15)
+ 11
+ 1
+
+
+ LCK10
+ Port x lock bit y (y=
+ 0..15)
+ 10
+ 1
+
+
+ LCK9
+ Port x lock bit y (y=
+ 0..15)
+ 9
+ 1
+
+
+ LCK8
+ Port x lock bit y (y=
+ 0..15)
+ 8
+ 1
+
+
+ LCK7
+ Port x lock bit y (y=
+ 0..15)
+ 7
+ 1
+
+
+ LCK6
+ Port x lock bit y (y=
+ 0..15)
+ 6
+ 1
+
+
+ LCK5
+ Port x lock bit y (y=
+ 0..15)
+ 5
+ 1
+
+
+ LCK4
+ Port x lock bit y (y=
+ 0..15)
+ 4
+ 1
+
+
+ LCK3
+ Port x lock bit y (y=
+ 0..15)
+ 3
+ 1
+
+
+ LCK2
+ Port x lock bit y (y=
+ 0..15)
+ 2
+ 1
+
+
+ LCK1
+ Port x lock bit y (y=
+ 0..15)
+ 1
+ 1
+
+
+ LCK0
+ Port x lock bit y (y=
+ 0..15)
+ 0
+ 1
+
+
+
+
+ AFRL
+ AFRL
+ GPIO alternate function low
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AFSEL7
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 28
+ 4
+
+
+ AFSEL6
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 24
+ 4
+
+
+ AFSEL5
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 20
+ 4
+
+
+ AFSEL4
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 16
+ 4
+
+
+ AFSEL3
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 12
+ 4
+
+
+ AFSEL2
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 8
+ 4
+
+
+ AFSEL1
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 4
+ 4
+
+
+ AFSEL0
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 0
+ 4
+
+
+
+
+ AFRH
+ AFRH
+ GPIO alternate function high
+ register
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AFSEL15
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 28
+ 4
+
+
+ AFSEL14
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 24
+ 4
+
+
+ AFSEL13
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 20
+ 4
+
+
+ AFSEL12
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 16
+ 4
+
+
+ AFSEL11
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 12
+ 4
+
+
+ AFSEL10
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 8
+ 4
+
+
+ AFSEL9
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 4
+ 4
+
+
+ AFSEL8
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 0
+ 4
+
+
+
+
+ BRR
+ BRR
+ port bit reset register
+ 0x28
+ 0x20
+ write-only
+ 0x00000000
+
+
+ BR0
+ Port Reset bit
+ 0
+ 1
+
+
+ BR1
+ Port Reset bit
+ 1
+ 1
+
+
+ BR2
+ Port Reset bit
+ 2
+ 1
+
+
+ BR3
+ Port Reset bit
+ 3
+ 1
+
+
+ BR4
+ Port Reset bit
+ 4
+ 1
+
+
+ BR5
+ Port Reset bit
+ 5
+ 1
+
+
+ BR6
+ Port Reset bit
+ 6
+ 1
+
+
+ BR7
+ Port Reset bit
+ 7
+ 1
+
+
+ BR8
+ Port Reset bit
+ 8
+ 1
+
+
+ BR9
+ Port Reset bit
+ 9
+ 1
+
+
+ BR10
+ Port Reset bit
+ 10
+ 1
+
+
+ BR11
+ Port Reset bit
+ 11
+ 1
+
+
+ BR12
+ Port Reset bit
+ 12
+ 1
+
+
+ BR13
+ Port Reset bit
+ 13
+ 1
+
+
+ BR14
+ Port Reset bit
+ 14
+ 1
+
+
+ BR15
+ Port Reset bit
+ 15
+ 1
+
+
+
+
+
+
+ GPIOB
+ General-purpose I/Os
+ GPIO
+ 0x50000400
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ MODER
+ MODER
+ GPIO port mode register
+ 0x0
+ 0x20
+ read-write
+ 0xFFFFFFFF
+
+
+ MODER15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ MODER14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ MODER13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ MODER12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ MODER11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ MODER10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ MODER9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ MODER8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ MODER7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ MODER6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ MODER5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ MODER4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ MODER3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ MODER2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ MODER1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ MODER0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ OTYPER
+ OTYPER
+ GPIO port output type register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OT15
+ Port x configuration bits (y =
+ 0..15)
+ 15
+ 1
+
+
+ OT14
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 1
+
+
+ OT13
+ Port x configuration bits (y =
+ 0..15)
+ 13
+ 1
+
+
+ OT12
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 1
+
+
+ OT11
+ Port x configuration bits (y =
+ 0..15)
+ 11
+ 1
+
+
+ OT10
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 1
+
+
+ OT9
+ Port x configuration bits (y =
+ 0..15)
+ 9
+ 1
+
+
+ OT8
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 1
+
+
+ OT7
+ Port x configuration bits (y =
+ 0..15)
+ 7
+ 1
+
+
+ OT6
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 1
+
+
+ OT5
+ Port x configuration bits (y =
+ 0..15)
+ 5
+ 1
+
+
+ OT4
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 1
+
+
+ OT3
+ Port x configuration bits (y =
+ 0..15)
+ 3
+ 1
+
+
+ OT2
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 1
+
+
+ OT1
+ Port x configuration bits (y =
+ 0..15)
+ 1
+ 1
+
+
+ OT0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ OSPEEDR
+ OSPEEDR
+ GPIO port output speed
+ register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OSPEEDR15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ OSPEEDR14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ OSPEEDR13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ OSPEEDR12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ OSPEEDR11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ OSPEEDR10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ OSPEEDR9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ OSPEEDR8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ OSPEEDR7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ OSPEEDR6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ OSPEEDR5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ OSPEEDR4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ OSPEEDR3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ OSPEEDR2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ OSPEEDR1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ OSPEEDR0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ PUPDR
+ PUPDR
+ GPIO port pull-up/pull-down
+ register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PUPDR15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ PUPDR14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ PUPDR13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ PUPDR12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ PUPDR11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ PUPDR10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ PUPDR9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ PUPDR8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ PUPDR7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ PUPDR6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ PUPDR5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ PUPDR4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ PUPDR3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ PUPDR2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ PUPDR1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ PUPDR0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ IDR
+ IDR
+ GPIO port input data register
+ 0x10
+ 0x20
+ read-only
+ 0x00000000
+
+
+ IDR15
+ Port input data (y =
+ 0..15)
+ 15
+ 1
+
+
+ IDR14
+ Port input data (y =
+ 0..15)
+ 14
+ 1
+
+
+ IDR13
+ Port input data (y =
+ 0..15)
+ 13
+ 1
+
+
+ IDR12
+ Port input data (y =
+ 0..15)
+ 12
+ 1
+
+
+ IDR11
+ Port input data (y =
+ 0..15)
+ 11
+ 1
+
+
+ IDR10
+ Port input data (y =
+ 0..15)
+ 10
+ 1
+
+
+ IDR9
+ Port input data (y =
+ 0..15)
+ 9
+ 1
+
+
+ IDR8
+ Port input data (y =
+ 0..15)
+ 8
+ 1
+
+
+ IDR7
+ Port input data (y =
+ 0..15)
+ 7
+ 1
+
+
+ IDR6
+ Port input data (y =
+ 0..15)
+ 6
+ 1
+
+
+ IDR5
+ Port input data (y =
+ 0..15)
+ 5
+ 1
+
+
+ IDR4
+ Port input data (y =
+ 0..15)
+ 4
+ 1
+
+
+ IDR3
+ Port input data (y =
+ 0..15)
+ 3
+ 1
+
+
+ IDR2
+ Port input data (y =
+ 0..15)
+ 2
+ 1
+
+
+ IDR1
+ Port input data (y =
+ 0..15)
+ 1
+ 1
+
+
+ IDR0
+ Port input data (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ ODR
+ ODR
+ GPIO port output data register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ODR15
+ Port output data (y =
+ 0..15)
+ 15
+ 1
+
+
+ ODR14
+ Port output data (y =
+ 0..15)
+ 14
+ 1
+
+
+ ODR13
+ Port output data (y =
+ 0..15)
+ 13
+ 1
+
+
+ ODR12
+ Port output data (y =
+ 0..15)
+ 12
+ 1
+
+
+ ODR11
+ Port output data (y =
+ 0..15)
+ 11
+ 1
+
+
+ ODR10
+ Port output data (y =
+ 0..15)
+ 10
+ 1
+
+
+ ODR9
+ Port output data (y =
+ 0..15)
+ 9
+ 1
+
+
+ ODR8
+ Port output data (y =
+ 0..15)
+ 8
+ 1
+
+
+ ODR7
+ Port output data (y =
+ 0..15)
+ 7
+ 1
+
+
+ ODR6
+ Port output data (y =
+ 0..15)
+ 6
+ 1
+
+
+ ODR5
+ Port output data (y =
+ 0..15)
+ 5
+ 1
+
+
+ ODR4
+ Port output data (y =
+ 0..15)
+ 4
+ 1
+
+
+ ODR3
+ Port output data (y =
+ 0..15)
+ 3
+ 1
+
+
+ ODR2
+ Port output data (y =
+ 0..15)
+ 2
+ 1
+
+
+ ODR1
+ Port output data (y =
+ 0..15)
+ 1
+ 1
+
+
+ ODR0
+ Port output data (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ BSRR
+ BSRR
+ GPIO port bit set/reset
+ register
+ 0x18
+ 0x20
+ write-only
+ 0x00000000
+
+
+ BR15
+ Port x reset bit y (y =
+ 0..15)
+ 31
+ 1
+
+
+ BR14
+ Port x reset bit y (y =
+ 0..15)
+ 30
+ 1
+
+
+ BR13
+ Port x reset bit y (y =
+ 0..15)
+ 29
+ 1
+
+
+ BR12
+ Port x reset bit y (y =
+ 0..15)
+ 28
+ 1
+
+
+ BR11
+ Port x reset bit y (y =
+ 0..15)
+ 27
+ 1
+
+
+ BR10
+ Port x reset bit y (y =
+ 0..15)
+ 26
+ 1
+
+
+ BR9
+ Port x reset bit y (y =
+ 0..15)
+ 25
+ 1
+
+
+ BR8
+ Port x reset bit y (y =
+ 0..15)
+ 24
+ 1
+
+
+ BR7
+ Port x reset bit y (y =
+ 0..15)
+ 23
+ 1
+
+
+ BR6
+ Port x reset bit y (y =
+ 0..15)
+ 22
+ 1
+
+
+ BR5
+ Port x reset bit y (y =
+ 0..15)
+ 21
+ 1
+
+
+ BR4
+ Port x reset bit y (y =
+ 0..15)
+ 20
+ 1
+
+
+ BR3
+ Port x reset bit y (y =
+ 0..15)
+ 19
+ 1
+
+
+ BR2
+ Port x reset bit y (y =
+ 0..15)
+ 18
+ 1
+
+
+ BR1
+ Port x reset bit y (y =
+ 0..15)
+ 17
+ 1
+
+
+ BR0
+ Port x set bit y (y=
+ 0..15)
+ 16
+ 1
+
+
+ BS15
+ Port x set bit y (y=
+ 0..15)
+ 15
+ 1
+
+
+ BS14
+ Port x set bit y (y=
+ 0..15)
+ 14
+ 1
+
+
+ BS13
+ Port x set bit y (y=
+ 0..15)
+ 13
+ 1
+
+
+ BS12
+ Port x set bit y (y=
+ 0..15)
+ 12
+ 1
+
+
+ BS11
+ Port x set bit y (y=
+ 0..15)
+ 11
+ 1
+
+
+ BS10
+ Port x set bit y (y=
+ 0..15)
+ 10
+ 1
+
+
+ BS9
+ Port x set bit y (y=
+ 0..15)
+ 9
+ 1
+
+
+ BS8
+ Port x set bit y (y=
+ 0..15)
+ 8
+ 1
+
+
+ BS7
+ Port x set bit y (y=
+ 0..15)
+ 7
+ 1
+
+
+ BS6
+ Port x set bit y (y=
+ 0..15)
+ 6
+ 1
+
+
+ BS5
+ Port x set bit y (y=
+ 0..15)
+ 5
+ 1
+
+
+ BS4
+ Port x set bit y (y=
+ 0..15)
+ 4
+ 1
+
+
+ BS3
+ Port x set bit y (y=
+ 0..15)
+ 3
+ 1
+
+
+ BS2
+ Port x set bit y (y=
+ 0..15)
+ 2
+ 1
+
+
+ BS1
+ Port x set bit y (y=
+ 0..15)
+ 1
+ 1
+
+
+ BS0
+ Port x set bit y (y=
+ 0..15)
+ 0
+ 1
+
+
+
+
+ LCKR
+ LCKR
+ GPIO port configuration lock
+ register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LCKK
+ Port x lock bit y (y=
+ 0..15)
+ 16
+ 1
+
+
+ LCK15
+ Port x lock bit y (y=
+ 0..15)
+ 15
+ 1
+
+
+ LCK14
+ Port x lock bit y (y=
+ 0..15)
+ 14
+ 1
+
+
+ LCK13
+ Port x lock bit y (y=
+ 0..15)
+ 13
+ 1
+
+
+ LCK12
+ Port x lock bit y (y=
+ 0..15)
+ 12
+ 1
+
+
+ LCK11
+ Port x lock bit y (y=
+ 0..15)
+ 11
+ 1
+
+
+ LCK10
+ Port x lock bit y (y=
+ 0..15)
+ 10
+ 1
+
+
+ LCK9
+ Port x lock bit y (y=
+ 0..15)
+ 9
+ 1
+
+
+ LCK8
+ Port x lock bit y (y=
+ 0..15)
+ 8
+ 1
+
+
+ LCK7
+ Port x lock bit y (y=
+ 0..15)
+ 7
+ 1
+
+
+ LCK6
+ Port x lock bit y (y=
+ 0..15)
+ 6
+ 1
+
+
+ LCK5
+ Port x lock bit y (y=
+ 0..15)
+ 5
+ 1
+
+
+ LCK4
+ Port x lock bit y (y=
+ 0..15)
+ 4
+ 1
+
+
+ LCK3
+ Port x lock bit y (y=
+ 0..15)
+ 3
+ 1
+
+
+ LCK2
+ Port x lock bit y (y=
+ 0..15)
+ 2
+ 1
+
+
+ LCK1
+ Port x lock bit y (y=
+ 0..15)
+ 1
+ 1
+
+
+ LCK0
+ Port x lock bit y (y=
+ 0..15)
+ 0
+ 1
+
+
+
+
+ AFRL
+ AFRL
+ GPIO alternate function low
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AFSEL7
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 28
+ 4
+
+
+ AFSEL6
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 24
+ 4
+
+
+ AFSEL5
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 20
+ 4
+
+
+ AFSEL4
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 16
+ 4
+
+
+ AFSEL3
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 12
+ 4
+
+
+ AFSEL2
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 8
+ 4
+
+
+ AFSEL1
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 4
+ 4
+
+
+ AFSEL0
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 0
+ 4
+
+
+
+
+ AFRH
+ AFRH
+ GPIO alternate function high
+ register
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AFSEL15
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 28
+ 4
+
+
+ AFSEL14
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 24
+ 4
+
+
+ AFSEL13
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 20
+ 4
+
+
+ AFSEL12
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 16
+ 4
+
+
+ AFSEL11
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 12
+ 4
+
+
+ AFSEL10
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 8
+ 4
+
+
+ AFSEL9
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 4
+ 4
+
+
+ AFSEL8
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 0
+ 4
+
+
+
+
+ BRR
+ BRR
+ port bit reset register
+ 0x28
+ 0x20
+ write-only
+ 0x00000000
+
+
+ BR0
+ Port Reset bit
+ 0
+ 1
+
+
+ BR1
+ Port Reset bit
+ 1
+ 1
+
+
+ BR2
+ Port Reset bit
+ 2
+ 1
+
+
+ BR3
+ Port Reset bit
+ 3
+ 1
+
+
+ BR4
+ Port Reset bit
+ 4
+ 1
+
+
+ BR5
+ Port Reset bit
+ 5
+ 1
+
+
+ BR6
+ Port Reset bit
+ 6
+ 1
+
+
+ BR7
+ Port Reset bit
+ 7
+ 1
+
+
+ BR8
+ Port Reset bit
+ 8
+ 1
+
+
+ BR9
+ Port Reset bit
+ 9
+ 1
+
+
+ BR10
+ Port Reset bit
+ 10
+ 1
+
+
+ BR11
+ Port Reset bit
+ 11
+ 1
+
+
+ BR12
+ Port Reset bit
+ 12
+ 1
+
+
+ BR13
+ Port Reset bit
+ 13
+ 1
+
+
+ BR14
+ Port Reset bit
+ 14
+ 1
+
+
+ BR15
+ Port Reset bit
+ 15
+ 1
+
+
+
+
+
+
+ GPIOC
+ 0x50000800
+
+
+ GPIOD
+ 0x50000C00
+
+
+ GPIOF
+ 0x50001400
+
+
+ CRC
+ Cyclic redundancy check calculation
+ unit
+ CRC
+ 0x40023000
+
+ 0x0
+ 0x400
+ registers
+
+
+ CEC
+ CEC global interrupt
+ 30
+
+
+
+ DR
+ DR
+ Data register
+ 0x0
+ 0x20
+ read-write
+ 0xFFFFFFFF
+
+
+ DR
+ Data register bits
+ 0
+ 32
+
+
+
+
+ IDR
+ IDR
+ Independent data register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IDR
+ General-purpose 32-bit data register
+ bits
+ 0
+ 32
+
+
+
+
+ CR
+ CR
+ Control register
+ 0x8
+ 0x20
+ 0x00000000
+
+
+ REV_OUT
+ Reverse output data
+ 7
+ 1
+ read-write
+
+
+ REV_IN
+ Reverse input data
+ 5
+ 2
+ read-write
+
+
+ POLYSIZE
+ Polynomial size
+ 3
+ 2
+ read-write
+
+
+ RESET
+ RESET bit
+ 0
+ 1
+ write-only
+
+
+
+
+ INIT
+ INIT
+ Initial CRC value
+ 0x10
+ 0x20
+ read-write
+ 0xFFFFFFFF
+
+
+ CRC_INIT
+ Programmable initial CRC
+ value
+ 0
+ 32
+
+
+
+
+ POL
+ POL
+ polynomial
+ 0x14
+ 0x20
+ read-write
+ 0x04C11DB7
+
+
+ POL
+ Programmable polynomial
+ 0
+ 32
+
+
+
+
+
+
+ EXTI
+ External interrupt/event
+ controller
+ EXTI
+ 0x40021800
+
+ 0x0
+ 0x400
+ registers
+
+
+ EXTI0_1
+ EXTI line 0 & 1 interrupt
+ 5
+
+
+ EXTI2_3
+ EXTI line 2 & 3 interrupt
+ 6
+
+
+ EXTI4_15
+ EXTI line 4 to 15 interrupt
+ 7
+
+
+
+ RTSR1
+ RTSR1
+ EXTI rising trigger selection
+ register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TR0
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 0
+ 1
+ TR0 read-write Disabled Rising edge trigger is disabled 0 Enabled Rising edge trigger is enabled 1
+
+ TR1
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 1
+ 1
+
+
+ TR2
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 2
+ 1
+
+
+ TR3
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 3
+ 1
+
+
+ TR4
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 4
+ 1
+
+
+ TR5
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 5
+ 1
+
+
+ TR6
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 6
+ 1
+
+
+ TR7
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 7
+ 1
+
+
+ TR8
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 8
+ 1
+
+
+ TR9
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 9
+ 1
+
+
+ TR10
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 10
+ 1
+
+
+ TR11
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 11
+ 1
+
+
+ TR12
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 12
+ 1
+
+
+ TR13
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 13
+ 1
+
+
+ TR14
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 14
+ 1
+
+
+ TR15
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 15
+ 1
+
+
+ TR16
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 16
+ 1
+
+
+ TR17
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 17
+ 1
+
+
+ TR18
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 18
+ 1
+
+
+
+
+ FTSR1
+ FTSR1
+ EXTI falling trigger selection
+ register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TR0
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 0
+ 1
+ TR0 read-write Disabled Falling edge trigger is disabled 0 Enabled Falling edge trigger is enabled 1
+
+ TR1
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 1
+ 1
+
+
+ TR2
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 2
+ 1
+
+
+ TR3
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 3
+ 1
+
+
+ TR4
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 4
+ 1
+
+
+ TR5
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 5
+ 1
+
+
+ TR6
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 6
+ 1
+
+
+ TR7
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 7
+ 1
+
+
+ TR8
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 8
+ 1
+
+
+ TR9
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 9
+ 1
+
+
+ TR10
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 10
+ 1
+
+
+ TR11
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 11
+ 1
+
+
+ TR12
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 12
+ 1
+
+
+ TR13
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 13
+ 1
+
+
+ TR14
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 14
+ 1
+
+
+ TR15
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 15
+ 1
+
+
+ TR16
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 16
+ 1
+
+
+ TR17
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 17
+ 1
+
+
+ TR18
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 18
+ 1
+
+
+
+
+ SWIER1
+ SWIER1
+ EXTI software interrupt event
+ register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SWIER0
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 0
+ 1
+ SWIER0W write Pend Generates an interrupt request 1
+
+ SWIER1
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 1
+ 1
+
+
+ SWIER2
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 2
+ 1
+
+
+ SWIER3
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 3
+ 1
+
+
+ SWIER4
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 4
+ 1
+
+
+ SWIER5
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 5
+ 1
+
+
+ SWIER6
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 6
+ 1
+
+
+ SWIER7
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 7
+ 1
+
+
+ SWIER8
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 8
+ 1
+
+
+ SWIER9
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 9
+ 1
+
+
+ SWIER10
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 10
+ 1
+
+
+ SWIER11
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 11
+ 1
+
+
+ SWIER12
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 12
+ 1
+
+
+ SWIER13
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 13
+ 1
+
+
+ SWIER14
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 14
+ 1
+
+
+ SWIER15
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 15
+ 1
+
+
+ SWIER16
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 16
+ 1
+
+
+ SWIER17
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 17
+ 1
+
+
+ SWIER18
+ Rising trigger event configuration bit
+ of Configurable Event input
+ 18
+ 1
+
+
+
+
+ RPR1
+ RPR1
+ EXTI rising edge pending
+ register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ RPIF0
+ configurable event inputs x rising edge
+ Pending bit.
+ 0
+ 1
+ RPIF0R read NotPending No trigger request occurred 0 Pending Selected trigger request occurred 1 RPIF0W write Clear Clears pending bit 1
+
+ RPIF1
+ configurable event inputs x rising edge
+ Pending bit.
+ 1
+ 1
+
+
+ RPIF2
+ configurable event inputs x rising edge
+ Pending bit.
+ 2
+ 1
+
+
+ RPIF3
+ configurable event inputs x rising edge
+ Pending bit.
+ 3
+ 1
+
+
+ RPIF4
+ configurable event inputs x rising edge
+ Pending bit.
+ 4
+ 1
+
+
+ RPIF5
+ configurable event inputs x rising edge
+ Pending bit
+ 5
+ 1
+
+
+ RPIF6
+ configurable event inputs x rising edge
+ Pending bit.
+ 6
+ 1
+
+
+ RPIF7
+ configurable event inputs x rising edge
+ Pending bit.
+ 7
+ 1
+
+
+ RPIF8
+ configurable event inputs x rising edge
+ Pending bit.
+ 8
+ 1
+
+
+ RPIF9
+ configurable event inputs x rising edge
+ Pending bit.
+ 9
+ 1
+
+
+ RPIF10
+ configurable event inputs x rising edge
+ Pending bit.
+ 10
+ 1
+
+
+ RPIF11
+ configurable event inputs x rising edge
+ Pending bit.
+ 11
+ 1
+
+
+ RPIF12
+ configurable event inputs x rising edge
+ Pending bit.
+ 12
+ 1
+
+
+ RPIF13
+ configurable event inputs x rising edge
+ Pending bit.
+ 13
+ 1
+
+
+ RPIF14
+ configurable event inputs x rising edge
+ Pending bit.
+ 14
+ 1
+
+
+ RPIF15
+ configurable event inputs x rising edge
+ Pending bit.
+ 15
+ 1
+
+
+ RPIF16
+ configurable event inputs x rising edge
+ Pending bit.
+ 16
+ 1
+
+
+ RPIF17
+ configurable event inputs x rising edge
+ Pending bit.
+ 17
+ 1
+
+
+ RPIF18
+ configurable event inputs x rising edge
+ Pending bit.
+ 18
+ 1
+
+
+
+
+ FPR1
+ FPR1
+ EXTI falling edge pending
+ register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FPIF0
+ configurable event inputs x falling edge
+ pending bit.
+ 0
+ 1
+ FPIF0R read NotPending No trigger request occurred 0 Pending Selected trigger request occurred 1 FPIF0W write Clear Clears pending bit 1
+
+ FPIF1
+ configurable event inputs x falling edge
+ pending bit.
+ 1
+ 1
+
+
+ FPIF2
+ configurable event inputs x falling edge
+ pending bit.
+ 2
+ 1
+
+
+ FPIF3
+ configurable event inputs x falling edge
+ pending bit.
+ 3
+ 1
+
+
+ FPIF4
+ configurable event inputs x falling edge
+ pending bit.
+ 4
+ 1
+
+
+ FPIF5
+ configurable event inputs x falling edge
+ pending bit.
+ 5
+ 1
+
+
+ FPIF6
+ configurable event inputs x falling edge
+ pending bit.
+ 6
+ 1
+
+
+ FPIF7
+ configurable event inputs x falling edge
+ pending bit.
+ 7
+ 1
+
+
+ FPIF8
+ configurable event inputs x falling edge
+ pending bit.
+ 8
+ 1
+
+
+ FPIF9
+ configurable event inputs x falling edge
+ pending bit.
+ 9
+ 1
+
+
+ FPIF10
+ configurable event inputs x falling edge
+ pending bit.
+ 10
+ 1
+
+
+ FPIF11
+ configurable event inputs x falling edge
+ pending bit.
+ 11
+ 1
+
+
+ FPIF12
+ configurable event inputs x falling edge
+ pending bit.
+ 12
+ 1
+
+
+ FPIF13
+ configurable event inputs x falling edge
+ pending bit.
+ 13
+ 1
+
+
+ FPIF14
+ configurable event inputs x falling edge
+ pending bit.
+ 14
+ 1
+
+
+ FPIF15
+ configurable event inputs x falling edge
+ pending bit.
+ 15
+ 1
+
+
+ FPIF16
+ configurable event inputs x falling edge
+ pending bit.
+ 16
+ 1
+
+
+ FPIF17
+ configurable event inputs x falling edge
+ pending bit.
+ 17
+ 1
+
+
+ FPIF18
+ configurable event inputs x falling edge
+ pending bit.
+ 18
+ 1
+
+
+
+
+ EXTICR1
+ EXTICR1
+ EXTI external interrupt selection
+ register
+ 0x60
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EXTI0_7
+ GPIO port selection
+ 0
+ 8
+ EXTI0_7 read-write PA GPIO port A selected 0 PB GPIO port B selected 1 PC GPIO port C selected 2 PD GPIO port D selected 3 PF GPIO port F selected 5
+
+ EXTI8_15
+ GPIO port selection
+ 8
+ 8
+
+
+ EXTI16_23
+ GPIO port selection
+ 16
+ 8
+
+
+ EXTI24_31
+ GPIO port selection
+ 24
+ 8
+
+
+
+
+ EXTICR2
+ EXTICR2
+ EXTI external interrupt selection
+ register
+ 0x64
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EXTI0_7
+ GPIO port selection
+ 0
+ 8
+ EXTI0_7 read-write PA GPIO port A selected 0 PB GPIO port B selected 1 PC GPIO port C selected 2 PD GPIO port D selected 3 PF GPIO port F selected 5
+
+ EXTI8_15
+ GPIO port selection
+ 8
+ 8
+
+
+ EXTI16_23
+ GPIO port selection
+ 16
+ 8
+
+
+ EXTI24_31
+ GPIO port selection
+ 24
+ 8
+
+
+
+
+ EXTICR3
+ EXTICR3
+ EXTI external interrupt selection
+ register
+ 0x68
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EXTI0_7
+ GPIO port selection
+ 0
+ 8
+ EXTI0_7 read-write PA GPIO port A selected 0 PB GPIO port B selected 1 PC GPIO port C selected 2 PD GPIO port D selected 3 PF GPIO port F selected 5
+
+ EXTI8_15
+ GPIO port selection
+ 8
+ 8
+
+
+ EXTI16_23
+ GPIO port selection
+ 16
+ 8
+
+
+ EXTI24_31
+ GPIO port selection
+ 24
+ 8
+
+
+
+
+ EXTICR4
+ EXTICR4
+ EXTI external interrupt selection
+ register
+ 0x6C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EXTI0_7
+ GPIO port selection
+ 0
+ 8
+ EXTI0_7 read-write PA GPIO port A selected 0 PB GPIO port B selected 1 PC GPIO port C selected 2 PD GPIO port D selected 3 PF GPIO port F selected 5
+
+ EXTI8_15
+ GPIO port selection
+ 8
+ 8
+
+
+ EXTI16_23
+ GPIO port selection
+ 16
+ 8
+
+
+ EXTI24_31
+ GPIO port selection
+ 24
+ 8
+
+
+
+
+ IMR1
+ IMR1
+ EXTI CPU wakeup with interrupt mask
+ register
+ 0x80
+ 0x20
+ read-write
+ 0xFFF80000
+
+
+ IM0
+ CPU wakeup with interrupt mask on event
+ input
+ 0
+ 1
+ IM0 read-write Masked Interrupt request line is masked 0 Unmasked Interrupt request line is unmasked 1
+
+ IM1
+ CPU wakeup with interrupt mask on event
+ input
+ 1
+ 1
+
+
+ IM2
+ CPU wakeup with interrupt mask on event
+ input
+ 2
+ 1
+
+
+ IM3
+ CPU wakeup with interrupt mask on event
+ input
+ 3
+ 1
+
+
+ IM4
+ CPU wakeup with interrupt mask on event
+ input
+ 4
+ 1
+
+
+ IM5
+ CPU wakeup with interrupt mask on event
+ input
+ 5
+ 1
+
+
+ IM6
+ CPU wakeup with interrupt mask on event
+ input
+ 6
+ 1
+
+
+ IM7
+ CPU wakeup with interrupt mask on event
+ input
+ 7
+ 1
+
+
+ IM8
+ CPU wakeup with interrupt mask on event
+ input
+ 8
+ 1
+
+
+ IM9
+ CPU wakeup with interrupt mask on event
+ input
+ 9
+ 1
+
+
+ IM10
+ CPU wakeup with interrupt mask on event
+ input
+ 10
+ 1
+
+
+ IM11
+ CPU wakeup with interrupt mask on event
+ input
+ 11
+ 1
+
+
+ IM12
+ CPU wakeup with interrupt mask on event
+ input
+ 12
+ 1
+
+
+ IM13
+ CPU wakeup with interrupt mask on event
+ input
+ 13
+ 1
+
+
+ IM14
+ CPU wakeup with interrupt mask on event
+ input
+ 14
+ 1
+
+
+ IM15
+ CPU wakeup with interrupt mask on event
+ input
+ 15
+ 1
+
+
+ IM16
+ CPU wakeup with interrupt mask on event
+ input
+ 16
+ 1
+
+
+ IM17
+ CPU wakeup with interrupt mask on event
+ input
+ 17
+ 1
+
+
+ IM18
+ CPU wakeup with interrupt mask on event
+ input
+ 18
+ 1
+
+
+ IM19
+ CPU wakeup with interrupt mask on event
+ input
+ 19
+ 1
+
+
+ IM20
+ CPU wakeup with interrupt mask on event
+ input
+ 20
+ 1
+
+
+ IM21
+ CPU wakeup with interrupt mask on event
+ input
+ 21
+ 1
+
+
+ IM22
+ CPU wakeup with interrupt mask on event
+ input
+ 22
+ 1
+
+
+ IM23
+ CPU wakeup with interrupt mask on event
+ input
+ 23
+ 1
+
+
+ IM24
+ CPU wakeup with interrupt mask on event
+ input
+ 24
+ 1
+
+
+ IM25
+ CPU wakeup with interrupt mask on event
+ input
+ 25
+ 1
+
+
+ IM26
+ CPU wakeup with interrupt mask on event
+ input
+ 26
+ 1
+
+
+ IM27
+ CPU wakeup with interrupt mask on event
+ input
+ 27
+ 1
+
+
+ IM28
+ CPU wakeup with interrupt mask on event
+ input
+ 28
+ 1
+
+
+ IM29
+ CPU wakeup with interrupt mask on event
+ input
+ 29
+ 1
+
+
+ IM30
+ CPU wakeup with interrupt mask on event
+ input
+ 30
+ 1
+
+
+ IM31
+ CPU wakeup with interrupt mask on event
+ input
+ 31
+ 1
+
+
+
+
+ EMR1
+ EMR1
+ EXTI CPU wakeup with event mask
+ register
+ IMR1
+ 0x84
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EM0
+ CPU wakeup with event mask on event
+ input
+ 0
+ 1
+ EM0 read-write Masked Interrupt request line is masked 0 Unmasked Interrupt request line is unmasked 1
+
+ EM1
+ CPU wakeup with event mask on event
+ input
+ 1
+ 1
+
+
+ EM2
+ CPU wakeup with event mask on event
+ input
+ 2
+ 1
+
+
+ EM3
+ CPU wakeup with event mask on event
+ input
+ 3
+ 1
+
+
+ EM4
+ CPU wakeup with event mask on event
+ input
+ 4
+ 1
+
+
+ EM5
+ CPU wakeup with event mask on event
+ input
+ 5
+ 1
+
+
+ EM6
+ CPU wakeup with event mask on event
+ input
+ 6
+ 1
+
+
+ EM7
+ CPU wakeup with event mask on event
+ input
+ 7
+ 1
+
+
+ EM8
+ CPU wakeup with event mask on event
+ input
+ 8
+ 1
+
+
+ EM9
+ CPU wakeup with event mask on event
+ input
+ 9
+ 1
+
+
+ EM10
+ CPU wakeup with event mask on event
+ input
+ 10
+ 1
+
+
+ EM11
+ CPU wakeup with event mask on event
+ input
+ 11
+ 1
+
+
+ EM12
+ CPU wakeup with event mask on event
+ input
+ 12
+ 1
+
+
+ EM13
+ CPU wakeup with event mask on event
+ input
+ 13
+ 1
+
+
+ EM14
+ CPU wakeup with event mask on event
+ input
+ 14
+ 1
+
+
+ EM15
+ CPU wakeup with event mask on event
+ input
+ 15
+ 1
+
+
+ EM16
+ CPU wakeup with event mask on event
+ input
+ 16
+ 1
+
+
+ EM17
+ CPU wakeup with event mask on event
+ input
+ 17
+ 1
+
+
+ EM18
+ CPU wakeup with event mask on event
+ input
+ 18
+ 1
+
+
+ EM19
+ CPU wakeup with event mask on event
+ input
+ 19
+ 1
+
+
+ EM21
+ CPU wakeup with event mask on event
+ input
+ 21
+ 1
+
+
+ EM23
+ CPU wakeup with event mask on event
+ input
+ 23
+ 1
+
+
+ EM25
+ CPU wakeup with event mask on event
+ input
+ 25
+ 1
+
+
+ EM26
+ CPU wakeup with event mask on event
+ input
+ 26
+ 1
+
+
+ EM27
+ CPU wakeup with event mask on event
+ input
+ 27
+ 1
+
+
+ EM28
+ CPU wakeup with event mask on event
+ input
+ 28
+ 1
+
+
+ EM29
+ CPU wakeup with event mask on event
+ input
+ 29
+ 1
+
+
+ EM30
+ CPU wakeup with event mask on event
+ input
+ 30
+ 1
+
+
+ EM31
+ CPU wakeup with event mask on event
+ input
+ 31
+ 1
+
+
+
+
+ IMR2
+ IMR2
+ EXTI CPU wakeup with interrupt mask
+ register
+ 0x90
+ 0x20
+ read-write
+ 0xFFFFFFFF
+
+
+ IM32
+ CPU wakeup with interrupt mask on event
+ input
+ 0
+ 1
+ IM32 read-write Masked Interrupt request line is masked 0 Unmasked Interrupt request line is unmasked 1
+
+ IM33
+ CPU wakeup with interrupt mask on event
+ input
+ 1
+ 1
+
+
+
+
+ EMR2
+ EMR2
+ EXTI CPU wakeup with event mask
+ register
+ 0x94
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EM32
+ CPU wakeup with event mask on event
+ input
+ 0
+ 1
+ EM32 read-write Masked Interrupt request line is masked 0 Unmasked Interrupt request line is unmasked 1
+
+ EM33
+ CPU wakeup with event mask on event
+ input
+ 1
+ 1
+
+
+
+
+ HWCFGR7
+ HWCFGR7
+ Hardware configuration
+ registers
+ 0x3D8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CPUEVENT
+ HW configuration CPU event
+ generation
+ 0
+ 32
+
+
+
+
+ HWCFGR6
+ HWCFGR6
+ Hardware configuration
+ registers
+ 0x3DC
+ 0x20
+ read-write
+ 0x00000003
+
+
+ CPUEVENT
+ HW configuration CPU event
+ generation
+ 0
+ 32
+
+
+
+
+ HWCFGR5
+ HWCFGR5
+ Hardware configuration
+ registers
+ 0x3E0
+ 0x20
+ read-write
+ 0xFEAFFFFF
+
+
+ CPUEVENT
+ HW configuration CPU event
+ generation
+ 0
+ 32
+
+
+
+
+ HWCFGR4
+ HWCFGR4
+ Hardware configuration
+ registers
+ 0x3E4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EVENT_TRG
+ HW configuration event trigger
+ type
+ 0
+ 32
+
+
+
+
+ HWCFGR3
+ HWCFGR3
+ Hardware configuration
+ registers
+ 0x3E8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EVENT_TRG
+ HW configuration event trigger
+ type
+ 0
+ 32
+
+
+
+
+ HWCFGR2
+ HWCFGR2
+ Hardware configuration
+ registers
+ 0x3EC
+ 0x20
+ read-write
+ 0x0007FFFF
+
+
+ EVENT_TRG
+ HW configuration event trigger
+ type
+ 0
+ 32
+
+
+
+
+ HWCFGR1
+ HWCFGR1
+ Hardware configuration
+ registers
+ 0x3F0
+ 0x20
+ read-only
+ 0x00051021
+
+
+ NBIOPORT
+ HW configuration of number of IO
+ ports
+ 16
+ 8
+
+
+ CPUEVTEN
+ HW configuration of CPU event output
+ enable
+ 12
+ 4
+
+
+ NBCPUS
+ configuration number of
+ CPUs
+ 8
+ 4
+
+
+ NBEVENTS
+ configuration number of
+ event
+ 0
+ 8
+
+
+
+
+
+
+ TIM15
+ General purpose timers
+ TIM
+ 0x40014000
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM15
+ Timer 15 global interrupt
+ 20
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CEN
+ Counter enable
+Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.
+ 0
+ 1
+ read-write
+
+
+ B_0x0
+ Counter disabled
+ 0x0
+
+
+ B_0x1
+ Counter enabled
+ 0x1
+
+
+
+
+ UDIS
+ Update disable
+This bit is set and cleared by software to enable/disable UEV event generation.
+Counter overflow/underflow
+Setting the UG bit
+Update generation through the slave mode controller
+Buffered registers are then loaded with their preload values.
+ 1
+ 1
+ read-write
+
+
+ B_0x0
+ UEV enabled. The Update (UEV) event is generated by one of the following events:
+ 0x0
+
+
+ B_0x1
+ UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.
+ 0x1
+
+
+
+
+ URS
+ Update request source
+This bit is set and cleared by software to select the UEV event sources.
+Counter overflow/underflow
+Setting the UG bit
+Update generation through the slave mode controller
+ 2
+ 1
+ read-write
+
+
+ B_0x0
+ Any of the following events generate an update interrupt if enabled. These events can be:
+ 0x0
+
+
+ B_0x1
+ Only counter overflow/underflow generates an update interrupt if enabled
+ 0x1
+
+
+
+
+ OPM
+ One-pulse mode
+ 3
+ 1
+ read-write
+
+
+ B_0x0
+ Counter is not stopped at update event
+ 0x0
+
+
+ B_0x1
+ Counter stops counting at the next update event (clearing the bit CEN)
+ 0x1
+
+
+
+
+ ARPE
+ Auto-reload preload enable
+ 7
+ 1
+ read-write
+
+
+ B_0x0
+ TIMx_ARR register is not buffered
+ 0x0
+
+
+ B_0x1
+ TIMx_ARR register is buffered
+ 0x1
+
+
+
+
+ CKD
+ Clock division
+This bitfield indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS) used by the dead-time generators and the digital filters (TIx)
+ 8
+ 2
+ read-write
+
+
+ B_0x0
+ tDTS = tCK_INT
+ 0x0
+
+
+ B_0x1
+ tDTS = 2*tCK_INT
+ 0x1
+
+
+ B_0x2
+ tDTS = 4*tCK_INT
+ 0x2
+
+
+ B_0x3
+ Reserved, do not program this value
+ 0x3
+
+
+
+
+ UIFREMAP
+ UIF status bit remapping
+ 11
+ 1
+ read-write
+
+
+ B_0x0
+ No remapping. UIF status bit is not copied to TIMx_CNT register bit 31.
+ 0x0
+
+
+ B_0x1
+ Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31.
+ 0x1
+
+
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ CCPC
+ Capture/compare preloaded control
+Note: This bit acts only on channels that have a complementary output.
+ 0
+ 1
+ read-write
+
+
+ B_0x0
+ CCxE, CCxNE and OCxM bits are not preloaded
+ 0x0
+
+
+ B_0x1
+ CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit).
+ 0x1
+
+
+
+
+ CCUS
+ Capture/compare control update selection
+Note: This bit acts only on channels that have a complementary output.
+ 2
+ 1
+ read-write
+
+
+ B_0x0
+ When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only.
+ 0x0
+
+
+ B_0x1
+ When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI.
+ 0x1
+
+
+
+
+ CCDS
+ Capture/compare DMA selection
+ 3
+ 1
+ read-write
+
+
+ B_0x0
+ CCx DMA request sent when CCx event occurs
+ 0x0
+
+
+ B_0x1
+ CCx DMA requests sent when update event occurs
+ 0x1
+
+
+
+
+ MMS
+ Master mode selection
+These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows:
+ 4
+ 3
+ read-write
+
+
+ B_0x0
+ Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.
+ 0x0
+
+
+ B_0x1
+ Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic AND between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register).
+ 0x1
+
+
+ B_0x2
+ Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.
+ 0x2
+
+
+ B_0x3
+ Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO).
+ 0x3
+
+
+ B_0x4
+ Compare - OC1REFC signal is used as trigger output (TRGO).
+ 0x4
+
+
+ B_0x5
+ Compare - OC2REFC signal is used as trigger output (TRGO).
+ 0x5
+
+
+
+
+ TI1S
+ TI1 selection
+ 7
+ 1
+ read-write
+
+
+ B_0x0
+ The TIMx_CH1 pin is connected to TI1 input
+ 0x0
+
+
+ B_0x1
+ The TIMx_CH1, CH2 pins are connected to the TI1 input (XOR combination)
+ 0x1
+
+
+
+
+ OIS1
+ Output Idle state 1 (OC1 output)
+Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register).
+ 8
+ 1
+ read-write
+
+
+ B_0x0
+ OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
+ 0x0
+
+
+ B_0x1
+ OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
+ 0x1
+
+
+
+
+ OIS1N
+ Output Idle state 1 (OC1N output)
+Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIM15_BDTR register).
+ 9
+ 1
+ read-write
+
+
+ B_0x0
+ OC1N=0 after a dead-time when MOE=0
+ 0x0
+
+
+ B_0x1
+ OC1N=1 after a dead-time when MOE=0
+ 0x1
+
+
+
+
+ OIS2
+ Output idle state 2 (OC2 output)
+Note: This bit cannot be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in the TIM15_BDTR register).
+ 10
+ 1
+ read-write
+
+
+ B_0x0
+ OC2=0 when MOE=0
+ 0x0
+
+
+ B_0x1
+ OC2=1 when MOE=0
+ 0x1
+
+
+
+
+
+
+ SMCR
+ SMCR
+ slave mode control register
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ SMS1
+ Slave mode selection
+When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description.
+Other codes: reserved.
+Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=’00100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal.
+Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
+ 0
+ 3
+ read-write
+
+
+ TS1
+ Trigger selection
+This bit field selects the trigger input to be used to synchronize the counter.
+Other: Reserved
+See for more details on ITRx meaning for each Timer.
+Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
+ 4
+ 3
+ read-write
+
+
+ MSM
+ Master/slave mode
+ 7
+ 1
+ read-write
+
+
+ B_0x0
+ No action
+ 0x0
+
+
+ B_0x1
+ The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
+ 0x1
+
+
+
+
+ SMS2
+ Slave mode selection
+When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description.
+Other codes: reserved.
+Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=’00100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal.
+Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
+ 16
+ 1
+ read-write
+
+
+ TS2
+ Trigger selection
+This bit field selects the trigger input to be used to synchronize the counter.
+Other: Reserved
+See for more details on ITRx meaning for each Timer.
+Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition.
+ 20
+ 2
+ read-write
+
+
+
+
+ DIER
+ DIER
+ DMA/Interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ UIE
+ Update interrupt enable
+ 0
+ 1
+ read-write
+
+
+ B_0x0
+ Update interrupt disabled
+ 0x0
+
+
+ B_0x1
+ Update interrupt enabled
+ 0x1
+
+
+
+
+ CC1IE
+ Capture/Compare 1 interrupt enable
+ 1
+ 1
+ read-write
+
+
+ B_0x0
+ CC1 interrupt disabled
+ 0x0
+
+
+ B_0x1
+ CC1 interrupt enabled
+ 0x1
+
+
+
+
+ CC2IE
+ Capture/Compare 2 interrupt enable
+ 2
+ 1
+ read-write
+
+
+ B_0x0
+ CC2 interrupt disabled
+ 0x0
+
+
+ B_0x1
+ CC2 interrupt enabled
+ 0x1
+
+
+
+
+ COMIE
+ COM interrupt enable
+ 5
+ 1
+ read-write
+
+
+ B_0x0
+ COM interrupt disabled
+ 0x0
+
+
+ B_0x1
+ COM interrupt enabled
+ 0x1
+
+
+
+
+ TIE
+ Trigger interrupt enable
+ 6
+ 1
+ read-write
+
+
+ B_0x0
+ Trigger interrupt disabled
+ 0x0
+
+
+ B_0x1
+ Trigger interrupt enabled
+ 0x1
+
+
+
+
+ BIE
+ Break interrupt enable
+ 7
+ 1
+ read-write
+
+
+ B_0x0
+ Break interrupt disabled
+ 0x0
+
+
+ B_0x1
+ Break interrupt enabled
+ 0x1
+
+
+
+
+ UDE
+ Update DMA request enable
+ 8
+ 1
+ read-write
+
+
+ B_0x0
+ Update DMA request disabled
+ 0x0
+
+
+ B_0x1
+ Update DMA request enabled
+ 0x1
+
+
+
+
+ CC1DE
+ Capture/Compare 1 DMA request enable
+ 9
+ 1
+ read-write
+
+
+ B_0x0
+ CC1 DMA request disabled
+ 0x0
+
+
+ B_0x1
+ CC1 DMA request enabled
+ 0x1
+
+
+
+
+ CC2DE
+ Capture/Compare 2 DMA request enable
+ 10
+ 1
+ read-write
+
+
+ B_0x0
+ CC2 DMA request disabled
+ 0x0
+
+
+ B_0x1
+ CC2 DMA request enabled
+ 0x1
+
+
+
+
+ COMDE
+ COM DMA request enable
+ 13
+ 1
+ read-write
+
+
+ B_0x0
+ COM DMA request disabled
+ 0x0
+
+
+ B_0x1
+ COM DMA request enabled
+ 0x1
+
+
+
+
+ TDE
+ Trigger DMA request enable
+ 14
+ 1
+ read-write
+
+
+ B_0x0
+ Trigger DMA request disabled
+ 0x0
+
+
+ B_0x1
+ Trigger DMA request enabled
+ 0x1
+
+
+
+
+
+
+ SR
+ SR
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ UIF
+ Update interrupt flag
+This bit is set by hardware on an update event. It is cleared by software.
+At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register.
+When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register.
+When CNT is reinitialized by a trigger event (refer to control register (TIM15_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register.
+ 0
+ 1
+ read-write
+
+
+ B_0x0
+ No update occurred.
+ 0x0
+
+
+ B_0x1
+ Update interrupt pending. This bit is set by hardware when the registers are updated:
+ 0x1
+
+
+
+
+ CC1IF
+ Capture/Compare 1 interrupt flag
+This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only).
+If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the content of TIMx_CCR1 is greater than the content of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). There are 3 possible options for flag setting in center-aligned mode, refer to the CMS bits in the TIMx_CR1 register for the full description.
+If channel CC1 is configured as input: this bit is set when counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1, as per the edge sensitivity defined with the CC1P and CC1NP bits setting, in TIMx_CCER).
+ 1
+ 1
+ read-write
+
+
+ B_0x0
+ No compare match / No input capture occurred
+ 0x0
+
+
+ B_0x1
+ A compare match or an input capture occurred
+ 0x1
+
+
+
+
+ CC2IF
+ Capture/Compare 2 interrupt flag
+refer to CC1IF description
+ 2
+ 1
+ read-write
+
+
+ COMIF
+ COM interrupt flag
+This flag is set by hardware on a COM event (once the capture/compare control bits –CCxE, CCxNE, OCxM– have been updated). It is cleared by software.
+ 5
+ 1
+ read-write
+
+
+ B_0x0
+ No COM event occurred
+ 0x0
+
+
+ B_0x1
+ COM interrupt pending
+ 0x1
+
+
+
+
+ TIF
+ Trigger interrupt flag
+This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode, both edges in case gated mode is selected). It is set when the counter starts or stops when gated mode is selected. It is cleared by software.
+ 6
+ 1
+ read-write
+
+
+ B_0x0
+ No trigger event occurred
+ 0x0
+
+
+ B_0x1
+ Trigger interrupt pending
+ 0x1
+
+
+
+
+ BIF
+ Break interrupt flag
+This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active.
+ 7
+ 1
+ read-write
+
+
+ B_0x0
+ No break event occurred
+ 0x0
+
+
+ B_0x1
+ An active level has been detected on the break input
+ 0x1
+
+
+
+
+ CC1OF
+ Capture/Compare 1 overcapture flag
+This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0’.
+ 9
+ 1
+ read-write
+
+
+ B_0x0
+ No overcapture has been detected
+ 0x0
+
+
+ B_0x1
+ The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set
+ 0x1
+
+
+
+
+ CC2OF
+ Capture/Compare 2 overcapture flag
+Refer to CC1OF description
+ 10
+ 1
+ read-write
+
+
+
+
+ EGR
+ EGR
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ UG
+ Update generation
+This bit can be set by software, it is automatically cleared by hardware.
+ 0
+ 1
+ write-only
+
+
+ B_0x0
+ No action
+ 0x0
+
+
+ B_0x1
+ Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected).
+ 0x1
+
+
+
+
+ CC1G
+ Capture/Compare 1 generation
+This bit is set by software in order to generate an event, it is automatically cleared by hardware.
+If channel CC1 is configured as output:
+CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
+If channel CC1 is configured as input:
+The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high.
+ 1
+ 1
+ write-only
+
+
+ B_0x0
+ No action
+ 0x0
+
+
+ B_0x1
+ A capture/compare event is generated on channel 1:
+ 0x1
+
+
+
+
+ CC2G
+ Capture/Compare 2 generation
+Refer to CC1G description
+ 2
+ 1
+ write-only
+
+
+ COMG
+ Capture/Compare control update generation
+This bit can be set by software, it is automatically cleared by hardware.
+Note: This bit acts only on channels that have a complementary output.
+ 5
+ 1
+ read-write
+
+
+ B_0x0
+ No action
+ 0x0
+
+
+ B_0x1
+ When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits
+ 0x1
+
+
+
+
+ TG
+ Trigger generation
+This bit is set by software in order to generate an event, it is automatically cleared by hardware.
+ 6
+ 1
+ write-only
+
+
+ B_0x0
+ No action
+ 0x0
+
+
+ B_0x1
+ The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled
+ 0x1
+
+
+
+
+ BG
+ Break generation
+This bit is set by software in order to generate an event, it is automatically cleared by hardware.
+ 7
+ 1
+ write-only
+
+
+ B_0x0
+ No action
+ 0x0
+
+
+ B_0x1
+ A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled.
+ 0x1
+
+
+
+
+
+
+ CCMR1_Output
+ CCMR1_Output
+ capture/compare mode register (output
+ mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CC1S
+ Capture/Compare 1 selection
+This bit-field defines the direction of the channel (input/output) as well as the used input.
+Note: CC1S bits are writable only when the channel is OFF (CC1E = '0’ in TIMx_CCER).
+ 0
+ 2
+ read-write
+
+
+ B_0x0
+ CC1 channel is configured as output.
+ 0x0
+
+
+ B_0x1
+ CC1 channel is configured as input, IC1 is mapped on TI1.
+ 0x1
+
+
+ B_0x2
+ CC1 channel is configured as input, IC1 is mapped on TI2.
+ 0x2
+
+
+ B_0x3
+ CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
+ 0x3
+
+
+
+
+ OC1FE
+ Output Compare 1 fast enable
+This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger.
+ 2
+ 1
+ read-write
+
+
+ B_0x0
+ CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles.
+ 0x0
+
+
+ B_0x1
+ An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode.
+ 0x1
+
+
+
+
+ OC1PE
+ Output Compare 1 preload enable
+Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output).
+The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.
+ 3
+ 1
+ read-write
+
+
+ B_0x0
+ Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately.
+ 0x0
+
+
+ B_0x1
+ Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event.
+ 0x1
+
+
+
+
+ OC1M1
+ Output Compare 1 mode
+These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
+Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output).
+In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen†mode to “PWM†mode.
+On channels that have a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated.
+The OC1M[3] bit is not contiguous, located in bit 16.
+ 4
+ 3
+ read-write
+
+
+ CC2S
+ Capture/Compare 2 selection
+This bit-field defines the direction of the channel (input/output) as well as the used input.
+Note: CC2S bits are writable only when the channel is OFF (CC2E = '0’ in TIMx_CCER).
+ 8
+ 2
+ read-write
+
+
+ B_0x0
+ CC2 channel is configured as output.
+ 0x0
+
+
+ B_0x1
+ CC2 channel is configured as input, IC2 is mapped on TI2.
+ 0x1
+
+
+ B_0x2
+ CC2 channel is configured as input, IC2 is mapped on TI1.
+ 0x2
+
+
+ B_0x3
+ CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)
+ 0x3
+
+
+
+
+ OC2FE
+ Output Compare 2 fast enable
+ 10
+ 1
+ read-write
+
+
+ OC2PE
+ Output Compare 2 preload enable
+ 11
+ 1
+ read-write
+
+
+ OC2M
+ Output Compare 2 mode
+ 12
+ 3
+ read-write
+ OC2M read-write Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / Reserved 6 PwmMode2 Inversely to PwmMode1 / Reserved 7
+
+ OC1M2
+ Output Compare 1 mode
+These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
+Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output).
+In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen†mode to “PWM†mode.
+On channels that have a complementary output, this bit field is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the OC1M active bits take the new value from the preloaded bits only when a COM event is generated.
+The OC1M[3] bit is not contiguous, located in bit 16.
+ 16
+ 1
+ read-write
+
+
+ OC2M_3
+ Output Compare 2 mode
+ 24
+ 1
+ read-write
+ OC2M_3 read-write Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1
+
+
+
+ CCMR1_Input
+ CCMR1_Input
+ capture/compare mode register 1 (input
+ mode)
+ CCMR1_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CC1S
+ Capture/Compare 1 Selection
+This bit-field defines the direction of the channel (input/output) as well as the used input.
+Note: CC1S bits are writable only when the channel is OFF (CC1E = '0’ in TIMx_CCER).
+ 0
+ 2
+ read-write
+
+
+ B_0x0
+ CC1 channel is configured as output
+ 0x0
+
+
+ B_0x1
+ CC1 channel is configured as input, IC1 is mapped on TI1
+ 0x1
+
+
+ B_0x2
+ CC1 channel is configured as input, IC1 is mapped on TI2
+ 0x2
+
+
+ B_0x3
+ CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
+ 0x3
+
+
+
+
+ IC1PSC
+ Input capture 1 prescaler
+This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).
+ 2
+ 2
+ read-write
+
+
+ B_0x0
+ no prescaler, capture is done each time an edge is detected on the capture input
+ 0x0
+
+
+ B_0x1
+ capture is done once every 2 events
+ 0x1
+
+
+ B_0x2
+ capture is done once every 4 events
+ 0x2
+
+
+ B_0x3
+ capture is done once every 8 events
+ 0x3
+
+
+
+
+ IC1F
+ Input capture 1 filter
+This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output:
+ 4
+ 4
+ read-write
+
+
+ B_0x0
+ No filter, sampling is done at fDTS
+ 0x0
+
+
+ B_0x1
+ fSAMPLING=fCK_INT, N=2
+ 0x1
+
+
+ B_0x2
+ fSAMPLING=fCK_INT, N=4
+ 0x2
+
+
+ B_0x3
+ fSAMPLING=fCK_INT, N=8
+ 0x3
+
+
+ B_0x4
+ fSAMPLING=fDTS/2, N=6
+ 0x4
+
+
+ B_0x5
+ fSAMPLING=fDTS/2, N=8
+ 0x5
+
+
+ B_0x6
+ fSAMPLING=fDTS/4, N=6
+ 0x6
+
+
+ B_0x7
+ fSAMPLING=fDTS/4, N=8
+ 0x7
+
+
+ B_0x8
+ fSAMPLING=fDTS/8, N=6
+ 0x8
+
+
+ B_0x9
+ fSAMPLING=fDTS/8, N=8
+ 0x9
+
+
+ B_0xA
+ fSAMPLING=fDTS/16, N=5
+ 0xA
+
+
+ B_0xB
+ fSAMPLING=fDTS/16, N=6
+ 0xB
+
+
+ B_0xC
+ fSAMPLING=fDTS/16, N=8
+ 0xC
+
+
+ B_0xD
+ fSAMPLING=fDTS/32, N=5
+ 0xD
+
+
+ B_0xE
+ fSAMPLING=fDTS/32, N=6
+ 0xE
+
+
+ B_0xF
+ fSAMPLING=fDTS/32, N=8
+ 0xF
+
+
+
+
+ CC2S
+ Capture/Compare 2 selection
+This bit-field defines the direction of the channel (input/output) as well as the used input.
+Note: CC2S bits are writable only when the channel is OFF (CC2E = '0’ in TIMx_CCER).
+ 8
+ 2
+ read-write
+
+
+ B_0x0
+ CC2 channel is configured as output
+ 0x0
+
+
+ B_0x1
+ CC2 channel is configured as input, IC2 is mapped on TI2
+ 0x1
+
+
+ B_0x2
+ CC2 channel is configured as input, IC2 is mapped on TI1
+ 0x2
+
+
+ B_0x3
+ CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register)
+ 0x3
+
+
+
+
+ IC2PSC
+ Input capture 2 prescaler
+ 10
+ 2
+ read-write
+
+
+ IC2F
+ Input capture 2 filter
+ 12
+ 4
+ read-write
+
+
+
+
+ CCER
+ CCER
+ capture/compare enable
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC1E
+ Capture/Compare 1 output enable
+When CC1 channel is configured as output, the OC1 level depends on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits, regardless of the CC1E bits state. Refer to for details.
+ 0
+ 1
+ read-write
+
+
+ B_0x0
+ Capture mode disabled / OC1 is not active (see below)
+ 0x0
+
+
+ B_0x1
+ Capture mode enabled / OC1 signal is output on the corresponding output pin
+ 0x1
+
+
+
+
+ CC1P
+ Capture/Compare 1 output polarity
+When CC1 channel is configured as input, both CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations.
+CC1NP=0, CC1P=0: non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode or encoder mode).
+CC1NP=0, CC1P=1: inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode or encoder mode).
+CC1NP=1, CC1P=1: non-inverted/both edges/ The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1is not inverted (trigger operation in gated mode). This configuration must not be used in encoder mode.
+CC1NP=1, CC1P=0: this configuration is reserved, it must not be used.
+Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
+On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated.
+ 1
+ 1
+ read-write
+
+
+ B_0x0
+ OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)
+ 0x0
+
+
+ B_0x1
+ OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)
+ 0x1
+
+
+
+
+ CC1NE
+ Capture/Compare 1 complementary output enable
+ 2
+ 1
+ read-write
+
+
+ B_0x0
+ Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
+ 0x0
+
+
+ B_0x1
+ On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
+ 0x1
+
+
+
+
+ CC1NP
+ Capture/Compare 1 complementary output polarity
+CC1 channel configured as output:
+CC1 channel configured as input:
+This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer
+to CC1P description.
+Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=â€00†(the channel is configured in output).
+On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a Commutation event is generated.
+ 3
+ 1
+ read-write
+
+
+ B_0x0
+ OC1N active high
+ 0x0
+
+
+ B_0x1
+ OC1N active low
+ 0x1
+
+
+
+
+ CC2E
+ Capture/Compare 2 output enable
+Refer to CC1E description
+ 4
+ 1
+ read-write
+
+
+ CC2P
+ Capture/Compare 2 output polarity
+Refer to CC1P description
+ 5
+ 1
+ read-write
+
+
+ CC2NP
+ Capture/Compare 2 complementary output polarity
+Refer to CC1NP description
+ 7
+ 1
+ read-write
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ 0x00000000
+
+
+ CNT
+ counter value
+ 0
+ 16
+ read-write
+
+
+ UIFCPY
+ UIF Copy
+ 31
+ 1
+ read-only
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ ARR
+ ARR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x0000FFFF
+
+
+ ARR
+ Auto-reload value
+ 0
+ 16
+
+
+
+
+ RCR
+ RCR
+ repetition counter register
+ 0x30
+ 0x20
+ read-write
+ 0x0000
+
+
+ REP
+ Repetition counter value
+ 0
+ 8
+
+
+
+
+ CCR1
+ CCR1
+ capture/compare register 1
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR1
+ Capture/Compare 1 value
+ 0
+ 16
+
+
+
+
+ CCR2
+ CCR2
+ capture/compare register 2
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR2
+ Capture/Compare 2 value
+ 0
+ 16
+
+
+
+
+ BDTR
+ BDTR
+ break and dead-time register
+ 0x44
+ 0x20
+ read-write
+ 0x0000
+
+
+ DTG
+ Dead-time generator setup
+This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration.
+DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS
+DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS
+DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS
+DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS
+Example if TDTS=125ns (8MHz), dead-time possible values are:
+0 to 15875 ns by 125 ns steps,
+16 µs to 31750 ns by 250 ns steps,
+32 µs to 63 µs by 1 µs steps,
+64 µs to 126 µs by 2 µs steps
+Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
+ 0
+ 8
+ read-write
+
+
+ LOCK
+ Lock configuration
+These bits offer a write protection against software errors.
+Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.
+ 8
+ 2
+ read-write
+
+
+ B_0x0
+ LOCK OFF - No bit is write protected
+ 0x0
+
+
+ B_0x1
+ LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written
+ 0x1
+
+
+ B_0x2
+ LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written.
+ 0x2
+
+
+ B_0x3
+ LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written.
+ 0x3
+
+
+
+
+ OSSI
+ Off-state selection for Idle mode
+This bit is used when MOE=0 on channels configured as outputs.
+See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818).
+Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
+ 10
+ 1
+ read-write
+
+
+ B_0x0
+ When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0)
+ 0x0
+
+
+ B_0x1
+ When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1)
+ 0x1
+
+
+
+
+ OSSR
+ Off-state selection for Run mode
+This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer.
+See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818).
+Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
+ 11
+ 1
+ read-write
+
+
+ B_0x0
+ When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the AFIO logic, which forces a Hi-Z state)
+ 0x0
+
+
+ B_0x1
+ When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer).
+ 0x1
+
+
+
+
+ BKE
+ Break enable
+1; Break inputs (BRK and CCS clock failure event) enabled
+This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
+Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
+ 12
+ 1
+ read-write
+
+
+ B_0x0
+ Break inputs (BRK and CCS clock failure event) disabled
+ 0x0
+
+
+
+
+ BKP
+ Break polarity
+Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
+Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
+ 13
+ 1
+ read-write
+
+
+ B_0x0
+ Break input BRK is active low
+ 0x0
+
+
+ B_0x1
+ Break input BRK is active high
+ 0x1
+
+
+
+
+ AOE
+ Automatic output enable
+Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
+ 14
+ 1
+ read-write
+
+
+ B_0x0
+ MOE can be set only by software
+ 0x0
+
+
+ B_0x1
+ MOE can be set by software or automatically at the next update event (if the break input is not be active)
+ 0x1
+
+
+
+
+ MOE
+ Main output enable
+This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output.
+See OC/OCN enable description for more details (enable register (TIM15_CCER) on page 818).
+ 15
+ 1
+ read-write
+
+
+ B_0x0
+ OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit.
+ 0x0
+
+
+ B_0x1
+ OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register)
+ 0x1
+
+
+
+
+ BKF
+ Break filter
+This bit-field defines the frequency used to sample the BRK input signal and the length of the digital filter applied to BRK. The digital filter is made of an event counter in which N events are needed to validate a transition on the output:
+Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
+ 16
+ 4
+ read-write
+
+
+ B_0x0
+ No filter, BRK acts asynchronously
+ 0x0
+
+
+ B_0x1
+ fSAMPLING=fCK_INT, N=2
+ 0x1
+
+
+ B_0x2
+ fSAMPLING=fCK_INT, N=4
+ 0x2
+
+
+ B_0x3
+ fSAMPLING=fCK_INT, N=8
+ 0x3
+
+
+ B_0x4
+ fSAMPLING=fDTS/2, N=6
+ 0x4
+
+
+ B_0x5
+ fSAMPLING=fDTS/2, N=8
+ 0x5
+
+
+ B_0x6
+ fSAMPLING=fDTS/4, N=6
+ 0x6
+
+
+ B_0x7
+ fSAMPLING=fDTS/4, N=8
+ 0x7
+
+
+ B_0x8
+ fSAMPLING=fDTS/8, N=6
+ 0x8
+
+
+ B_0x9
+ fSAMPLING=fDTS/8, N=8
+ 0x9
+
+
+ B_0xA
+ fSAMPLING=fDTS/16, N=5
+ 0xA
+
+
+ B_0xB
+ fSAMPLING=fDTS/16, N=6
+ 0xB
+
+
+ B_0xC
+ fSAMPLING=fDTS/16, N=8
+ 0xC
+
+
+ B_0xD
+ fSAMPLING=fDTS/32, N=5
+ 0xD
+
+
+ B_0xE
+ fSAMPLING=fDTS/32, N=6
+ 0xE
+
+
+ B_0xF
+ fSAMPLING=fDTS/32, N=8
+ 0xF
+
+
+
+
+ BKDSRM
+ Break Disarm
+This bit is cleared by hardware when no break source is active.
+The BKDSRM bit must be set by software to release the bidirectional output control (open-drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared.
+Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
+ 26
+ 1
+ read-write
+
+
+ B_0x0
+ Break input BRK is armed
+ 0x0
+
+
+ B_0x1
+ Break input BRK is disarmed
+ 0x1
+
+
+
+
+ BKBID
+ Break Bidirectional
+In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices.
+Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
+Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
+ 28
+ 1
+ read-write
+
+
+ B_0x0
+ Break input BRK in input mode
+ 0x0
+
+
+ B_0x1
+ Break input BRK in bidirectional mode
+ 0x1
+
+
+
+
+
+
+ DCR
+ DCR
+ DMA control register
+ 0x48
+ 0x20
+ read-write
+ 0x0000
+
+
+ DBA
+ DMA base address
+This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register.
+Example:
+...
+ 0
+ 5
+ read-write
+
+
+ B_0x0
+ TIMx_CR1,
+ 0x0
+
+
+ B_0x1
+ TIMx_CR2,
+ 0x1
+
+
+ B_0x2
+ TIMx_SMCR,
+ 0x2
+
+
+
+
+ DBL
+ DMA burst length
+This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address).
+...
+ 8
+ 5
+ read-write
+
+
+ B_0x0
+ 1 transfer,
+ 0x0
+
+
+ B_0x1
+ 2 transfers,
+ 0x1
+
+
+ B_0x2
+ 3 transfers,
+ 0x2
+
+
+ B_0x11
+ 18 transfers.
+ 0x11
+
+
+
+
+
+
+ DMAR
+ DMAR
+ DMA address for full transfer
+ 0x4C
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMAB
+ DMA register for burst
+ accesses
+ 0
+ 16
+
+
+
+
+
+
+ TIM16
+ General purpose timers
+ TIM
+ 0x40014400
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM16
+ TIM16 global interrupt
+ 21
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+ UDIS
+ Update disable
+ 1
+ 1
+
+
+ URS
+ Update request source
+ 2
+ 1
+
+
+ OPM
+ One-pulse mode
+ 3
+ 1
+
+
+ ARPE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ CKD
+ Clock division
+ 8
+ 2
+
+
+ UIFREMAP
+ UIF status bit remapping
+ 11
+ 1
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ OIS1N
+ Output Idle state 1
+ 9
+ 1
+
+
+ OIS1
+ Output Idle state 1
+ 8
+ 1
+
+
+ CCDS
+ Capture/compare DMA
+ selection
+ 3
+ 1
+
+
+ CCUS
+ Capture/compare control update
+ selection
+ 2
+ 1
+
+
+ CCPC
+ Capture/compare preloaded
+ control
+ 0
+ 1
+
+
+
+
+ DIER
+ DIER
+ DMA/Interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ COMDE
+ COM DMA request enable
+ 13
+ 1
+
+
+ CC1DE
+ Capture/Compare 1 DMA request
+ enable
+ 9
+ 1
+
+
+ UDE
+ Update DMA request enable
+ 8
+ 1
+
+
+ BIE
+ Break interrupt enable
+ 7
+ 1
+
+
+ COMIE
+ COM interrupt enable
+ 5
+ 1
+
+
+ CC1IE
+ Capture/Compare 1 interrupt
+ enable
+ 1
+ 1
+
+
+ UIE
+ Update interrupt enable
+ 0
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC1OF
+ Capture/Compare 1 overcapture
+ flag
+ 9
+ 1
+
+
+ BIF
+ Break interrupt flag
+ 7
+ 1
+
+
+ COMIF
+ COM interrupt flag
+ 5
+ 1
+
+
+ CC1IF
+ Capture/compare 1 interrupt
+ flag
+ 1
+ 1
+
+
+ UIF
+ Update interrupt flag
+ 0
+ 1
+
+
+
+
+ EGR
+ EGR
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ BG
+ Break generation
+ 7
+ 1
+
+
+ COMG
+ Capture/Compare control update
+ generation
+ 5
+ 1
+
+
+ CC1G
+ Capture/compare 1
+ generation
+ 1
+ 1
+
+
+ UG
+ Update generation
+ 0
+ 1
+
+
+
+
+ CCMR1_Output
+ CCMR1_Output
+ capture/compare mode register (output
+ mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OC1M_2
+ Output Compare 1 mode
+ 16
+ 1
+
+
+ OC1M
+ Output Compare 1 mode
+ 4
+ 3
+ OC1M read-write Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy 3 ForceInactive OCyREF is forced low 4 ForceActive OCyREF is forced high 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active 6 PwmMode2 Inversely to PwmMode1 7
+
+ OC1PE
+ Output Compare 1 preload
+ enable
+ 3
+ 1
+
+
+ OC1FE
+ Output Compare 1 fast
+ enable
+ 2
+ 1
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+
+
+ CCMR1_Input
+ CCMR1_Input
+ capture/compare mode register 1 (input
+ mode)
+ CCMR1_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IC1F
+ Input capture 1 filter
+ 4
+ 4
+
+
+ IC1PSC
+ Input capture 1 prescaler
+ 2
+ 2
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+
+
+ CCER
+ CCER
+ capture/compare enable
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC1NP
+ Capture/Compare 1 output
+ Polarity
+ 3
+ 1
+
+
+ CC1NE
+ Capture/Compare 1 complementary output
+ enable
+ 2
+ 1
+
+
+ CC1P
+ Capture/Compare 1 output
+ Polarity
+ 1
+ 1
+
+
+ CC1E
+ Capture/Compare 1 output
+ enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ 0x00000000
+
+
+ CNT
+ counter value
+ 0
+ 16
+ read-write
+
+
+ UIFCPY
+ UIF Copy
+ 31
+ 1
+ read-only
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ ARR
+ ARR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ARR
+ Auto-reload value
+ 0
+ 16
+
+
+
+
+ RCR
+ RCR
+ repetition counter register
+ 0x30
+ 0x20
+ read-write
+ 0x0000
+
+
+ REP
+ Repetition counter value
+ 0
+ 8
+
+
+
+
+ CCR1
+ CCR1
+ capture/compare register 1
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR1
+ Capture/Compare 1 value
+ 0
+ 16
+
+
+
+
+ BDTR
+ BDTR
+ break and dead-time register
+ 0x44
+ 0x20
+ read-write
+ 0x0000
+
+
+ DTG
+ Dead-time generator setup
+ 0
+ 8
+
+
+ LOCK
+ Lock configuration
+ 8
+ 2
+
+
+ OSSI
+ Off-state selection for Idle
+ mode
+ 10
+ 1
+
+
+ OSSR
+ Off-state selection for Run
+ mode
+ 11
+ 1
+
+
+ BKE
+ Break enable
+ 12
+ 1
+
+
+ BKP
+ Break polarity
+ 13
+ 1
+
+
+ AOE
+ Automatic output enable
+ 14
+ 1
+
+
+ MOE
+ Main output enable
+ 15
+ 1
+
+
+ BKF
+ Break filter
+ 16
+ 4
+
+
+ BKDSRM
+ Break Disarm
+ 26
+ 1
+
+
+ BKBID
+ Break Bidirectional
+ 28
+ 1
+
+
+
+
+ DCR
+ DCR
+ DMA control register
+ 0x48
+ 0x20
+ read-write
+ 0x0000
+
+
+ DBL
+ DMA burst length
+ 8
+ 5
+
+
+ DBA
+ DMA base address
+ 0
+ 5
+
+
+
+
+ DMAR
+ DMAR
+ DMA address for full transfer
+ 0x4C
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMAB
+ DMA register for burst
+ accesses
+ 0
+ 16
+
+
+
+
+ AF1
+ AF1
+ TIM17 option register 1
+ 0x60
+ 0x20
+ read-write
+ 0x0000
+
+
+ BKINE
+ BRK BKIN input enable
+ 0
+ 1
+
+
+ BKCMP1E
+ BRK COMP1 enable
+ 1
+ 1
+
+
+ BKCMP2E
+ BRK COMP2 enable
+ 2
+ 1
+
+
+ BKDFBK1E
+ BRK DFSDM_BREAK1 enable
+ 8
+ 1
+
+
+ BKINP
+ BRK BKIN input polarity
+ 9
+ 1
+
+
+ BKCMP1P
+ BRK COMP1 input polarity
+ 10
+ 1
+
+
+ BKCMP2P
+ BRK COMP2 input polarit
+ 11
+ 1
+
+
+
+
+ TISEL
+ TISEL
+ input selection register
+ 0x68
+ 0x20
+ read-write
+ 0x0000
+
+
+ TI1SEL
+ selects input
+ 0
+ 4
+
+
+
+
+
+
+ TIM17
+ 0x40014800
+
+ TIM17
+ TIM17 global interrupt
+ 22
+
+
+
+ USART1
+ Universal synchronous asynchronous receiver
+ transmitter
+ USART
+ 0x40013800
+
+ 0x0
+ 0x400
+ registers
+
+
+ USART1
+ USART1 global interrupt
+ 27
+
+ USART3_USART4 USART3 + USART4 interrupt 29
+
+ CR1
+ CR1
+ Control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ RXFFIE
+ RXFIFO Full interrupt
+ enable
+ 31
+ 1
+
+
+ TXFEIE
+ TXFIFO empty interrupt
+ enable
+ 30
+ 1
+
+
+ FIFOEN
+ FIFO mode enable
+ 29
+ 1
+
+
+ M1
+ Word length
+ 28
+ 1
+
+
+ EOBIE
+ End of Block interrupt
+ enable
+ 27
+ 1
+
+
+ RTOIE
+ Receiver timeout interrupt
+ enable
+ 26
+ 1
+
+
+ DEAT
+ DEAT
+ 21
+ 5
+
+
+ DEDT
+ DEDT
+ 16
+ 5
+
+
+ OVER8
+ Oversampling mode
+ 15
+ 1
+
+
+ CMIE
+ Character match interrupt
+ enable
+ 14
+ 1
+
+
+ MME
+ Mute mode enable
+ 13
+ 1
+
+
+ M0
+ Word length
+ 12
+ 1
+
+
+ WAKE
+ Receiver wakeup method
+ 11
+ 1
+
+
+ PCE
+ Parity control enable
+ 10
+ 1
+
+
+ PS
+ Parity selection
+ 9
+ 1
+
+
+ PEIE
+ PE interrupt enable
+ 8
+ 1
+
+
+ TXEIE
+ interrupt enable
+ 7
+ 1
+
+
+ TCIE
+ Transmission complete interrupt
+ enable
+ 6
+ 1
+
+
+ RXNEIE
+ RXNE interrupt enable
+ 5
+ 1
+
+
+ IDLEIE
+ IDLE interrupt enable
+ 4
+ 1
+
+
+ TE
+ Transmitter enable
+ 3
+ 1
+
+
+ RE
+ Receiver enable
+ 2
+ 1
+
+
+ UESM
+ USART enable in Stop mode
+ 1
+ 1
+
+
+ UE
+ USART enable
+ 0
+ 1
+
+
+
+
+ CR2
+ CR2
+ Control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ ADD4_7
+ Address of the USART node
+ 28
+ 4
+
+
+ ADD0_3
+ Address of the USART node
+ 24
+ 4
+
+
+ RTOEN
+ Receiver timeout enable
+ 23
+ 1
+
+
+ ABRMOD
+ Auto baud rate mode
+ 21
+ 2
+
+
+ ABREN
+ Auto baud rate enable
+ 20
+ 1
+
+
+ MSBFIRST
+ Most significant bit first
+ 19
+ 1
+
+
+ TAINV
+ Binary data inversion
+ 18
+ 1
+
+
+ TXINV
+ TX pin active level
+ inversion
+ 17
+ 1
+
+
+ RXINV
+ RX pin active level
+ inversion
+ 16
+ 1
+
+
+ SWAP
+ Swap TX/RX pins
+ 15
+ 1
+
+
+ LINEN
+ LIN mode enable
+ 14
+ 1
+
+
+ STOP
+ STOP bits
+ 12
+ 2
+
+
+ CLKEN
+ Clock enable
+ 11
+ 1
+
+
+ CPOL
+ Clock polarity
+ 10
+ 1
+
+
+ CPHA
+ Clock phase
+ 9
+ 1
+
+
+ LBCL
+ Last bit clock pulse
+ 8
+ 1
+
+
+ LBDIE
+ LIN break detection interrupt
+ enable
+ 6
+ 1
+
+
+ LBDL
+ LIN break detection length
+ 5
+ 1
+
+
+ ADDM7
+ 7-bit Address Detection/4-bit Address
+ Detection
+ 4
+ 1
+
+
+ DIS_NSS
+ When the DSI_NSS bit is set, the NSS pin
+ input will be ignored
+ 3
+ 1
+
+
+ SLVEN
+ Synchronous Slave mode
+ enable
+ 0
+ 1
+
+
+
+
+ CR3
+ CR3
+ Control register 3
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ TXFTCFG
+ TXFIFO threshold
+ configuration
+ 29
+ 3
+
+
+ RXFTIE
+ RXFIFO threshold interrupt
+ enable
+ 28
+ 1
+
+
+ RXFTCFG
+ Receive FIFO threshold
+ configuration
+ 25
+ 3
+
+
+ TCBGTIE
+ Tr Complete before guard time, interrupt
+ enable
+ 24
+ 1
+
+
+ TXFTIE
+ threshold interrupt enable
+ 23
+ 1
+
+
+ WUFIE
+ Wakeup from Stop mode interrupt
+ enable
+ 22
+ 1
+
+
+ WUS
+ Wakeup from Stop mode interrupt flag
+ selection
+ 20
+ 2
+
+
+ SCARCNT
+ Smartcard auto-retry count
+ 17
+ 3
+
+
+ DEP
+ Driver enable polarity
+ selection
+ 15
+ 1
+
+
+ DEM
+ Driver enable mode
+ 14
+ 1
+
+
+ DDRE
+ DMA Disable on Reception
+ Error
+ 13
+ 1
+
+
+ OVRDIS
+ Overrun Disable
+ 12
+ 1
+
+
+ ONEBIT
+ One sample bit method
+ enable
+ 11
+ 1
+
+
+ CTSIE
+ CTS interrupt enable
+ 10
+ 1
+
+
+ CTSE
+ CTS enable
+ 9
+ 1
+
+
+ RTSE
+ RTS enable
+ 8
+ 1
+
+
+ DMAT
+ DMA enable transmitter
+ 7
+ 1
+
+
+ DMAR
+ DMA enable receiver
+ 6
+ 1
+
+
+ SCEN
+ Smartcard mode enable
+ 5
+ 1
+
+
+ NACK
+ Smartcard NACK enable
+ 4
+ 1
+
+
+ HDSEL
+ Half-duplex selection
+ 3
+ 1
+
+
+ IRLP
+ Ir low-power
+ 2
+ 1
+
+
+ IREN
+ Ir mode enable
+ 1
+ 1
+
+
+ EIE
+ Error interrupt enable
+ 0
+ 1
+
+
+
+
+ BRR
+ BRR
+ Baud rate register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ BRR_4_15
+ BRR_4_15
+ 4
+ 12
+
+
+ BRR_0_3
+ BRR_0_3
+ 0
+ 4
+
+
+
+
+ GTPR
+ GTPR
+ Guard time and prescaler
+ register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ GT
+ Guard time value
+ 8
+ 8
+
+
+ PSC
+ Prescaler value
+ 0
+ 8
+
+
+
+
+ RTOR
+ RTOR
+ Receiver timeout register
+ 0x14
+ 0x20
+ read-write
+ 0x0000
+
+
+ BLEN
+ Block Length
+ 24
+ 8
+
+
+ RTO
+ Receiver timeout value
+ 0
+ 24
+
+
+
+
+ RQR
+ RQR
+ Request register
+ 0x18
+ 0x20
+ write-only
+ 0x0000
+
+
+ TXFRQ
+ Transmit data flush
+ request
+ 4
+ 1
+
+
+ RXFRQ
+ Receive data flush request
+ 3
+ 1
+
+
+ MMRQ
+ Mute mode request
+ 2
+ 1
+
+
+ SBKRQ
+ Send break request
+ 1
+ 1
+
+
+ ABRRQ
+ Auto baud rate request
+ 0
+ 1
+
+
+
+
+ ISR
+ ISR
+ Interrupt & status
+ register
+ 0x1C
+ 0x20
+ read-only
+ 0x00C0
+
+
+ TXFT
+ TXFIFO threshold flag
+ 27
+ 1
+
+
+ RXFT
+ RXFIFO threshold flag
+ 26
+ 1
+
+
+ TCBGT
+ Transmission complete before guard time
+ flag
+ 25
+ 1
+
+
+ RXFF
+ RXFIFO Full
+ 24
+ 1
+
+
+ TXFE
+ TXFIFO Empty
+ 23
+ 1
+
+
+ REACK
+ REACK
+ 22
+ 1
+
+
+ TEACK
+ TEACK
+ 21
+ 1
+
+
+ WUF
+ WUF
+ 20
+ 1
+
+
+ RWU
+ RWU
+ 19
+ 1
+
+
+ SBKF
+ SBKF
+ 18
+ 1
+
+
+ CMF
+ CMF
+ 17
+ 1
+
+
+ BUSY
+ BUSY
+ 16
+ 1
+
+
+ ABRF
+ ABRF
+ 15
+ 1
+
+
+ ABRE
+ ABRE
+ 14
+ 1
+
+
+ UDR
+ SPI slave underrun error
+ flag
+ 13
+ 1
+
+
+ EOBF
+ EOBF
+ 12
+ 1
+
+
+ RTOF
+ RTOF
+ 11
+ 1
+
+
+ CTS
+ CTS
+ 10
+ 1
+
+
+ CTSIF
+ CTSIF
+ 9
+ 1
+
+
+ LBDF
+ LBDF
+ 8
+ 1
+
+
+ TXE
+ TXE
+ 7
+ 1
+
+
+ TC
+ TC
+ 6
+ 1
+
+
+ RXNE
+ RXNE
+ 5
+ 1
+
+
+ IDLE
+ IDLE
+ 4
+ 1
+
+
+ ORE
+ ORE
+ 3
+ 1
+
+
+ NF
+ NF
+ 2
+ 1
+
+
+ FE
+ FE
+ 1
+ 1
+
+
+ PE
+ PE
+ 0
+ 1
+
+
+
+
+ ICR
+ ICR
+ Interrupt flag clear register
+ 0x20
+ 0x20
+ write-only
+ 0x0000
+
+
+ WUCF
+ Wakeup from Stop mode clear
+ flag
+ 20
+ 1
+
+
+ CMCF
+ Character match clear flag
+ 17
+ 1
+
+
+ UDRCF
+ SPI slave underrun clear
+ flag
+ 13
+ 1
+
+
+ EOBCF
+ End of block clear flag
+ 12
+ 1
+
+
+ RTOCF
+ Receiver timeout clear
+ flag
+ 11
+ 1
+
+
+ CTSCF
+ CTS clear flag
+ 9
+ 1
+
+
+ LBDCF
+ LIN break detection clear
+ flag
+ 8
+ 1
+
+
+ TCBGTCF
+ Transmission complete before Guard time
+ clear flag
+ 7
+ 1
+
+
+ TCCF
+ Transmission complete clear
+ flag
+ 6
+ 1
+
+
+ TXFECF
+ TXFIFO empty clear flag
+ 5
+ 1
+
+
+ IDLECF
+ Idle line detected clear
+ flag
+ 4
+ 1
+
+
+ ORECF
+ Overrun error clear flag
+ 3
+ 1
+
+
+ NCF
+ Noise detected clear flag
+ 2
+ 1
+
+
+ FECF
+ Framing error clear flag
+ 1
+ 1
+
+
+ PECF
+ Parity error clear flag
+ 0
+ 1
+
+
+
+
+ RDR
+ RDR
+ Receive data register
+ 0x24
+ 0x20
+ read-only
+ 0x0000
+
+
+ RDR
+ Receive data value
+ 0
+ 9
+
+
+
+
+ TDR
+ TDR
+ Transmit data register
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ TDR
+ Transmit data value
+ 0
+ 9
+
+
+
+
+ PRESC
+ PRESC
+ Prescaler register
+ 0x2C
+ 0x20
+ read-write
+ 0x0000
+
+
+ PRESCALER
+ Clock prescaler
+ 0
+ 4
+
+
+
+
+
+
+ USART2
+ 0x40004400
+
+ USART2
+ USART2 global interrupt
+ 28
+
+
+
+ USART4
+ 0x40004C00
+
+
+ SPI1
+ Serial peripheral interface/Inter-IC
+ sound
+ SPI
+ 0x40013000
+
+ 0x0
+ 0x400
+ registers
+
+
+ SPI1
+ SPI1 global interrupt
+ 25
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ BIDIMODE
+ Bidirectional data mode
+ enable
+ 15
+ 1
+
+
+ BIDIOE
+ Output enable in bidirectional
+ mode
+ 14
+ 1
+
+
+ CRCEN
+ Hardware CRC calculation
+ enable
+ 13
+ 1
+
+
+ CRCNEXT
+ CRC transfer next
+ 12
+ 1
+
+
+ DFF
+ Data frame format
+ 11
+ 1
+
+
+ RXONLY
+ Receive only
+ 10
+ 1
+
+
+ SSM
+ Software slave management
+ 9
+ 1
+
+
+ SSI
+ Internal slave select
+ 8
+ 1
+
+
+ LSBFIRST
+ Frame format
+ 7
+ 1
+
+
+ SPE
+ SPI enable
+ 6
+ 1
+
+
+ BR
+ Baud rate control
+ 3
+ 3
+
+
+ MSTR
+ Master selection
+ 2
+ 1
+
+
+ CPOL
+ Clock polarity
+ 1
+ 1
+
+
+ CPHA
+ Clock phase
+ 0
+ 1
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ RXDMAEN
+ Rx buffer DMA enable
+ 0
+ 1
+
+
+ TXDMAEN
+ Tx buffer DMA enable
+ 1
+ 1
+
+
+ SSOE
+ SS output enable
+ 2
+ 1
+
+
+ NSSP
+ NSS pulse management
+ 3
+ 1
+
+
+ FRF
+ Frame format
+ 4
+ 1
+
+
+ ERRIE
+ Error interrupt enable
+ 5
+ 1
+
+
+ RXNEIE
+ RX buffer not empty interrupt
+ enable
+ 6
+ 1
+
+
+ TXEIE
+ Tx buffer empty interrupt
+ enable
+ 7
+ 1
+
+
+ DS
+ Data size
+ 8
+ 4
+
+
+ FRXTH
+ FIFO reception threshold
+ 12
+ 1
+
+
+ LDMA_RX
+ Last DMA transfer for
+ reception
+ 13
+ 1
+
+
+ LDMA_TX
+ Last DMA transfer for
+ transmission
+ 14
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x8
+ 0x20
+ 0x0002
+
+
+ RXNE
+ Receive buffer not empty
+ 0
+ 1
+ read-only
+
+
+ TXE
+ Transmit buffer empty
+ 1
+ 1
+ read-only
+
+
+ CHSIDE
+ Channel side
+ 2
+ 1
+ read-only
+
+
+ UDR
+ Underrun flag
+ 3
+ 1
+ read-only
+
+
+ CRCERR
+ CRC error flag
+ 4
+ 1
+ read-write
+
+
+ MODF
+ Mode fault
+ 5
+ 1
+ read-only
+
+
+ OVR
+ Overrun flag
+ 6
+ 1
+ read-only
+
+
+ BSY
+ Busy flag
+ 7
+ 1
+ read-only
+
+
+ TIFRFE
+ TI frame format error
+ 8
+ 1
+ read-only
+
+
+ FRLVL
+ FIFO reception level
+ 9
+ 2
+ read-only
+
+
+ FTLVL
+ FIFO transmission level
+ 11
+ 2
+ read-only
+
+
+
+
+ DR
+ DR
+ data register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ DR
+ Data register
+ 0
+ 16
+
+
+
+
+ CRCPR
+ CRCPR
+ CRC polynomial register
+ 0x10
+ 0x20
+ read-write
+ 0x0007
+
+
+ CRCPOLY
+ CRC polynomial register
+ 0
+ 16
+
+
+
+
+ RXCRCR
+ RXCRCR
+ RX CRC register
+ 0x14
+ 0x20
+ read-only
+ 0x0000
+
+
+ RxCRC
+ Rx CRC register
+ 0
+ 16
+
+
+
+
+ TXCRCR
+ TXCRCR
+ TX CRC register
+ 0x18
+ 0x20
+ read-only
+ 0x0000
+
+
+ TxCRC
+ Tx CRC register
+ 0
+ 16
+
+
+
+
+ I2SCFGR
+ I2SCFGR
+ configuration register
+ 0x1C
+ 0x20
+ read-write
+ 0x0000
+
+
+ CHLEN
+ Channel length (number of bits per audio
+ channel)
+ 0
+ 1
+
+
+ DATLEN
+ Data length to be
+ transferred
+ 1
+ 2
+
+
+ CKPOL
+ Inactive state clock
+ polarity
+ 3
+ 1
+
+
+ I2SSTD
+ standard selection
+ 4
+ 2
+
+
+ PCMSYNC
+ PCM frame synchronization
+ 7
+ 1
+
+
+ I2SCFG
+ I2S configuration mode
+ 8
+ 2
+
+
+ SE2
+ I2S enable
+ 10
+ 1
+
+
+ I2SMOD
+ I2S mode selection
+ 11
+ 1
+
+
+
+
+ I2SPR
+ I2SPR
+ prescaler register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ I2SDIV
+ linear prescaler
+ 0
+ 8
+
+
+ ODD
+ Odd factor for the
+ prescaler
+ 8
+ 1
+
+
+ MCKOE
+ Master clock output enable
+ 9
+ 1
+
+
+
+
+ HWCFGR
+ HWCFGR
+ hardware configuration
+ register
+ 0x3F0
+ 0x20
+ read-only
+ 0x0000
+
+
+ CRCCFG
+ CRC capable at SPI mode
+ 0
+ 4
+
+
+ I2SCFG
+ I2S mode implementation
+ 4
+ 4
+
+
+ I2SCKCFG
+ I2S master clock generator at I2S
+ mode
+ 8
+ 4
+
+
+ DSCFG
+ SPI data size
+ configuration
+ 12
+ 4
+
+
+ NSSCFG
+ NSS pulse feature enhancement at SPI
+ master
+ 16
+ 4
+
+
+
+
+ VERR
+ VERR
+ EXTI IP Version register
+ 0x3F4
+ 0x20
+ read-only
+ 0x00000000
+
+
+ MINREV
+ Minor Revision number
+ 0
+ 4
+
+
+ MAJREV
+ Major Revision number
+ 4
+ 4
+
+
+
+
+ IPIDR
+ IPIDR
+ EXTI Identification register
+ 0x3F8
+ 0x20
+ read-only
+ 0x00000000
+
+
+ IPID
+ IP Identification
+ 0
+ 32
+
+
+
+
+ SIDR
+ SIDR
+ EXTI Size ID register
+ 0x3FC
+ 0x20
+ read-only
+ 0x00000000
+
+
+ SID
+ Size Identification
+ 0
+ 32
+
+
+
+
+
+
+ SPI2
+ 0x40003800
+
+ SPI2
+ SPI2 global interrupt
+ 26
+
+
+
+ TIM1
+ Advanced-timers
+ TIM
+ 0x40012C00
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM1_BRK_UP_TRG_COM
+ TIM1 break, update, trigger and commutation interrupts
+ 13
+
+
+ TIM1_CC
+ TIM1 Capture Compare interrupt
+ 14
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+ OPM
+ One-pulse mode
+ 3
+ 1
+
+
+ UDIS
+ Update disable
+ 1
+ 1
+
+
+ URS
+ Update request source
+ 2
+ 1
+
+
+ DIR
+ Direction
+ 4
+ 1
+
+
+ CMS
+ Center-aligned mode
+ selection
+ 5
+ 2
+
+
+ ARPE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ CKD
+ Clock division
+ 8
+ 2
+
+
+ UIFREMAP
+ UIF status bit remapping
+ 11
+ 1
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ MMS2
+ Master mode selection 2
+ 20
+ 4
+
+
+ OIS6
+ Output Idle state 6 (OC6
+ output)
+ 18
+ 1
+
+
+ OIS5
+ Output Idle state 5 (OC5
+ output)
+ 16
+ 1
+
+
+ OIS4
+ Output Idle state 4
+ 14
+ 1
+
+
+ OIS3N
+ Output Idle state 3
+ 13
+ 1
+
+
+ OIS3
+ Output Idle state 3
+ 12
+ 1
+
+
+ OIS2N
+ Output Idle state 2
+ 11
+ 1
+
+
+ OIS2
+ Output Idle state 2
+ 10
+ 1
+
+
+ OIS1N
+ Output Idle state 1
+ 9
+ 1
+
+
+ OIS1
+ Output Idle state 1
+ 8
+ 1
+
+
+ TI1S
+ TI1 selection
+ 7
+ 1
+
+
+ MMS
+ Master mode selection
+ 4
+ 3
+
+
+ CCDS
+ Capture/compare DMA
+ selection
+ 3
+ 1
+
+
+ CCUS
+ Capture/compare control update
+ selection
+ 2
+ 1
+
+
+ CCPC
+ Capture/compare preloaded
+ control
+ 0
+ 1
+
+
+
+
+ SMCR
+ SMCR
+ slave mode control register
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ SMS
+ Slave mode selection
+ 0
+ 3
+
+
+ OCCS
+ OCREF clear selection
+ 3
+ 1
+
+
+ TS_4
+ Trigger selection
+ 4
+ 3
+
+
+ MSM
+ Master/Slave mode
+ 7
+ 1
+
+
+ ETF
+ External trigger filter
+ 8
+ 4
+
+
+ ETPS
+ External trigger prescaler
+ 12
+ 2
+
+
+ ECE
+ External clock enable
+ 14
+ 1
+
+
+ ETP
+ External trigger polarity
+ 15
+ 1
+
+
+ SMS_3
+ Slave mode selection - bit
+ 3
+ 16
+ 1
+
+
+ TS
+ Trigger selection
+ 20
+ 2
+
+
+
+
+ DIER
+ DIER
+ DMA/Interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ UIE
+ Update interrupt enable
+ 0
+ 1
+
+
+ CC1IE
+ Capture/Compare 1 interrupt
+ enable
+ 1
+ 1
+
+
+ CC2IE
+ Capture/Compare 2 interrupt
+ enable
+ 2
+ 1
+
+
+ CC3IE
+ Capture/Compare 3 interrupt
+ enable
+ 3
+ 1
+
+
+ CC4IE
+ Capture/Compare 4 interrupt
+ enable
+ 4
+ 1
+
+
+ COMIE
+ COM interrupt enable
+ 5
+ 1
+
+
+ TIE
+ Trigger interrupt enable
+ 6
+ 1
+
+
+ BIE
+ Break interrupt enable
+ 7
+ 1
+
+
+ UDE
+ Update DMA request enable
+ 8
+ 1
+
+
+ CC1DE
+ Capture/Compare 1 DMA request
+ enable
+ 9
+ 1
+
+
+ CC2DE
+ Capture/Compare 2 DMA request
+ enable
+ 10
+ 1
+
+
+ CC3DE
+ Capture/Compare 3 DMA request
+ enable
+ 11
+ 1
+
+
+ CC4DE
+ Capture/Compare 4 DMA request
+ enable
+ 12
+ 1
+
+
+ COMDE
+ COM DMA request enable
+ 13
+ 1
+
+
+ TDE
+ Trigger DMA request enable
+ 14
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ UIF
+ Update interrupt flag
+ 0
+ 1
+
+
+ CC1IF
+ Capture/compare 1 interrupt
+ flag
+ 1
+ 1
+
+
+ CC2IF
+ Capture/Compare 2 interrupt
+ flag
+ 2
+ 1
+
+
+ CC3IF
+ Capture/Compare 3 interrupt
+ flag
+ 3
+ 1
+
+
+ CC4IF
+ Capture/Compare 4 interrupt
+ flag
+ 4
+ 1
+
+
+ COMIF
+ COM interrupt flag
+ 5
+ 1
+
+
+ TIF
+ Trigger interrupt flag
+ 6
+ 1
+
+
+ BIF
+ Break interrupt flag
+ 7
+ 1
+
+
+ B2IF
+ Break 2 interrupt flag
+ 8
+ 1
+
+
+ CC1OF
+ Capture/Compare 1 overcapture
+ flag
+ 9
+ 1
+
+
+ CC2OF
+ Capture/compare 2 overcapture
+ flag
+ 10
+ 1
+
+
+ CC3OF
+ Capture/Compare 3 overcapture
+ flag
+ 11
+ 1
+
+
+ CC4OF
+ Capture/Compare 4 overcapture
+ flag
+ 12
+ 1
+
+
+ SBIF
+ System Break interrupt
+ flag
+ 13
+ 1
+
+
+ CC5IF
+ Compare 5 interrupt flag
+ 16
+ 1
+
+
+ CC6IF
+ Compare 6 interrupt flag
+ 17
+ 1
+
+
+
+
+ EGR
+ EGR
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ UG
+ Update generation
+ 0
+ 1
+
+
+ CC1G
+ Capture/compare 1
+ generation
+ 1
+ 1
+
+
+ CC2G
+ Capture/compare 2
+ generation
+ 2
+ 1
+
+
+ CC3G
+ Capture/compare 3
+ generation
+ 3
+ 1
+
+
+ CC4G
+ Capture/compare 4
+ generation
+ 4
+ 1
+
+
+ COMG
+ Capture/Compare control update
+ generation
+ 5
+ 1
+
+
+ TG
+ Trigger generation
+ 6
+ 1
+
+
+ BG
+ Break generation
+ 7
+ 1
+
+
+ B2G
+ Break 2 generation
+ 8
+ 1
+
+
+
+
+ CCMR1_Output
+ CCMR1_Output
+ capture/compare mode register 1 (output
+ mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+ OC1FE
+ Output Compare 1 fast
+ enable
+ 2
+ 1
+
+
+ OC1PE
+ Output Compare 1 preload
+ enable
+ 3
+ 1
+
+
+ OC1M
+ Output Compare 1 mode
+ 4
+ 3
+ OC1M read-write Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7
+
+ OC1CE
+ Output Compare 1 clear
+ enable
+ 7
+ 1
+
+
+ CC2S
+ Capture/Compare 2
+ selection
+ 8
+ 2
+
+
+ OC2FE
+ Output Compare 2 fast
+ enable
+ 10
+ 1
+
+
+ OC2PE
+ Output Compare 2 preload
+ enable
+ 11
+ 1
+
+
+ OC2M
+ Output Compare 2 mode
+ 12
+ 3
+
+
+ OC2CE
+ Output Compare 2 clear
+ enable
+ 15
+ 1
+
+
+ OC1M_3
+ Output Compare 1 mode - bit
+ 3
+ 16
+ 1
+ OC1M_3 read-write Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1
+
+ OC2M_3
+ Output Compare 2 mode - bit
+ 3
+ 24
+ 1
+
+
+
+
+ CCMR1_Input
+ CCMR1_Input
+ capture/compare mode register 1 (output
+ mode)
+ CCMR1_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+ OC1FE
+ Output Compare 1 fast
+ enable
+ 2
+ 1
+
+
+ OC1PE
+ Output Compare 1 preload
+ enable
+ 3
+ 1
+
+
+ OC1M
+ Output Compare 1 mode
+ 4
+ 3
+
+
+ OC1CE
+ Output Compare 1 clear
+ enable
+ 7
+ 1
+
+
+ CC2S
+ Capture/Compare 2
+ selection
+ 8
+ 2
+
+
+ OC2FE
+ Output Compare 2 fast
+ enable
+ 10
+ 1
+
+
+ OC2PE
+ Output Compare 2 preload
+ enable
+ 11
+ 1
+
+
+ OC2M
+ Output Compare 2 mode
+ 12
+ 3
+
+
+ OC2CE
+ Output Compare 2 clear
+ enable
+ 15
+ 1
+
+
+
+
+ CCMR2_Output
+ CCMR2_Output
+ capture/compare mode register 2 (output
+ mode)
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CC3S
+ Capture/Compare 3
+ selection
+ 0
+ 2
+
+
+ OC3FE
+ Output compare 3 fast
+ enable
+ 2
+ 1
+
+
+ OC3PE
+ Output compare 3 preload
+ enable
+ 3
+ 1
+
+
+ OC3M
+ Output compare 3 mode
+ 4
+ 3
+ OC3M read-write Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7
+
+ OC3CE
+ Output compare 3 clear
+ enable
+ 7
+ 1
+
+
+ CC4S
+ Capture/Compare 4
+ selection
+ 8
+ 2
+
+
+ OC4FE
+ Output compare 4 fast
+ enable
+ 10
+ 1
+
+
+ OC4PE
+ Output compare 4 preload
+ enable
+ 11
+ 1
+
+
+ OC4M
+ Output compare 4 mode
+ 12
+ 3
+
+
+ OC4CE
+ Output compare 4 clear
+ enable
+ 15
+ 1
+
+
+ OC3M_3
+ Output Compare 3 mode - bit
+ 3
+ 16
+ 1
+ OC3M_3 read-write Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1
+
+ OC4M_3
+ Output Compare 4 mode - bit
+ 3
+ 24
+ 1
+
+
+
+
+ CCMR2_Input
+ CCMR2_Input
+ capture/compare mode register 2 (output
+ mode)
+ CCMR2_Output
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CC3S
+ Capture/Compare 3
+ selection
+ 0
+ 2
+
+
+ OC3FE
+ Output compare 3 fast
+ enable
+ 2
+ 1
+
+
+ OC3PE
+ Output compare 3 preload
+ enable
+ 3
+ 1
+
+
+ OC3M
+ Output compare 3 mode
+ 4
+ 3
+
+
+ OC3CE
+ Output compare 3 clear
+ enable
+ 7
+ 1
+
+
+ CC4S
+ Capture/Compare 4
+ selection
+ 8
+ 2
+
+
+ OC4FE
+ Output compare 4 fast
+ enable
+ 10
+ 1
+
+
+ OC4PE
+ Output compare 4 preload
+ enable
+ 11
+ 1
+
+
+ OC4M
+ Output compare 4 mode
+ 12
+ 3
+
+
+ OC4CE
+ Output compare 4 clear
+ enable
+ 15
+ 1
+
+
+
+
+ CCER
+ CCER
+ capture/compare enable
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC1E
+ Capture/Compare 1 output
+ enable
+ 0
+ 1
+
+
+ CC1P
+ Capture/Compare 1 output
+ Polarity
+ 1
+ 1
+
+
+ CC1NE
+ Capture/Compare 1 complementary output
+ enable
+ 2
+ 1
+
+
+ CC1NP
+ Capture/Compare 1 output
+ Polarity
+ 3
+ 1
+
+
+ CC2E
+ Capture/Compare 2 output
+ enable
+ 4
+ 1
+
+
+ CC2P
+ Capture/Compare 2 output
+ Polarity
+ 5
+ 1
+
+
+ CC2NE
+ Capture/Compare 2 complementary output
+ enable
+ 6
+ 1
+
+
+ CC2NP
+ Capture/Compare 2 output
+ Polarity
+ 7
+ 1
+
+
+ CC3E
+ Capture/Compare 3 output
+ enable
+ 8
+ 1
+
+
+ CC3P
+ Capture/Compare 3 output
+ Polarity
+ 9
+ 1
+
+
+ CC3NE
+ Capture/Compare 3 complementary output
+ enable
+ 10
+ 1
+
+
+ CC3NP
+ Capture/Compare 3 output
+ Polarity
+ 11
+ 1
+
+
+ CC4E
+ Capture/Compare 4 output
+ enable
+ 12
+ 1
+
+
+ CC4P
+ Capture/Compare 3 output
+ Polarity
+ 13
+ 1
+
+
+ CC4NP
+ Capture/Compare 4 complementary output
+ polarity
+ 15
+ 1
+
+
+ CC5E
+ Capture/Compare 5 output
+ enable
+ 16
+ 1
+
+
+ CC5P
+ Capture/Compare 5 output
+ polarity
+ 17
+ 1
+
+
+ CC6E
+ Capture/Compare 6 output
+ enable
+ 20
+ 1
+
+
+ CC6P
+ Capture/Compare 6 output
+ polarity
+ 21
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ 0x00000000
+
+
+ CNT
+ counter value
+ 0
+ 16
+ read-write
+
+
+ UIFCPY
+ UIF copy
+ 31
+ 1
+ read-only
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ ARR
+ ARR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ARR
+ Auto-reload value
+ 0
+ 16
+
+
+
+
+ RCR
+ RCR
+ repetition counter register
+ 0x30
+ 0x20
+ read-write
+ 0x0000
+
+
+ REP
+ Repetition counter value
+ 0
+ 16
+
+
+
+
+ CCR1
+ CCR1
+ capture/compare register 1
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR1
+ Capture/Compare 1 value
+ 0
+ 16
+
+
+
+
+ CCR2
+ CCR2
+ capture/compare register 2
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR2
+ Capture/Compare 2 value
+ 0
+ 16
+
+
+
+
+ CCR3
+ CCR3
+ capture/compare register 3
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR3
+ Capture/Compare value
+ 0
+ 16
+
+
+
+
+ CCR4
+ CCR4
+ capture/compare register 4
+ 0x40
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR4
+ Capture/Compare value
+ 0
+ 16
+
+
+
+
+ BDTR
+ BDTR
+ break and dead-time register
+ 0x44
+ 0x20
+ read-write
+ 0x0000
+
+
+ DTG
+ Dead-time generator setup
+ 0
+ 8
+
+
+ LOCK
+ Lock configuration
+ 8
+ 2
+
+
+ OSSI
+ Off-state selection for Idle
+ mode
+ 10
+ 1
+
+
+ OSSR
+ Off-state selection for Run
+ mode
+ 11
+ 1
+
+
+ BKE
+ Break enable
+ 12
+ 1
+
+
+ BKP
+ Break polarity
+ 13
+ 1
+
+
+ AOE
+ Automatic output enable
+ 14
+ 1
+
+
+ MOE
+ Main output enable
+ 15
+ 1
+
+
+ BKF
+ Break filter
+ 16
+ 4
+
+
+ BK2F
+ Break 2 filter
+ 20
+ 4
+
+
+ BK2E
+ Break 2 enable
+ 24
+ 1
+
+
+ BK2P
+ Break 2 polarity
+ 25
+ 1
+
+
+ BKDSRM
+ Break Disarm
+ 26
+ 1
+
+
+ BK2DSRM
+ Break2 Disarm
+ 27
+ 1
+
+
+ BKBID
+ Break Bidirectional
+ 28
+ 1
+
+
+ BK2ID
+ Break2 bidirectional
+ 29
+ 1
+
+
+
+
+ DCR
+ DCR
+ DMA control register
+ 0x48
+ 0x20
+ read-write
+ 0x0000
+
+
+ DBL
+ DMA burst length
+ 8
+ 5
+
+
+ DBA
+ DMA base address
+ 0
+ 5
+
+
+
+
+ DMAR
+ DMAR
+ DMA address for full transfer
+ 0x4C
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMAB
+ DMA register for burst
+ accesses
+ 0
+ 16
+
+
+
+
+ OR1
+ OR1
+ option register 1
+ 0x50
+ 0x20
+ read-write
+ 0x0000
+
+
+ OCREF_CLR
+ Ocref_clr source selection
+ 0
+ 1
+
+
+
+
+ CCMR3_Output
+ CCMR3_Output
+ capture/compare mode register 2 (output
+ mode)
+ 0x54
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OC6M_3
+ Output Compare 6 mode bit
+ 3
+ 24
+ 1
+
+
+ OC5M_3
+ Output Compare 5 mode bit
+ 3
+ 16
+ 1
+ OC5M_3 read-write Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1
+
+ OC6CE
+ Output compare 6 clear
+ enable
+ 15
+ 1
+
+
+ OC6M
+ Output compare 6 mode
+ 12
+ 3
+
+
+ OC6PE
+ Output compare 6 preload
+ enable
+ 11
+ 1
+
+
+ OC6FE
+ Output compare 6 fast
+ enable
+ 10
+ 1
+
+
+ OC5CE
+ Output compare 5 clear
+ enable
+ 7
+ 1
+
+
+ OC5M
+ Output compare 5 mode
+ 4
+ 3
+ OC5M read-write Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7
+
+ OC5PE
+ Output compare 5 preload
+ enable
+ 3
+ 1
+
+
+ OC5FE
+ Output compare 5 fast
+ enable
+ 2
+ 1
+
+
+
+
+ CCR5
+ CCR5
+ capture/compare register 4
+ 0x58
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR5
+ Capture/Compare value
+ 0
+ 16
+
+
+ GC5C1
+ Group Channel 5 and Channel
+ 1
+ 29
+ 1
+
+
+ GC5C2
+ Group Channel 5 and Channel
+ 2
+ 30
+ 1
+
+
+ GC5C3
+ Group Channel 5 and Channel
+ 3
+ 31
+ 1
+
+
+
+
+ CCR6
+ CCR6
+ capture/compare register 4
+ 0x5C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR6
+ Capture/Compare value
+ 0
+ 16
+
+
+
+
+ AF1
+ AF1
+ DMA address for full transfer
+ 0x60
+ 0x20
+ read-write
+ 0x00000001
+
+
+ BKINE
+ BRK BKIN input enable
+ 0
+ 1
+
+
+ BKCMP1E
+ BRK COMP1 enable
+ 1
+ 1
+
+
+ BKCMP2E
+ BRK COMP2 enable
+ 2
+ 1
+
+
+ BKINP
+ BRK BKIN input polarity
+ 9
+ 1
+
+
+ BKCMP1P
+ BRK COMP1 input polarity
+ 10
+ 1
+
+
+ BKCMP2P
+ BRK COMP2 input polarity
+ 11
+ 1
+
+
+ ETRSEL
+ ETR source selection
+ 14
+ 3
+
+
+
+
+ AF2
+ AF2
+ DMA address for full transfer
+ 0x64
+ 0x20
+ read-write
+ 0x00000001
+
+
+ BK2INE
+ BRK2 BKIN input enable
+ 0
+ 1
+
+
+ BK2CMP1E
+ BRK2 COMP1 enable
+ 1
+ 1
+
+
+ BK2CMP2E
+ BRK2 COMP2 enable
+ 2
+ 1
+
+
+ BK2DFBK0E
+ BRK2 DFSDM_BREAK0 enable
+ 8
+ 1
+
+
+ BK2INP
+ BRK2 BKIN input polarity
+ 9
+ 1
+
+
+ BK2CMP1P
+ BRK2 COMP1 input polarity
+ 10
+ 1
+
+
+ BK2CMP2P
+ BRK2 COMP2 input polarity
+ 11
+ 1
+
+
+
+
+
+
+ ADC
+ Analog to Digital Converter instance
+ 1
+ ADC
+ 0x40012400
+
+ 0x0
+ 0x400
+ registers
+
+
+ ADC
+ ADC Interrupt
+ 12
+
+
+
+ ISR
+ ISR
+ ADC interrupt and status
+ register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCRDY
+ Channel Configuration Ready
+ flag
+ 13
+ 1
+
+
+ EOCAL
+ End Of Calibration flag
+ 11
+ 1
+
+
+ AWD3
+ ADC analog watchdog 3 flag
+ 9
+ 1
+
+
+ AWD2
+ ADC analog watchdog 2 flag
+ 8
+ 1
+
+
+ AWD1
+ ADC analog watchdog 1 flag
+ 7
+ 1
+
+
+ OVR
+ ADC group regular overrun
+ flag
+ 4
+ 1
+
+
+ EOS
+ ADC group regular end of sequence
+ conversions flag
+ 3
+ 1
+
+
+ EOC
+ ADC group regular end of unitary
+ conversion flag
+ 2
+ 1
+
+
+ EOSMP
+ ADC group regular end of sampling
+ flag
+ 1
+ 1
+
+
+ ADRDY
+ ADC ready flag
+ 0
+ 1
+
+
+
+
+ IER
+ IER
+ ADC interrupt enable register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCRDYIE
+ Channel Configuration Ready Interrupt
+ enable
+ 13
+ 1
+
+
+ EOCALIE
+ End of calibration interrupt
+ enable
+ 11
+ 1
+
+
+ AWD3IE
+ ADC analog watchdog 3
+ interrupt
+ 9
+ 1
+
+
+ AWD2IE
+ ADC analog watchdog 2
+ interrupt
+ 8
+ 1
+
+
+ AWD1IE
+ ADC analog watchdog 1
+ interrupt
+ 7
+ 1
+
+
+ OVRIE
+ ADC group regular overrun
+ interrupt
+ 4
+ 1
+
+
+ EOSIE
+ ADC group regular end of sequence
+ conversions interrupt
+ 3
+ 1
+
+
+ EOCIE
+ ADC group regular end of unitary
+ conversion interrupt
+ 2
+ 1
+
+
+ EOSMPIE
+ ADC group regular end of sampling
+ interrupt
+ 1
+ 1
+
+
+ ADRDYIE
+ ADC ready interrupt
+ 0
+ 1
+
+
+
+
+ CR
+ CR
+ ADC control register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ADCAL
+ ADC calibration
+ 31
+ 1
+
+
+ ADVREGEN
+ ADC voltage regulator
+ enable
+ 28
+ 1
+
+
+ ADSTP
+ ADC group regular conversion
+ stop
+ 4
+ 1
+
+
+ ADSTART
+ ADC group regular conversion
+ start
+ 2
+ 1
+
+
+ ADDIS
+ ADC disable
+ 1
+ 1
+
+
+ ADEN
+ ADC enable
+ 0
+ 1
+
+
+
+
+ CFGR1
+ CFGR1
+ ADC configuration register 1
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AWDCH1CH
+ ADC analog watchdog 1 monitored channel
+ selection
+ 26
+ 5
+
+
+ AWD1EN
+ ADC analog watchdog 1 enable on scope
+ ADC group regular
+ 23
+ 1
+
+
+ AWD1SGL
+ ADC analog watchdog 1 monitoring a
+ single channel or all channels
+ 22
+ 1
+
+
+ CHSELRMOD
+ Mode selection of the ADC_CHSELR
+ register
+ 21
+ 1
+
+
+ DISCEN
+ ADC group regular sequencer
+ discontinuous mode
+ 16
+ 1
+
+
+ AUTOFF
+ Auto-off mode
+ 15
+ 1
+
+
+ WAIT
+ Wait conversion mode
+ 14
+ 1
+
+
+ CONT
+ ADC group regular continuous conversion
+ mode
+ 13
+ 1
+
+
+ OVRMOD
+ ADC group regular overrun
+ configuration
+ 12
+ 1
+
+
+ EXTEN
+ ADC group regular external trigger
+ polarity
+ 10
+ 2
+
+
+ EXTSEL
+ ADC group regular external trigger
+ source
+ 6
+ 3
+
+
+ ALIGN
+ ADC data alignement
+ 5
+ 1
+
+
+ RES
+ ADC data resolution
+ 3
+ 2
+
+
+ SCANDIR
+ Scan sequence direction
+ 2
+ 1
+
+
+ DMACFG
+ ADC DMA transfer
+ configuration
+ 1
+ 1
+
+
+ DMAEN
+ ADC DMA transfer enable
+ 0
+ 1
+
+
+
+
+ CFGR2
+ CFGR2
+ ADC configuration register 2
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CKMODE
+ ADC clock mode
+ 30
+ 2
+
+
+ LFTRIG
+ Low frequency trigger mode
+ enable
+ 29
+ 1
+
+
+ TOVS
+ ADC oversampling discontinuous mode
+ (triggered mode) for ADC group regular
+ 9
+ 1
+
+
+ OVSS
+ ADC oversampling shift
+ 5
+ 4
+
+
+ OVSR
+ ADC oversampling ratio
+ 2
+ 3
+
+
+ OVSE
+ ADC oversampler enable on scope ADC
+ group regular
+ 0
+ 1
+
+
+
+
+ SMPR
+ SMPR
+ ADC sampling time register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SMP1
+ Sampling time selection
+ 0
+ 3
+
+
+ SMP2
+ Sampling time selection
+ 4
+ 3
+
+
+ SMPSEL
+ Channel sampling time
+ selection
+ 8
+ 19
+
+
+
+
+ AWD1TR
+ AWD1TR
+ watchdog threshold register
+ 0x20
+ 0x20
+ read-write
+ 0x0FFF0000
+
+
+ HT1
+ ADC analog watchdog 1 threshold
+ high
+ 16
+ 12
+
+
+ LT1
+ ADC analog watchdog 1 threshold
+ low
+ 0
+ 12
+
+
+
+
+ AWD2TR
+ AWD2TR
+ watchdog threshold register
+ 0x24
+ 0x20
+ read-write
+ 0x0FFF0000
+
+
+ HT2
+ ADC analog watchdog 2 threshold
+ high
+ 16
+ 12
+
+
+ LT2
+ ADC analog watchdog 2 threshold
+ low
+ 0
+ 12
+
+
+
+
+ CHSELR
+ CHSELR
+ channel selection register
+ 0x28
+ 0x20
+ read-write
+ 0x0FFF0000
+
+
+ CHSEL
+ Channel-x selection
+ 0
+ 19
+
+
+
+
+ CHSELR_1
+ CHSELR_1
+ channel selection register CHSELRMOD = 1 in
+ ADC_CFGR1
+ CHSELR
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SQ1
+ conversion of the sequence
+ 0
+ 4
+
+
+ SQ2
+ conversion of the sequence
+ 4
+ 4
+
+
+ SQ3
+ conversion of the sequence
+ 8
+ 4
+
+
+ SQ4
+ conversion of the sequence
+ 12
+ 4
+
+
+ SQ5
+ conversion of the sequence
+ 16
+ 4
+
+
+ SQ6
+ conversion of the sequence
+ 20
+ 4
+
+
+ SQ7
+ conversion of the sequence
+ 24
+ 4
+
+
+ SQ8
+ conversion of the sequence
+ 28
+ 4
+
+
+
+
+ AWD3TR
+ AWD3TR
+ watchdog threshold register
+ 0x2C
+ 0x20
+ read-write
+ 0x0FFF0000
+
+
+ HT3
+ ADC analog watchdog 3 threshold
+ high
+ 16
+ 12
+
+
+ LT3
+ ADC analog watchdog 3 threshold
+ high
+ 0
+ 12
+
+
+
+
+ DR
+ DR
+ ADC group regular conversion data
+ register
+ 0x40
+ 0x20
+ read-only
+ 0x00000000
+
+
+ regularDATA
+ ADC group regular conversion
+ data
+ 0
+ 16
+
+
+
+
+ AWD2CR
+ AWD2CR
+ ADC analog watchdog 2 configuration
+ register
+ 0xA0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AWD2CH
+ ADC analog watchdog 2 monitored channel
+ selection
+ 0
+ 19
+
+
+
+
+ AWD3CR
+ AWD3CR
+ ADC analog watchdog 3 configuration
+ register
+ 0xA4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AWD3CH
+ ADC analog watchdog 3 monitored channel
+ selection
+ 0
+ 19
+
+
+
+
+ CALFACT
+ CALFACT
+ ADC calibration factors
+ register
+ 0xB4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CALFACT
+ ADC calibration factor in single-ended
+ mode
+ 0
+ 7
+
+
+
+
+ CCR
+ CCR
+ ADC common control register
+ 0x308
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRESC
+ ADC prescaler
+ 18
+ 4
+
+
+ VREFEN
+ VREFINT enable
+ 22
+ 1
+
+
+ TSEN
+ Temperature sensor enable
+ 23
+ 1
+
+
+ VBATEN
+ VBAT enable
+ 24
+ 1
+
+
+
+
+ HWCFGR6
+ HWCFGR6
+ Hardware Configuration
+ Register
+ 0x3D8
+ 0x20
+ read-write
+ 0x1F1F1F1F
+
+
+ CHMAP20
+ Input channel mapping
+ 0
+ 5
+
+
+ CHMAP21
+ Input channel mapping
+ 8
+ 5
+
+
+ CHMAP22
+ Input channel mapping
+ 16
+ 5
+
+
+ CHMAP23
+ Input channel mapping
+ 24
+ 5
+
+
+
+
+ HWCFGR5
+ HWCFGR5
+ Hardware Configuration
+ Register
+ 0x3DC
+ 0x20
+ read-write
+ 0x1F080807
+
+
+ CHMAP19
+ Input channel mapping
+ 0
+ 5
+
+
+ CHMAP18
+ Input channel mapping
+ 8
+ 5
+
+
+ CHMAP17
+ Input channel mapping
+ 16
+ 5
+
+
+ CHMAP16
+ Input channel mapping
+ 24
+ 5
+
+
+
+
+ HWCFGR4
+ HWCFGR4
+ Hardware Configuration
+ Register
+ 0x3E0
+ 0x20
+ read-write
+ 0x070B0A09
+
+
+ CHMAP15
+ Input channel mapping
+ 0
+ 5
+
+
+ CHMAP14
+ Input channel mapping
+ 8
+ 5
+
+
+ CHMAP13
+ Input channel mapping
+ 16
+ 5
+
+
+ CHMAP12
+ Input channel mapping
+ 24
+ 5
+
+
+
+
+ HWCFGR3
+ HWCFGR3
+ Hardware Configuration
+ Register
+ 0x3E4
+ 0x20
+ read-write
+ 0x07060605
+
+
+ CHMAP11
+ Input channel mapping
+ 0
+ 5
+
+
+ CHMAP10
+ Input channel mapping
+ 8
+ 5
+
+
+ CHMAP9
+ Input channel mapping
+ 16
+ 5
+
+
+ CHMAP8
+ Input channel mapping
+ 24
+ 5
+
+
+
+
+ HWCFGR2
+ HWCFGR2
+ Hardware Configuration
+ Register
+ 0x3E8
+ 0x20
+ read-write
+ 0x05050404
+
+
+ CHMAP7
+ Input channel mapping
+ 0
+ 5
+
+
+ CHMAP6
+ Input channel mapping
+ 8
+ 5
+
+
+ CHMAP5
+ Input channel mapping
+ 16
+ 5
+
+
+ CHMAP4
+ Input channel mapping
+ 24
+ 5
+
+
+
+
+ HWCFGR1
+ HWCFGR1
+ Hardware Configuration
+ Register
+ 0x3EC
+ 0x20
+ read-write
+ 0x03020100
+
+
+ CHMAP3
+ Input channel mapping
+ 0
+ 5
+
+
+ CHMAP2
+ Input channel mapping
+ 8
+ 5
+
+
+ CHMAP1
+ Input channel mapping
+ 16
+ 5
+
+
+ CHMAP0
+ Input channel mapping
+ 24
+ 5
+
+
+
+
+ HWCFGR0
+ HWCFGR0
+ Hardware Configuration
+ Register
+ 0x3F0
+ 0x20
+ read-only
+ 0x00000110
+
+
+ NUM_CHAN_24
+ NUM_CHAN_24
+ 0
+ 4
+
+
+ EXTRA_AWDS
+ Extra analog watchdog
+ 4
+ 4
+
+
+ OVS
+ Oversampling
+ 8
+ 4
+
+
+
+
+ VERR
+ VERR
+ EXTI IP Version register
+ 0x3F4
+ 0x20
+ read-only
+ 0x00000000
+
+
+ MINREV
+ Minor Revision number
+ 0
+ 4
+
+
+ MAJREV
+ Major Revision number
+ 4
+ 4
+
+
+
+
+ IPIDR
+ IPIDR
+ EXTI Identification register
+ 0x3F8
+ 0x20
+ read-only
+ 0x00000000
+
+
+ IPID
+ IP Identification
+ 0
+ 32
+
+
+
+
+ SIDR
+ SIDR
+ EXTI Size ID register
+ 0x3FC
+ 0x20
+ read-only
+ 0x00000000
+
+
+ SID
+ Size Identification
+ 0
+ 32
+
+
+
+
+
+
+ TAMP
+ Tamper and backup registers
+ TAMP
+ 0x4000B000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0xFFFF0000
+
+
+ TAMP1E
+ TAMP1E
+ 0
+ 1
+
+
+ TAMP2E
+ TAMP2E
+ 1
+ 1
+
+
+ ITAMP1E
+ ITAMP1E
+ 16
+ 1
+
+
+ ITAMP3E
+ ITAMP3E
+ 18
+ 1
+
+
+ ITAMP4E
+ ITAMP4E
+ 19
+ 1
+
+
+ ITAMP5E
+ ITAMP5E
+ 20
+ 1
+
+
+ ITAMP6E
+ ITAMP6E
+ 21
+ 1
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TAMP1NOER
+ TAMP1NOER
+ 0
+ 1
+
+
+ TAMP2NOER
+ TAMP2NOER
+ 1
+ 1
+
+
+ TAMP1MSK
+ TAMP1MSK
+ 16
+ 1
+
+
+ TAMP2MSK
+ TAMP2MSK
+ 17
+ 1
+
+
+ TAMP1TRG
+ TAMP1TRG
+ 24
+ 1
+
+
+ TAMP2TRG
+ TAMP2TRG
+ 25
+ 1
+
+
+
+
+ FLTCR
+ FLTCR
+ TAMP filter control register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TAMPFREQ
+ TAMPFREQ
+ 0
+ 3
+
+
+ TAMPFLT
+ TAMPFLT
+ 3
+ 2
+
+
+ TAMPPRCH
+ TAMPPRCH
+ 5
+ 2
+
+
+ TAMPPUDIS
+ TAMPPUDIS
+ 7
+ 1
+
+
+
+
+ IER
+ IER
+ TAMP interrupt enable register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TAMP1IE
+ TAMP1IE
+ 0
+ 1
+
+
+ TAMP2IE
+ TAMP2IE
+ 1
+ 1
+
+
+ ITAMP1IE
+ ITAMP1IE
+ 16
+ 1
+
+
+ ITAMP3IE
+ ITAMP3IE
+ 18
+ 1
+
+
+ ITAMP4IE
+ ITAMP4IE
+ 19
+ 1
+
+
+ ITAMP5IE
+ ITAMP5IE
+ 20
+ 1
+
+
+ ITAMP6IE
+ ITAMP6IE
+ 21
+ 1
+
+
+
+
+ SR
+ SR
+ TAMP status register
+ 0x30
+ 0x20
+ read-only
+ 0x00000000
+
+
+ TAMP1F
+ TAMP1F
+ 0
+ 1
+
+
+ TAMP2F
+ TAMP2F
+ 1
+ 1
+
+
+ ITAMP1F
+ ITAMP1F
+ 16
+ 1
+
+
+ ITAMP3F
+ ITAMP3F
+ 18
+ 1
+
+
+ ITAMP4F
+ ITAMP4F
+ 19
+ 1
+
+
+ ITAMP5F
+ ITAMP5F
+ 20
+ 1
+
+
+ ITAMP6F
+ ITAMP6F
+ 21
+ 1
+
+
+ ITAMP7F
+ ITAMP7F
+ 22
+ 1
+
+
+
+
+ MISR
+ MISR
+ TAMP masked interrupt status
+ register
+ 0x34
+ 0x20
+ read-only
+ 0x00000000
+
+
+ TAMP1MF
+ TAMP1MF:
+ 0
+ 1
+
+
+ TAMP2MF
+ TAMP2MF
+ 1
+ 1
+
+
+ ITAMP1MF
+ ITAMP1MF
+ 16
+ 1
+
+
+ ITAMP3MF
+ ITAMP3MF
+ 18
+ 1
+
+
+ ITAMP4MF
+ ITAMP4MF
+ 19
+ 1
+
+
+ ITAMP5MF
+ ITAMP5MF
+ 20
+ 1
+
+
+ ITAMP6MF
+ ITAMP6MF
+ 21
+ 1
+
+
+
+
+ SCR
+ SCR
+ TAMP status clear register
+ 0x3C
+ 0x20
+ write-only
+ 0x00000000
+
+
+ CTAMP1F
+ CTAMP1F
+ 0
+ 1
+
+
+ CTAMP2F
+ CTAMP2F
+ 1
+ 1
+
+
+ CITAMP1F
+ CITAMP1F
+ 16
+ 1
+
+
+ CITAMP3F
+ CITAMP3F
+ 18
+ 1
+
+
+ CITAMP4F
+ CITAMP4F
+ 19
+ 1
+
+
+ CITAMP5F
+ CITAMP5F
+ 20
+ 1
+
+
+ CITAMP6F
+ CITAMP6F
+ 21
+ 1
+
+
+ CITAMP7F
+ CITAMP7F
+ 22
+ 1
+
+
+
+
+ BKP0R
+ BKP0R
+ TAMP backup register
+ 0x100
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP1R
+ BKP1R
+ TAMP backup register
+ 0x104
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP2R
+ BKP2R
+ TAMP backup register
+ 0x108
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP3R
+ BKP3R
+ TAMP backup register
+ 0x10C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ BKP4R
+ BKP4R
+ TAMP backup register
+ 0x110
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BKP
+ BKP
+ 0
+ 32
+
+
+
+
+ HWCFGR2
+ HWCFGR2
+ TAMP hardware configuration register
+ 2
+ 0x3EC
+ 0x20
+ read-only
+ 0x00000000
+
+
+ PTIONREG_OUT
+ PTIONREG_OUT
+ 0
+ 8
+
+
+ TRUST_ZONE
+ TRUST_ZONE
+ 8
+ 4
+
+
+
+
+ HWCFGR1
+ HWCFGR1
+ TAMP hardware configuration register
+ 1
+ 0x3F0
+ 0x20
+ read-only
+ 0x00000000
+
+
+ BACKUP_REGS
+ BACKUP_REGS
+ 0
+ 8
+
+
+ TAMPER
+ TAMPER
+ 8
+ 4
+
+
+ ACTIVE_TAMPER
+ ACTIVE_TAMPER
+ 12
+ 4
+
+
+ INT_TAMPER
+ INT_TAMPER
+ 16
+ 16
+
+
+
+
+ VERR
+ VERR
+ EXTI IP Version register
+ 0x3F4
+ 0x20
+ read-only
+ 0x00000000
+
+
+ MINREV
+ Minor Revision number
+ 0
+ 4
+
+
+ MAJREV
+ Major Revision number
+ 4
+ 4
+
+
+
+
+ IPIDR
+ IPIDR
+ EXTI Identification register
+ 0x3F8
+ 0x20
+ read-only
+ 0x00000000
+
+
+ IPID
+ IP Identification
+ 0
+ 32
+
+
+
+
+ SIDR
+ SIDR
+ EXTI Size ID register
+ 0x3FC
+ 0x20
+ read-only
+ 0x00000000
+
+
+ SID
+ Size Identification
+ 0
+ 32
+
+
+
+
+
+
+ I2C1
+ Inter-integrated circuit
+ I2C
+ 0x40005400
+
+ 0x0
+ 0x400
+ registers
+
+
+ I2C1
+ I2C1 global interrupt
+ 23
+
+
+
+ CR1
+ CR1
+ Control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PE
+ Peripheral enable
+ 0
+ 1
+
+
+ TXIE
+ TX Interrupt enable
+ 1
+ 1
+
+
+ RXIE
+ RX Interrupt enable
+ 2
+ 1
+
+
+ ADDRIE
+ Address match interrupt enable (slave
+ only)
+ 3
+ 1
+
+
+ NACKIE
+ Not acknowledge received interrupt
+ enable
+ 4
+ 1
+
+
+ STOPIE
+ STOP detection Interrupt
+ enable
+ 5
+ 1
+
+
+ TCIE
+ Transfer Complete interrupt
+ enable
+ 6
+ 1
+
+
+ ERRIE
+ Error interrupts enable
+ 7
+ 1
+
+
+ DNF
+ Digital noise filter
+ 8
+ 4
+
+
+ ANFOFF
+ Analog noise filter OFF
+ 12
+ 1
+
+
+ TXDMAEN
+ DMA transmission requests
+ enable
+ 14
+ 1
+
+
+ RXDMAEN
+ DMA reception requests
+ enable
+ 15
+ 1
+
+
+ SBC
+ Slave byte control
+ 16
+ 1
+
+
+ NOSTRETCH
+ Clock stretching disable
+ 17
+ 1
+
+
+ WUPEN
+ Wakeup from STOP enable
+ 18
+ 1
+
+
+ GCEN
+ General call enable
+ 19
+ 1
+
+
+ SMBHEN
+ SMBus Host address enable
+ 20
+ 1
+
+
+ SMBDEN
+ SMBus Device Default address
+ enable
+ 21
+ 1
+
+
+ ALERTEN
+ SMBUS alert enable
+ 22
+ 1
+
+
+ PECEN
+ PEC enable
+ 23
+ 1
+
+
+
+
+ CR2
+ CR2
+ Control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PECBYTE
+ Packet error checking byte
+ 26
+ 1
+
+
+ AUTOEND
+ Automatic end mode (master
+ mode)
+ 25
+ 1
+
+
+ RELOAD
+ NBYTES reload mode
+ 24
+ 1
+
+
+ NBYTES
+ Number of bytes
+ 16
+ 8
+
+
+ NACK
+ NACK generation (slave
+ mode)
+ 15
+ 1
+
+
+ STOP
+ Stop generation (master
+ mode)
+ 14
+ 1
+
+
+ START
+ Start generation
+ 13
+ 1
+
+
+ HEAD10R
+ 10-bit address header only read
+ direction (master receiver mode)
+ 12
+ 1
+
+
+ ADD10
+ 10-bit addressing mode (master
+ mode)
+ 11
+ 1
+
+
+ RD_WRN
+ Transfer direction (master
+ mode)
+ 10
+ 1
+
+
+ SADD
+ Slave address bit (master
+ mode)
+ 0
+ 10
+
+
+
+
+ OAR1
+ OAR1
+ Own address register 1
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OA1_0
+ Interface address
+ 0
+ 1
+
+
+ OA1_7_1
+ Interface address
+ 1
+ 7
+
+
+ OA1_8_9
+ Interface address
+ 8
+ 2
+
+
+ OA1MODE
+ Own Address 1 10-bit mode
+ 10
+ 1
+
+
+ OA1EN
+ Own Address 1 enable
+ 15
+ 1
+
+
+
+
+ OAR2
+ OAR2
+ Own address register 2
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OA2
+ Interface address
+ 1
+ 7
+
+
+ OA2MSK
+ Own Address 2 masks
+ 8
+ 3
+
+
+ OA2EN
+ Own Address 2 enable
+ 15
+ 1
+
+
+
+
+ TIMINGR
+ TIMINGR
+ Timing register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SCLL
+ SCL low period (master
+ mode)
+ 0
+ 8
+
+
+ SCLH
+ SCL high period (master
+ mode)
+ 8
+ 8
+
+
+ SDADEL
+ Data hold time
+ 16
+ 4
+
+
+ SCLDEL
+ Data setup time
+ 20
+ 4
+
+
+ PRESC
+ Timing prescaler
+ 28
+ 4
+
+
+
+
+ TIMEOUTR
+ TIMEOUTR
+ Status register 1
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TIMEOUTA
+ Bus timeout A
+ 0
+ 12
+
+
+ TIDLE
+ Idle clock timeout
+ detection
+ 12
+ 1
+
+
+ TIMOUTEN
+ Clock timeout enable
+ 15
+ 1
+
+
+ TIMEOUTB
+ Bus timeout B
+ 16
+ 12
+
+
+ TEXTEN
+ Extended clock timeout
+ enable
+ 31
+ 1
+
+
+
+
+ ISR
+ ISR
+ Interrupt and Status register
+ 0x18
+ 0x20
+ 0x00000001
+
+
+ ADDCODE
+ Address match code (Slave
+ mode)
+ 17
+ 7
+ read-only
+
+
+ DIR
+ Transfer direction (Slave
+ mode)
+ 16
+ 1
+ read-only
+
+
+ BUSY
+ Bus busy
+ 15
+ 1
+ read-only
+
+
+ ALERT
+ SMBus alert
+ 13
+ 1
+ read-only
+
+
+ TIMEOUT
+ Timeout or t_low detection
+ flag
+ 12
+ 1
+ read-only
+
+
+ PECERR
+ PEC Error in reception
+ 11
+ 1
+ read-only
+
+
+ OVR
+ Overrun/Underrun (slave
+ mode)
+ 10
+ 1
+ read-only
+
+
+ ARLO
+ Arbitration lost
+ 9
+ 1
+ read-only
+
+
+ BERR
+ Bus error
+ 8
+ 1
+ read-only
+
+
+ TCR
+ Transfer Complete Reload
+ 7
+ 1
+ read-only
+
+
+ TC
+ Transfer Complete (master
+ mode)
+ 6
+ 1
+ read-only
+
+
+ STOPF
+ Stop detection flag
+ 5
+ 1
+ read-only
+
+
+ NACKF
+ Not acknowledge received
+ flag
+ 4
+ 1
+ read-only
+
+
+ ADDR
+ Address matched (slave
+ mode)
+ 3
+ 1
+ read-only
+
+
+ RXNE
+ Receive data register not empty
+ (receivers)
+ 2
+ 1
+ read-only
+
+
+ TXIS
+ Transmit interrupt status
+ (transmitters)
+ 1
+ 1
+ read-write
+
+
+ TXE
+ Transmit data register empty
+ (transmitters)
+ 0
+ 1
+ read-write
+
+
+
+
+ ICR
+ ICR
+ Interrupt clear register
+ 0x1C
+ 0x20
+ write-only
+ 0x00000000
+
+
+ ALERTCF
+ Alert flag clear
+ 13
+ 1
+
+
+ TIMOUTCF
+ Timeout detection flag
+ clear
+ 12
+ 1
+
+
+ PECCF
+ PEC Error flag clear
+ 11
+ 1
+
+
+ OVRCF
+ Overrun/Underrun flag
+ clear
+ 10
+ 1
+
+
+ ARLOCF
+ Arbitration lost flag
+ clear
+ 9
+ 1
+
+
+ BERRCF
+ Bus error flag clear
+ 8
+ 1
+
+
+ STOPCF
+ Stop detection flag clear
+ 5
+ 1
+
+
+ NACKCF
+ Not Acknowledge flag clear
+ 4
+ 1
+
+
+ ADDRCF
+ Address Matched flag clear
+ 3
+ 1
+
+
+
+
+ PECR
+ PECR
+ PEC register
+ 0x20
+ 0x20
+ read-only
+ 0x00000000
+
+
+ PEC
+ Packet error checking
+ register
+ 0
+ 8
+
+
+
+
+ RXDR
+ RXDR
+ Receive data register
+ 0x24
+ 0x20
+ read-only
+ 0x00000000
+
+
+ RXDATA
+ 8-bit receive data
+ 0
+ 8
+
+
+
+
+ TXDR
+ TXDR
+ Transmit data register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TXDATA
+ 8-bit transmit data
+ 0
+ 8
+
+
+
+
+
+
+ I2C2
+ 0x40005800
+
+ I2C2
+ I2C2 global interrupt
+ 24
+
+
+
+ RTC
+ Real-time clock
+ RTC
+ 0x40002800
+
+ 0x0
+ 0x400
+ registers
+
+
+ RTC_STAMP
+ RTC and TAMP interrupts
+ 2
+
+
+
+ TR
+ TR
+ time register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PM
+ AM/PM notation
+ 22
+ 1
+
+
+ HT
+ Hour tens in BCD format
+ 20
+ 2
+
+
+ HU
+ Hour units in BCD format
+ 16
+ 4
+
+
+ MNT
+ Minute tens in BCD format
+ 12
+ 3
+
+
+ MNU
+ Minute units in BCD format
+ 8
+ 4
+
+
+ ST
+ Second tens in BCD format
+ 4
+ 3
+
+
+ SU
+ Second units in BCD format
+ 0
+ 4
+
+
+
+
+ DR
+ DR
+ date register
+ 0x4
+ 0x20
+ read-write
+ 0x00002101
+
+
+ YT
+ Year tens in BCD format
+ 20
+ 4
+
+
+ YU
+ Year units in BCD format
+ 16
+ 4
+
+
+ WDU
+ Week day units
+ 13
+ 3
+
+
+ MT
+ Month tens in BCD format
+ 12
+ 1
+
+
+ MU
+ Month units in BCD format
+ 8
+ 4
+
+
+ DT
+ Date tens in BCD format
+ 4
+ 2
+
+
+ DU
+ Date units in BCD format
+ 0
+ 4
+
+
+
+
+ SSR
+ SSR
+ sub second register
+ 0x8
+ 0x20
+ read-only
+ 0x00000000
+
+
+ SS
+ Sub second value
+ 0
+ 16
+
+
+
+
+ ICSR
+ ICSR
+ initialization and status
+ register
+ 0xC
+ 0x20
+ 0x00000007
+
+
+ ALRAWF
+ Alarm A write flag
+ 0
+ 1
+ read-only
+
+
+ ALRBWF
+ Alarm B write flag
+ 1
+ 1
+ read-only
+
+
+ WUTWF
+ Wakeup timer write flag
+ 2
+ 1
+ read-only
+
+
+ SHPF
+ Shift operation pending
+ 3
+ 1
+ read-write
+
+
+ INITS
+ Initialization status flag
+ 4
+ 1
+ read-only
+
+
+ RSF
+ Registers synchronization
+ flag
+ 5
+ 1
+ read-write
+
+
+ INITF
+ Initialization flag
+ 6
+ 1
+ read-only
+
+
+ INIT
+ Initialization mode
+ 7
+ 1
+ read-write
+
+
+ RECALPF
+ Recalibration pending Flag
+ 16
+ 1
+ read-only
+
+
+
+
+ PRER
+ PRER
+ prescaler register
+ 0x10
+ 0x20
+ read-write
+ 0x007F00FF
+
+
+ PREDIV_A
+ Asynchronous prescaler
+ factor
+ 16
+ 7
+
+
+ PREDIV_S
+ Synchronous prescaler
+ factor
+ 0
+ 15
+
+
+
+
+ WUTR
+ WUTR
+ wakeup timer register
+ 0x14
+ 0x20
+ read-write
+ 0x0000FFFF
+
+
+ WUT
+ Wakeup auto-reload value
+ bits
+ 0
+ 16
+
+
+
+
+ CR
+ CR
+ control register
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ WUCKSEL
+ WUCKSEL
+ 0
+ 3
+
+
+ TSEDGE
+ TSEDGE
+ 3
+ 1
+
+
+ REFCKON
+ REFCKON
+ 4
+ 1
+
+
+ BYPSHAD
+ BYPSHAD
+ 5
+ 1
+
+
+ FMT
+ FMT
+ 6
+ 1
+
+
+ ALRAE
+ ALRAE
+ 8
+ 1
+
+
+ ALRBE
+ ALRBE
+ 9
+ 1
+
+
+ WUTE
+ WUTE
+ 10
+ 1
+
+
+ TSE
+ TSE
+ 11
+ 1
+
+
+ ALRAIE
+ ALRAIE
+ 12
+ 1
+
+
+ ALRBIE
+ ALRBIE
+ 13
+ 1
+
+
+ WUTIE
+ WUTIE
+ 14
+ 1
+
+
+ TSIE
+ TSIE
+ 15
+ 1
+
+
+ ADD1H
+ ADD1H
+ 16
+ 1
+
+
+ SUB1H
+ SUB1H
+ 17
+ 1
+
+
+ BKP
+ BKP
+ 18
+ 1
+
+
+ COSEL
+ COSEL
+ 19
+ 1
+
+
+ POL
+ POL
+ 20
+ 1
+
+
+ OSEL
+ OSEL
+ 21
+ 2
+
+
+ COE
+ COE
+ 23
+ 1
+
+
+ ITSE
+ ITSE
+ 24
+ 1
+
+
+ TAMPTS
+ TAMPTS
+ 25
+ 1
+
+
+ TAMPOE
+ TAMPOE
+ 26
+ 1
+
+
+ TAMPALRM_PU
+ TAMPALRM_PU
+ 29
+ 1
+
+
+ TAMPALRM_TYPE
+ TAMPALRM_TYPE
+ 30
+ 1
+
+
+ OUT2EN
+ OUT2EN
+ 31
+ 1
+
+
+
+
+ WPR
+ WPR
+ write protection register
+ 0x24
+ 0x20
+ write-only
+ 0x00000000
+
+
+ KEY
+ Write protection key
+ 0
+ 8
+
+
+
+
+ CALR
+ CALR
+ calibration register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CALP
+ Increase frequency of RTC by 488.5
+ ppm
+ 15
+ 1
+
+
+ CALW8
+ Use an 8-second calibration cycle
+ period
+ 14
+ 1
+
+
+ CALW16
+ Use a 16-second calibration cycle
+ period
+ 13
+ 1
+
+
+ CALM
+ Calibration minus
+ 0
+ 9
+
+
+
+
+ SHIFTR
+ SHIFTR
+ shift control register
+ 0x2C
+ 0x20
+ write-only
+ 0x00000000
+
+
+ ADD1S
+ Add one second
+ 31
+ 1
+
+
+ SUBFS
+ Subtract a fraction of a
+ second
+ 0
+ 15
+
+
+
+
+ TSTR
+ TSTR
+ time stamp time register
+ 0x30
+ 0x20
+ read-only
+ 0x00000000
+
+
+ SU
+ Second units in BCD format
+ 0
+ 4
+
+
+ ST
+ Second tens in BCD format
+ 4
+ 3
+
+
+ MNU
+ Minute units in BCD format
+ 8
+ 4
+
+
+ MNT
+ Minute tens in BCD format
+ 12
+ 3
+
+
+ HU
+ Hour units in BCD format
+ 16
+ 4
+
+
+ HT
+ Hour tens in BCD format
+ 20
+ 2
+
+
+ PM
+ AM/PM notation
+ 22
+ 1
+
+
+
+
+ TSDR
+ TSDR
+ time stamp date register
+ 0x34
+ 0x20
+ read-only
+ 0x00000000
+
+
+ WDU
+ Week day units
+ 13
+ 3
+
+
+ MT
+ Month tens in BCD format
+ 12
+ 1
+
+
+ MU
+ Month units in BCD format
+ 8
+ 4
+
+
+ DT
+ Date tens in BCD format
+ 4
+ 2
+
+
+ DU
+ Date units in BCD format
+ 0
+ 4
+
+
+
+
+ TSSSR
+ TSSSR
+ timestamp sub second register
+ 0x38
+ 0x20
+ read-only
+ 0x00000000
+
+
+ SS
+ Sub second value
+ 0
+ 16
+
+
+
+
+ ALRMAR
+ ALRMAR
+ alarm A register
+ 0x40
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MSK4
+ Alarm A date mask
+ 31
+ 1
+
+
+ WDSEL
+ Week day selection
+ 30
+ 1
+
+
+ DT
+ Date tens in BCD format
+ 28
+ 2
+
+
+ DU
+ Date units or day in BCD
+ format
+ 24
+ 4
+
+
+ MSK3
+ Alarm A hours mask
+ 23
+ 1
+
+
+ PM
+ AM/PM notation
+ 22
+ 1
+
+
+ HT
+ Hour tens in BCD format
+ 20
+ 2
+
+
+ HU
+ Hour units in BCD format
+ 16
+ 4
+
+
+ MSK2
+ Alarm A minutes mask
+ 15
+ 1
+
+
+ MNT
+ Minute tens in BCD format
+ 12
+ 3
+
+
+ MNU
+ Minute units in BCD format
+ 8
+ 4
+
+
+ MSK1
+ Alarm A seconds mask
+ 7
+ 1
+
+
+ ST
+ Second tens in BCD format
+ 4
+ 3
+
+
+ SU
+ Second units in BCD format
+ 0
+ 4
+
+
+
+
+ ALRMASSR
+ ALRMASSR
+ alarm A sub second register
+ 0x44
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MASKSS
+ Mask the most-significant bits starting
+ at this bit
+ 24
+ 4
+
+
+ SS
+ Sub seconds value
+ 0
+ 15
+
+
+
+
+ ALRMBR
+ ALRMBR
+ alarm B register
+ 0x48
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MSK4
+ Alarm B date mask
+ 31
+ 1
+
+
+ WDSEL
+ Week day selection
+ 30
+ 1
+
+
+ DT
+ Date tens in BCD format
+ 28
+ 2
+
+
+ DU
+ Date units or day in BCD
+ format
+ 24
+ 4
+
+
+ MSK3
+ Alarm B hours mask
+ 23
+ 1
+
+
+ PM
+ AM/PM notation
+ 22
+ 1
+
+
+ HT
+ Hour tens in BCD format
+ 20
+ 2
+
+
+ HU
+ Hour units in BCD format
+ 16
+ 4
+
+
+ MSK2
+ Alarm B minutes mask
+ 15
+ 1
+
+
+ MNT
+ Minute tens in BCD format
+ 12
+ 3
+
+
+ MNU
+ Minute units in BCD format
+ 8
+ 4
+
+
+ MSK1
+ Alarm B seconds mask
+ 7
+ 1
+
+
+ ST
+ Second tens in BCD format
+ 4
+ 3
+
+
+ SU
+ Second units in BCD format
+ 0
+ 4
+
+
+
+
+ ALRMBSSR
+ ALRMBSSR
+ alarm B sub second register
+ 0x4C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MASKSS
+ Mask the most-significant bits starting
+ at this bit
+ 24
+ 4
+
+
+ SS
+ Sub seconds value
+ 0
+ 15
+
+
+
+
+ SR
+ SR
+ status register
+ 0x50
+ 0x20
+ read-only
+ 0x00000000
+
+
+ ALRAF
+ ALRAF
+ 0
+ 1
+
+
+ ALRBF
+ ALRBF
+ 1
+ 1
+
+
+ WUTF
+ WUTF
+ 2
+ 1
+
+
+ TSF
+ TSF
+ 3
+ 1
+
+
+ TSOVF
+ TSOVF
+ 4
+ 1
+
+
+ ITSF
+ ITSF
+ 5
+ 1
+
+
+
+
+ MISR
+ MISR
+ masked interrupt status
+ register
+ 0x54
+ 0x20
+ read-only
+ 0x00000000
+
+
+ ALRAMF
+ ALRAMF
+ 0
+ 1
+
+
+ ALRBMF
+ ALRBMF
+ 1
+ 1
+
+
+ WUTMF
+ WUTMF
+ 2
+ 1
+
+
+ TSMF
+ TSMF
+ 3
+ 1
+
+
+ TSOVMF
+ TSOVMF
+ 4
+ 1
+
+
+ ITSMF
+ ITSMF
+ 5
+ 1
+
+
+
+
+ SCR
+ SCR
+ status clear register
+ 0x5C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CALRAF
+ CALRAF
+ 0
+ 1
+
+
+ CALRBF
+ CALRBF
+ 1
+ 1
+
+
+ CWUTF
+ CWUTF
+ 2
+ 1
+
+
+ CTSF
+ CTSF
+ 3
+ 1
+
+
+ CTSOVF
+ CTSOVF
+ 4
+ 1
+
+
+ CITSF
+ CITSF
+ 5
+ 1
+
+
+
+
+ HWCFGR
+ HWCFGR
+ hardware configuration
+ register
+ 0x3F0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ALARMB
+ ALARMB
+ 0
+ 4
+
+
+ WAKEUP
+ WAKEUP
+ 4
+ 4
+
+
+ SMOOTH_CALIB
+ SMOOTH_CALIB
+ 8
+ 4
+
+
+ TIMESTAMP
+ TIMESTAMP
+ 12
+ 4
+
+
+ OPTIONREG_OUT
+ OPTIONREG_OUT
+ 16
+ 8
+
+
+ TRUST_ZONE
+ TRUST_ZONE
+ 24
+ 4
+
+
+
+
+ VERR
+ VERR
+ EXTI IP Version register
+ 0x3F4
+ 0x20
+ read-only
+ 0x00000010
+
+
+ MINREV
+ Minor Revision number
+ 0
+ 4
+
+
+ MAJREV
+ Major Revision number
+ 4
+ 4
+
+
+
+
+ IPIDR
+ IPIDR
+ EXTI Identification register
+ 0x3F8
+ 0x20
+ read-only
+ 0x00120033
+
+
+ IPID
+ IP Identification
+ 0
+ 32
+
+
+
+
+ SIDR
+ SIDR
+ EXTI Size ID register
+ 0x3FC
+ 0x20
+ read-only
+ 0xA3C5DD01
+
+
+ SID
+ Size Identification
+ 0
+ 32
+
+
+
+
+
+
+ TIM14
+ General purpose timers
+ TIM
+ 0x40002000
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM14
+ TIM14 global interrupt
+ 19
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ UIFREMAP
+ UIF status bit remapping
+ 11
+ 1
+
+
+ CKD
+ Clock division
+ 8
+ 2
+
+
+ ARPE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ OPM
+ One-pulse mode
+ 3
+ 1
+
+
+ URS
+ Update request source
+ 2
+ 1
+
+
+ UDIS
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ DIER
+ DIER
+ DMA/Interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC1IE
+ Capture/Compare 1 interrupt
+ enable
+ 1
+ 1
+
+
+ UIE
+ Update interrupt enable
+ 0
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC1OF
+ Capture/Compare 1 overcapture
+ flag
+ 9
+ 1
+
+
+ CC1IF
+ Capture/compare 1 interrupt
+ flag
+ 1
+ 1
+
+
+ UIF
+ Update interrupt flag
+ 0
+ 1
+
+
+
+
+ EGR
+ EGR
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ CC1G
+ Capture/compare 1
+ generation
+ 1
+ 1
+
+
+ UG
+ Update generation
+ 0
+ 1
+
+
+
+
+ CCMR1_Output
+ CCMR1_Output
+ capture/compare mode register 1 (output
+ mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CC1S
+ CC1S
+ 0
+ 2
+
+
+ OC1FE
+ OC1FE
+ 2
+ 1
+
+
+ OC1PE
+ OC1PE
+ 3
+ 1
+
+
+ OC1M
+ OC1M
+ 4
+ 3
+ OC1M read-write Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy 3 ForceInactive OCyREF is forced low 4 ForceActive OCyREF is forced high 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active 6 PwmMode2 Inversely to PwmMode1 7
+
+ OC1CE
+ OC1CE
+ 7
+ 1
+
+
+ OC1M_3
+ Output Compare 1 mode - bit
+ 3
+ 16
+ 1
+
+
+
+
+ CCMR1_Input
+ CCMR1_Input
+ capture/compare mode register 1 (input
+ mode)
+ CCMR1_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IC1F
+ Input capture 1 filter
+ 4
+ 4
+
+
+ ICPCS
+ Input capture 1 prescaler
+ 2
+ 2
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+
+
+ CCER
+ CCER
+ capture/compare enable
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC1NP
+ Capture/Compare 1 output
+ Polarity
+ 3
+ 1
+
+
+ CC1P
+ Capture/Compare 1 output
+ Polarity
+ 1
+ 1
+
+
+ CC1E
+ Capture/Compare 1 output
+ enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ low counter value
+ 0
+ 16
+
+
+ UIFCPY
+ UIF Copy
+ 31
+ 1
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ ARR
+ ARR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ARR
+ Low Auto-reload value
+ 0
+ 16
+
+
+
+
+ CCR1
+ CCR1
+ capture/compare register 1
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR1
+ Low Capture/Compare 1
+ value
+ 0
+ 16
+
+
+
+
+ TISEL
+ TISEL
+ TIM timer input selection
+ register
+ 0x68
+ 0x20
+ read-write
+ 0x0000
+
+
+ TISEL
+ TI1[0] to TI1[15] input
+ selection
+ 0
+ 4
+
+
+
+
+
+
+ TIM6
+ Basic timers
+ TIM
+ 0x40001000
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM6
+ TIM6 global interrupt
+ 17
+
+ TIM7 TIM7 global interrupt 18
+
+ CR1
+ CR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ UIFREMAP
+ UIF status bit remapping
+ 11
+ 1
+
+
+ ARPE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ OPM
+ One-pulse mode
+ 3
+ 1
+
+
+ URS
+ Update request source
+ 2
+ 1
+
+
+ UDIS
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ MMS
+ Master mode selection
+ 4
+ 3
+
+
+
+
+ DIER
+ DIER
+ DMA/Interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ UDE
+ Update DMA request enable
+ 8
+ 1
+
+
+ UIE
+ Update interrupt enable
+ 0
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ UIF
+ Update interrupt flag
+ 0
+ 1
+
+
+
+
+ EGR
+ EGR
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ UG
+ Update generation
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ Low counter value
+ 0
+ 16
+
+
+ UIFCPY
+ UIF Copy
+ 31
+ 1
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ ARR
+ ARR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ARR
+ Low Auto-reload value
+ 0
+ 16
+
+
+
+
+
+
+ TIM3
+ General-purpose-timers
+ TIM
+ 0x40000400
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM3
+ TIM3 global interrupt
+ 16
+
+
+
+ CR1
+ CR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ UIFREMAP
+ UIF status bit remapping
+ 11
+ 1
+
+
+ CKD
+ Clock division
+ 8
+ 2
+
+
+ ARPE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ CMS
+ Center-aligned mode
+ selection
+ 5
+ 2
+
+
+ DIR
+ Direction
+ 4
+ 1
+
+
+ OPM
+ One-pulse mode
+ 3
+ 1
+
+
+ URS
+ Update request source
+ 2
+ 1
+
+
+ UDIS
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ CR2
+ CR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ TI1S
+ TI1 selection
+ 7
+ 1
+
+
+ MMS
+ Master mode selection
+ 4
+ 3
+
+
+ CCDS
+ Capture/compare DMA
+ selection
+ 3
+ 1
+
+
+
+
+ SMCR
+ SMCR
+ slave mode control register
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ TS_4_3
+ Trigger selection
+ 20
+ 2
+
+
+ SMS_3
+ Slave mode selection - bit
+ 3
+ 16
+ 1
+
+
+ ETP
+ External trigger polarity
+ 15
+ 1
+
+
+ ECE
+ External clock enable
+ 14
+ 1
+
+
+ ETPS
+ External trigger prescaler
+ 12
+ 2
+
+
+ ETF
+ External trigger filter
+ 8
+ 4
+
+
+ MSM
+ Master/Slave mode
+ 7
+ 1
+
+
+ TS
+ Trigger selection
+ 4
+ 3
+
+
+ OCCS
+ OCREF clear selection
+ 3
+ 1
+
+
+ SMS
+ Slave mode selection
+ 0
+ 3
+
+
+
+
+ DIER
+ DIER
+ DMA/Interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ TDE
+ Trigger DMA request enable
+ 14
+ 1
+
+
+ CC4DE
+ Capture/Compare 4 DMA request
+ enable
+ 12
+ 1
+
+
+ CC3DE
+ Capture/Compare 3 DMA request
+ enable
+ 11
+ 1
+
+
+ CC2DE
+ Capture/Compare 2 DMA request
+ enable
+ 10
+ 1
+
+
+ CC1DE
+ Capture/Compare 1 DMA request
+ enable
+ 9
+ 1
+
+
+ UDE
+ Update DMA request enable
+ 8
+ 1
+
+
+ TIE
+ Trigger interrupt enable
+ 6
+ 1
+
+
+ CC4IE
+ Capture/Compare 4 interrupt
+ enable
+ 4
+ 1
+
+
+ CC3IE
+ Capture/Compare 3 interrupt
+ enable
+ 3
+ 1
+
+
+ CC2IE
+ Capture/Compare 2 interrupt
+ enable
+ 2
+ 1
+
+
+ CC1IE
+ Capture/Compare 1 interrupt
+ enable
+ 1
+ 1
+
+
+ UIE
+ Update interrupt enable
+ 0
+ 1
+
+
+
+
+ SR
+ SR
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC4OF
+ Capture/Compare 4 overcapture
+ flag
+ 12
+ 1
+
+
+ CC3OF
+ Capture/Compare 3 overcapture
+ flag
+ 11
+ 1
+
+
+ CC2OF
+ Capture/compare 2 overcapture
+ flag
+ 10
+ 1
+
+
+ CC1OF
+ Capture/Compare 1 overcapture
+ flag
+ 9
+ 1
+
+
+ TIF
+ Trigger interrupt flag
+ 6
+ 1
+
+
+ CC4IF
+ Capture/Compare 4 interrupt
+ flag
+ 4
+ 1
+
+
+ CC3IF
+ Capture/Compare 3 interrupt
+ flag
+ 3
+ 1
+
+
+ CC2IF
+ Capture/Compare 2 interrupt
+ flag
+ 2
+ 1
+
+
+ CC1IF
+ Capture/compare 1 interrupt
+ flag
+ 1
+ 1
+
+
+ UIF
+ Update interrupt flag
+ 0
+ 1
+
+
+
+
+ EGR
+ EGR
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ TG
+ Trigger generation
+ 6
+ 1
+
+
+ CC4G
+ Capture/compare 4
+ generation
+ 4
+ 1
+
+
+ CC3G
+ Capture/compare 3
+ generation
+ 3
+ 1
+
+
+ CC2G
+ Capture/compare 2
+ generation
+ 2
+ 1
+
+
+ CC1G
+ Capture/compare 1
+ generation
+ 1
+ 1
+
+
+ UG
+ Update generation
+ 0
+ 1
+
+
+
+
+ CCMR1_Output
+ CCMR1_Output
+ capture/compare mode register 1 (output
+ mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OC2M_3
+ Output Compare 2 mode - bit
+ 3
+ 24
+ 1
+
+
+ OC1M_3
+ Output Compare 1 mode - bit
+ 3
+ 16
+ 1
+ OC1M_3 read-write Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1
+
+ OC2CE
+ Output compare 2 clear
+ enable
+ 15
+ 1
+
+
+ OC2M
+ Output compare 2 mode
+ 12
+ 3
+
+
+ OC2PE
+ Output compare 2 preload
+ enable
+ 11
+ 1
+
+
+ OC2FE
+ Output compare 2 fast
+ enable
+ 10
+ 1
+
+
+ CC2S
+ Capture/Compare 2
+ selection
+ 8
+ 2
+
+
+ OC1CE
+ Output compare 1 clear
+ enable
+ 7
+ 1
+
+
+ OC1M
+ Output compare 1 mode
+ 4
+ 3
+ OC1M read-write Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7
+
+ OC1PE
+ Output compare 1 preload
+ enable
+ 3
+ 1
+
+
+ OC1FE
+ Output compare 1 fast
+ enable
+ 2
+ 1
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+
+
+ CCMR1_Input
+ CCMR1_Input
+ capture/compare mode register 1 (input
+ mode)
+ CCMR1_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IC2F
+ Input capture 2 filter
+ 12
+ 4
+
+
+ IC2PSC
+ Input capture 2 prescaler
+ 10
+ 2
+
+
+ CC2S
+ Capture/compare 2
+ selection
+ 8
+ 2
+
+
+ IC1F
+ Input capture 1 filter
+ 4
+ 4
+
+
+ IC1PSC
+ Input capture 1 prescaler
+ 2
+ 2
+
+
+ CC1S
+ Capture/Compare 1
+ selection
+ 0
+ 2
+
+
+
+
+ CCMR2_Output
+ CCMR2_Output
+ capture/compare mode register 2 (output
+ mode)
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OC4M_3
+ Output Compare 4 mode - bit
+ 3
+ 24
+ 1
+
+
+ OC3M_3
+ Output Compare 3 mode - bit
+ 3
+ 16
+ 1
+ OC3M_3 read-write Normal Normal output compare mode (modes 0-7) 0 Extended Extended output compare mode (modes 7-15) 1
+
+ OC4CE
+ Output compare 4 clear
+ enable
+ 15
+ 1
+
+
+ OC4M
+ Output compare 4 mode
+ 12
+ 3
+
+
+ OC4PE
+ Output compare 4 preload
+ enable
+ 11
+ 1
+
+
+ OC4FE
+ Output compare 4 fast
+ enable
+ 10
+ 1
+
+
+ CC4S
+ Capture/Compare 4
+ selection
+ 8
+ 2
+
+
+ OC3CE
+ Output compare 3 clear
+ enable
+ 7
+ 1
+
+
+ OC3M
+ Output compare 3 mode
+ 4
+ 3
+ OC3M read-write Frozen The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive 0 ActiveOnMatch Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1 1 InactiveOnMatch Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved 2 Toggle OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved 3 ForceInactive OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF 4 ForceActive OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF 5 PwmMode1 In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down 6 PwmMode2 Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1 7
+
+ OC3PE
+ Output compare 3 preload
+ enable
+ 3
+ 1
+
+
+ OC3FE
+ Output compare 3 fast
+ enable
+ 2
+ 1
+
+
+ CC3S
+ Capture/Compare 3
+ selection
+ 0
+ 2
+
+
+
+
+ CCMR2_Input
+ CCMR2_Input
+ capture/compare mode register 2 (input
+ mode)
+ CCMR2_Output
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IC4F
+ Input capture 4 filter
+ 12
+ 4
+
+
+ IC4PSC
+ Input capture 4 prescaler
+ 10
+ 2
+
+
+ CC4S
+ Capture/Compare 4
+ selection
+ 8
+ 2
+
+
+ IC3F
+ Input capture 3 filter
+ 4
+ 4
+
+
+ IC3PSC
+ Input capture 3 prescaler
+ 2
+ 2
+
+
+ CC3S
+ Capture/Compare 3
+ selection
+ 0
+ 2
+
+
+
+
+ CCER
+ CCER
+ capture/compare enable
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CC4NP
+ Capture/Compare 4 output
+ Polarity
+ 15
+ 1
+
+
+ CC4P
+ Capture/Compare 3 output
+ Polarity
+ 13
+ 1
+
+
+ CC4E
+ Capture/Compare 4 output
+ enable
+ 12
+ 1
+
+
+ CC3NP
+ Capture/Compare 3 output
+ Polarity
+ 11
+ 1
+
+
+ CC3P
+ Capture/Compare 3 output
+ Polarity
+ 9
+ 1
+
+
+ CC3E
+ Capture/Compare 3 output
+ enable
+ 8
+ 1
+
+
+ CC2NP
+ Capture/Compare 2 output
+ Polarity
+ 7
+ 1
+
+
+ CC2P
+ Capture/Compare 2 output
+ Polarity
+ 5
+ 1
+
+
+ CC2E
+ Capture/Compare 2 output
+ enable
+ 4
+ 1
+
+
+ CC1NP
+ Capture/Compare 1 output
+ Polarity
+ 3
+ 1
+
+
+ CC1P
+ Capture/Compare 1 output
+ Polarity
+ 1
+ 1
+
+
+ CC1E
+ Capture/Compare 1 output
+ enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT_H
+ High counter value (TIM2
+ only)
+ 16
+ 16
+
+
+ CNT_L
+ Low counter value
+ 0
+ 16
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ ARR
+ ARR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ARR_H
+ High Auto-reload value (TIM2
+ only)
+ 16
+ 16
+
+
+ ARR_L
+ Low Auto-reload value
+ 0
+ 16
+
+
+
+
+ CCR1
+ CCR1
+ capture/compare register 1
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR1_H
+ High Capture/Compare 1 value (TIM2
+ only)
+ 16
+ 16
+
+
+ CCR1_L
+ Low Capture/Compare 1
+ value
+ 0
+ 16
+
+
+
+
+ CCR2
+ CCR2
+ capture/compare register 2
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR2_H
+ High Capture/Compare 2 value (TIM2
+ only)
+ 16
+ 16
+
+
+ CCR2_L
+ Low Capture/Compare 2
+ value
+ 0
+ 16
+
+
+
+
+ CCR3
+ CCR3
+ capture/compare register 3
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR3_H
+ High Capture/Compare value (TIM2
+ only)
+ 16
+ 16
+
+
+ CCR3_L
+ Low Capture/Compare value
+ 0
+ 16
+
+
+
+
+ CCR4
+ CCR4
+ capture/compare register 4
+ 0x40
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CCR4_H
+ High Capture/Compare value (TIM2
+ only)
+ 16
+ 16
+
+
+ CCR4_L
+ Low Capture/Compare value
+ 0
+ 16
+
+
+
+
+ DCR
+ DCR
+ DMA control register
+ 0x48
+ 0x20
+ read-write
+ 0x0000
+
+
+ DBL
+ DMA burst length
+ 8
+ 5
+
+
+ DBA
+ DMA base address
+ 0
+ 5
+
+
+
+
+ DMAR
+ DMAR
+ DMA address for full transfer
+ 0x4C
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMAB
+ DMA register for burst
+ accesses
+ 0
+ 16
+
+
+
+
+ OR1
+ OR1
+ TIM option register
+ 0x50
+ 0x20
+ read-write
+ 0x0000
+
+
+ IOCREF_CLR
+ IOCREF_CLR
+ 0
+ 1
+
+
+
+
+ AF1
+ AF1
+ TIM alternate function option register
+ 1
+ 0x60
+ 0x20
+ read-write
+ 0x0000
+
+
+ ETRSEL
+ External trigger source
+ selection
+ 14
+ 4
+
+
+
+
+ TISEL
+ TISEL
+ TIM alternate function option register
+ 1
+ 0x68
+ 0x20
+ read-write
+ 0x0000
+
+
+ TI1SEL
+ TI1SEL
+ 0
+ 4
+
+
+ TI2SEL
+ TI2SEL
+ 8
+ 4
+
+
+
+
+
+
+ NVIC
+ Nested Vectored Interrupt
+ Controller
+ NVIC
+ 0xE000E100
+
+ 0x0
+ 0x33D
+ registers
+
+
+
+ ISER
+ ISER
+ Interrupt Set Enable Register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ICER
+ ICER
+ Interrupt Clear Enable
+ Register
+ 0x80
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ISPR
+ ISPR
+ Interrupt Set-Pending Register
+ 0x100
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ICPR
+ ICPR
+ Interrupt Clear-Pending
+ Register
+ 0x180
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ IPR0
+ IPR0
+ Interrupt Priority Register 0
+ 0x300
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_0
+ priority for interrupt 0
+ 0
+ 8
+
+
+ PRI_1
+ priority for interrupt 1
+ 8
+ 8
+
+
+ PRI_2
+ priority for interrupt 2
+ 16
+ 8
+
+
+ PRI_3
+ priority for interrupt 3
+ 24
+ 8
+
+
+
+
+ IPR1
+ IPR1
+ Interrupt Priority Register 1
+ 0x304
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_4
+ priority for interrupt n
+ 0
+ 8
+
+
+ PRI_5
+ priority for interrupt n
+ 8
+ 8
+
+
+ PRI_6
+ priority for interrupt n
+ 16
+ 8
+
+
+ PRI_7
+ priority for interrupt n
+ 24
+ 8
+
+
+
+
+ IPR2
+ IPR2
+ Interrupt Priority Register 2
+ 0x308
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_8
+ priority for interrupt n
+ 0
+ 8
+
+
+ PRI_9
+ priority for interrupt n
+ 8
+ 8
+
+
+ PRI_10
+ priority for interrupt n
+ 16
+ 8
+
+
+ PRI_11
+ priority for interrupt n
+ 24
+ 8
+
+
+
+
+ IPR3
+ IPR3
+ Interrupt Priority Register 3
+ 0x30C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_12
+ priority for interrupt n
+ 0
+ 8
+
+
+ PRI_13
+ priority for interrupt n
+ 8
+ 8
+
+
+ PRI_14
+ priority for interrupt n
+ 16
+ 8
+
+
+ PRI_15
+ priority for interrupt n
+ 24
+ 8
+
+
+
+
+ IPR4
+ IPR4
+ Interrupt Priority Register 4
+ 0x310
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_16
+ priority for interrupt n
+ 0
+ 8
+
+
+ PRI_17
+ priority for interrupt n
+ 8
+ 8
+
+
+ PRI_18
+ priority for interrupt n
+ 16
+ 8
+
+
+ PRI_19
+ priority for interrupt n
+ 24
+ 8
+
+
+
+
+ IPR5
+ IPR5
+ Interrupt Priority Register 5
+ 0x314
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_20
+ priority for interrupt n
+ 0
+ 8
+
+
+ PRI_21
+ priority for interrupt n
+ 8
+ 8
+
+
+ PRI_22
+ priority for interrupt n
+ 16
+ 8
+
+
+ PRI_23
+ priority for interrupt n
+ 24
+ 8
+
+
+
+
+ IPR6
+ IPR6
+ Interrupt Priority Register 6
+ 0x318
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_24
+ priority for interrupt n
+ 0
+ 8
+
+
+ PRI_25
+ priority for interrupt n
+ 8
+ 8
+
+
+ PRI_26
+ priority for interrupt n
+ 16
+ 8
+
+
+ PRI_27
+ priority for interrupt n
+ 24
+ 8
+
+
+
+
+ IPR7
+ IPR7
+ Interrupt Priority Register 7
+ 0x31C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_28
+ priority for interrupt n
+ 0
+ 8
+
+
+ PRI_29
+ priority for interrupt n
+ 8
+ 8
+
+
+ PRI_30
+ priority for interrupt n
+ 16
+ 8
+
+
+ PRI_31
+ priority for interrupt n
+ 24
+ 8
+
+
+
+
+
+
+ MPU
+ Memory protection unit
+ MPU
+ 0xE000ED90
+
+ 0x0
+ 0x15
+ registers
+
+
+
+ TYPER
+ TYPER
+ MPU type register
+ 0x0
+ 0x20
+ read-only
+ 0X00000800
+
+
+ SEPARATE
+ Separate flag
+ 0
+ 1
+
+
+ DREGION
+ Number of MPU data regions
+ 8
+ 8
+
+
+ IREGION
+ Number of MPU instruction
+ regions
+ 16
+ 8
+
+
+
+
+ CTRL
+ CTRL
+ MPU control register
+ 0x4
+ 0x20
+ read-only
+ 0X00000000
+
+
+ ENABLE
+ Enables the MPU
+ 0
+ 1
+
+
+ HFNMIENA
+ Enables the operation of MPU during hard
+ fault
+ 1
+ 1
+
+
+ PRIVDEFENA
+ Enable priviliged software access to
+ default memory map
+ 2
+ 1
+
+
+
+
+ RNR
+ RNR
+ MPU region number register
+ 0x8
+ 0x20
+ read-write
+ 0X00000000
+
+
+ REGION
+ MPU region
+ 0
+ 8
+
+
+
+
+ RBAR
+ RBAR
+ MPU region base address
+ register
+ 0xC
+ 0x20
+ read-write
+ 0X00000000
+
+
+ REGION
+ MPU region field
+ 0
+ 4
+
+
+ VALID
+ MPU region number valid
+ 4
+ 1
+
+
+ ADDR
+ Region base address field
+ 5
+ 27
+
+
+
+
+ RASR
+ RASR
+ MPU region attribute and size
+ register
+ 0x10
+ 0x20
+ read-write
+ 0X00000000
+
+
+ ENABLE
+ Region enable bit.
+ 0
+ 1
+
+
+ SIZE
+ Size of the MPU protection
+ region
+ 1
+ 5
+
+
+ SRD
+ Subregion disable bits
+ 8
+ 8
+
+
+ B
+ memory attribute
+ 16
+ 1
+
+
+ C
+ memory attribute
+ 17
+ 1
+
+
+ S
+ Shareable memory attribute
+ 18
+ 1
+
+
+ TEX
+ memory attribute
+ 19
+ 3
+
+
+ AP
+ Access permission
+ 24
+ 3
+
+
+ XN
+ Instruction access disable
+ bit
+ 28
+ 1
+
+
+
+
+
+
+ STK
+ SysTick timer
+ STK
+ 0xE000E010
+
+ 0x0
+ 0x11
+ registers
+
+
+
+ CSR
+ CSR
+ SysTick control and status
+ register
+ 0x0
+ 0x20
+ read-write
+ 0X00000000
+
+
+ ENABLE
+ Counter enable
+ 0
+ 1
+
+
+ TICKINT
+ SysTick exception request
+ enable
+ 1
+ 1
+
+
+ CLKSOURCE
+ Clock source selection
+ 2
+ 1
+
+
+ COUNTFLAG
+ COUNTFLAG
+ 16
+ 1
+
+
+
+
+ RVR
+ RVR
+ SysTick reload value register
+ 0x4
+ 0x20
+ read-write
+ 0X00000000
+
+
+ RELOAD
+ RELOAD value
+ 0
+ 24
+
+
+
+
+ CVR
+ CVR
+ SysTick current value register
+ 0x8
+ 0x20
+ read-write
+ 0X00000000
+
+
+ CURRENT
+ Current counter value
+ 0
+ 24
+
+
+
+
+ CALIB
+ CALIB
+ SysTick calibration value
+ register
+ 0xC
+ 0x20
+ read-write
+ 0X00000000
+
+
+ TENMS
+ Calibration value
+ 0
+ 24
+
+
+ SKEW
+ SKEW flag: Indicates whether the TENMS
+ value is exact
+ 30
+ 1
+
+
+ NOREF
+ NOREF flag. Reads as zero
+ 31
+ 1
+
+
+
+
+
+
+ SCB
+ System control block
+ SCB
+ 0xE000ED00
+
+ 0x0
+ 0x41
+ registers
+
+
+
+ CPUID
+ CPUID
+ CPUID base register
+ 0x0
+ 0x20
+ read-only
+ 0x410FC241
+
+
+ Revision
+ Revision number
+ 0
+ 4
+
+
+ PartNo
+ Part number of the
+ processor
+ 4
+ 12
+
+
+ Architecture
+ Reads as 0xF
+ 16
+ 4
+
+
+ Variant
+ Variant number
+ 20
+ 4
+
+
+ Implementer
+ Implementer code
+ 24
+ 8
+
+
+
+
+ ICSR
+ ICSR
+ Interrupt control and state
+ register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ VECTACTIVE
+ Active vector
+ 0
+ 9
+
+
+ RETTOBASE
+ Return to base level
+ 11
+ 1
+
+
+ VECTPENDING
+ Pending vector
+ 12
+ 7
+
+
+ ISRPENDING
+ Interrupt pending flag
+ 22
+ 1
+
+
+ PENDSTCLR
+ SysTick exception clear-pending
+ bit
+ 25
+ 1
+
+
+ PENDSTSET
+ SysTick exception set-pending
+ bit
+ 26
+ 1
+
+
+ PENDSVCLR
+ PendSV clear-pending bit
+ 27
+ 1
+
+
+ PENDSVSET
+ PendSV set-pending bit
+ 28
+ 1
+
+
+ NMIPENDSET
+ NMI set-pending bit.
+ 31
+ 1
+
+
+
+
+ VTOR
+ VTOR
+ Vector table offset register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TBLOFF
+ Vector table base offset
+ field
+ 7
+ 25
+
+
+
+
+ AIRCR
+ AIRCR
+ Application interrupt and reset control
+ register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ VECTCLRACTIVE
+ VECTCLRACTIVE
+ 1
+ 1
+
+
+ SYSRESETREQ
+ SYSRESETREQ
+ 2
+ 1
+
+
+ ENDIANESS
+ ENDIANESS
+ 15
+ 1
+
+
+ VECTKEYSTAT
+ Register key
+ 16
+ 16
+
+
+
+
+ SCR
+ SCR
+ System control register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SLEEPONEXIT
+ SLEEPONEXIT
+ 1
+ 1
+
+
+ SLEEPDEEP
+ SLEEPDEEP
+ 2
+ 1
+
+
+ SEVEONPEND
+ Send Event on Pending bit
+ 4
+ 1
+
+
+
+
+ CCR
+ CCR
+ Configuration and control
+ register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NONBASETHRDENA
+ Configures how the processor enters
+ Thread mode
+ 0
+ 1
+
+
+ USERSETMPEND
+ USERSETMPEND
+ 1
+ 1
+
+
+ UNALIGN__TRP
+ UNALIGN_ TRP
+ 3
+ 1
+
+
+ DIV_0_TRP
+ DIV_0_TRP
+ 4
+ 1
+
+
+ BFHFNMIGN
+ BFHFNMIGN
+ 8
+ 1
+
+
+ STKALIGN
+ STKALIGN
+ 9
+ 1
+
+
+
+
+ SHPR2
+ SHPR2
+ System handler priority
+ registers
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_11
+ Priority of system handler
+ 11
+ 24
+ 8
+
+
+
+
+ SHPR3
+ SHPR3
+ System handler priority
+ registers
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_14
+ Priority of system handler
+ 14
+ 16
+ 8
+
+
+ PRI_15
+ Priority of system handler
+ 15
+ 24
+ 8
+
+
+
+
+
+ TIM7 0x40001400 USART3 0x40004800
+
\ No newline at end of file